Chapter 1: Introduction

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1.

INTRODUCTION

As the technology is scaling down the demand for low voltage low power efficient circuits that can be implemented in portable battery operated devices has lead to development and use of current mode circuits rather than their voltage mode counterparts. Current-mode circuits are very useful in analog signal processing. A useful function block for high-frequency current-mode applications is a current conveyor. The current conveyor presents an alternative method of implementing analog system which traditionally has been used on op-amp. Current conveyor in many design cases is far better in performance, gain, bandwidth than traditional op-amp [paper1]. 1.1 OBJECTIVE OF THE THESIS WORK

1.2 Motivation for current mode filter design

1.1 MOTIVATION: With the reduction in the supply voltage and device threshold voltage of CMOS technology, the performance of voltage-mode circuits has been greatly affected which results in a reduced dynamic range, reduced voltage swing, increased propagation delay and low noise margins. The influence of supply voltage reduction on the performance of current-mode circuits, however, is less severe as compared with that of voltage-mode circuits. This is because the design emphasis of current-mode circuits is on branch currents rather than nodal voltages. The usefulness of CMOS current-mode circuits in overcoming the difficulties arising from the reduction of the supply voltage and the increase in the operation speed has received an increasing attention from the industry [4]. Current Conveyors represent the emerging class of high performance analog circuit design based on current-mode approach. They have simple structure, wide bandwidth and capability to operate at low voltages. Current conveyors are unity gain active elements exhibiting higher linearity, wider dynamic range and better high frequency performance. A current conveyor can function like voltage mode operational amplifier, thus can be used as effective alternative to the same op-amp for analog circuit design [LVLPCMOS CC book ferri,guerrini]

1.3 CONTRIBUTION AND ORGANIZATION OF THESIS Main contributions of this thesis are: Design and simulation of CMOS VCOs by the use of two circuit techniques.

Chapter 1: Introduction
voltage-frequency plot. Selection of VCO for pacemaker application. Design of a low frequency VCO for pacemaker application. The thesis report is organized into six chapters. The chapter wise detail is given below:

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Comparative study of CMOS VCOs, based on their linearity, which is observed from

Chapter 1: In this chapter, the objective of the thesis work is presented .The Design Methodology and EDA Tools used. Chapter 2: This chapter presents introduction of pacemaker and the need of VCO in it. Chapter 3: In this chapter, basic theory of Oscillators and its types are discussed. Chapter 4: In this chapter, Literature Review is presented. Chapter 5: In this chapter, brief introduction to the MENTOR GRAPHICS tool is presented. Chapter 6: This chapter discusses the design and comparison of CMOS VCOs with results of the schematic and layout simulations. It also presents the design of VCO for pacemaker application. Chapter 7: This chapter presents the conclusion of the work done and future scope.

1.3 DESIGN METHODOLOGY AND EDA TOOLS USED The design flow shown in figure 1 is typically used by a CMOS IC designer .In any design, specifications are written first. Specifications describe abstractly the circuit inputs, outputs, interfaces and functionality. The CMOS circuit design process consists of defining circuit specification, hand calculations and schematics. After that simulations of circuit is performed and checkout whether it meets design specification. If the circuit meets specification then the layout engineer makes layout of circuit. It is extremely important that the engineer be able to layout a chip and understands the parasitics involved in the layout. Then circuit will be again simulated with parasitics. This step is called post layout simulation. And again checkout whether it meets design specification. If the circuit meets specification finally sent for the fabrication and testing. Again specification is checkout and last sent for the mask production.

Chapter 1: Introduction

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Figure 1: Flow chart for the CMOS IC design process

THE SOFTWARE AND EDA TOOLS USED Operating System Tools Design Architect IC Station Windows, Linux MENTOR GRAPHICS ELDO SPICE SIMULATOR SDL, DRC, LVS & PEX

The Current conveyors are unity gain active element exhibiting high linearity, wide dynamic range and high frequency performance than their voltage mode counterparts. A current-mode approach is not just restricted to current processing, but also offers certain important advantages when

Chapter 1: Introduction
interfaced to voltage-mode circuits.

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1. INTRODUCTION
Current-mode circuits are very useful in analog signal processing. A useful function block for high-frequency current-mode applications is a current conveyor. The current conveyor presents an alternative method of implementing analog system which traditionally has been used on opamp. Current conveyor in many design cases is far better in performance, gain, bandwidth than traditional op-amp.

1.2 PROBLEM STATEMENT: The current-mode design technique is a good alternative for the high performance analog circuit design as it offers voltage independent high bandwidth. In current-mode design, the stress is more on the current levels for the operation of the circuits and the voltage levels at various nodes are immaterial. In voltage-mode circuits (VMCs), such as operational amplifiers (op amp), the performance of the circuit is determined in terms of voltage levels at various nodes including the input and the output nodes. But all these circuits suffer from the following disadvantages: 1. Output voltage cannot change instantly when there is a sudden change in the input voltage due to stray and other circuit capacitances. 2. Bandwidth of the op amp based circuits is usually low because of finite unity gain bandwidth. 3. Slew rate is dependent on the time constants associated with the circuit. 4. Circuits do not have high voltage swings. 5. Require higher supply voltages for better signal-to-noise ratio. Therefore, VMCs are not suitable for high frequency applications. When the signal is conveyed as a current, the voltages in MOS transistor circuits are proportional to the square root of the signal, if the devices are assumed to be operating in saturation region. Therefore, a compression of voltage signal swing and a reduction of supply voltage are possible. However, as a result of the device mismatches, this non-linear operation may generate an excessive amount of distortion and cannot be used for the applications where high linearity is required. Thus, linearization techniques are utilized in current-mode circuits to reduce the nonlinearity of the transistor transconductance and in this case the voltage signal swing is also not reduced. 1.3 OBJECTIVE OF DISSERTATION: The objective of the proposed dissertation is to design high gain, high bandwidth op-amp using current conveyor (CC-II) configuration. The designed op-amp is then compared

Chapter 1: Introduction

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with conventional op-amp using voltage mode approach, the comparison parameters are slew rate, CMRR, gain, bandwidth and propagation delay. The proposed CC-II based opamp is then used to design instrumentation amplifier to achieve better CMRR and high frequency performance.