Operator Precedence 1. 2. 3. 4. 5. 6.

Unary,Mul,Div Add, Sub, Shift Relation, Equality Reduction Logic Conditional

timing controls delay bases event based level sensitive 1. module clk_gen(); reg clk, reset; initial begin $monitor("TIME=%g RESET=%b CLOCK=%b",$time,reset,clk); clk=0; reset=0; #2 reset=1; #5 reset=0; #10 $finish; end always #1 clk=!clk; endmodule 2. module intra_assign(); reg a,b; initial begin; $monitor("TIME=%g A=%b B=%b",$time,a,b); a=1; b=0; a=#10 0; b=a; #20 $display("TIME=%g RESET=%b CLOCK=%b",$time,reset,clk); $finish end endmodule 3. intial begin x=0; y=0; end initialbegin #0 x=1; #0 y=1; 4.module edge_wait(); reg enable,clk,trigger; always @(posedge enable0 begin trigger=0; repeat(5) begin@(posedge clk) end trigger=1; end initial begin

$monitor("TIME=%g CLK=%b", $time,clk0; clk=0; enable=0; # 5 enable=1; #1 enable=0; #10 enable=1 #1 enable=0; #10 $finish end endmodule 5. event received_data; always @(posedge clock) begin if(last_data_pocket) if(received_data) end always @(received_data) always @(resetorclockord) always wait(count_enable)#20 count=count+1;