Digital Logic Design Combinational Logic: Mustafa Kemal Uyguroğlu

Digital Logic Design
Combinational Logic
Mustafa Kemal Uygurolu
Combinational Circuits
Output is function of input only
i.e. no feedback
n inputs
m outputs
When input changes, output may change (after a delay)

Eastern Mediterranean University
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Analysis
Given a circuit, find out its function
Function may be expressed as:
Boolean function
A B C A B C A B A C B C F2 F1
? ?
Truth table
Design
Given a desired function, determine its circuit Function may be expressed as:
Boolean function Truth table
?
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Analysis Procedure
Boolean Expression Approach
A B C A B C A B A C B C
F2=AB+AC+BC
F1
T2=ABC T1=A+B+C T3=AB'C'+A'BC'+A'B'C
F2=(A+B)(A+C)(B+C)
F2
F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
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Analysis Procedure
Truth Table Approach
A =0 B =0 C =0 A =0 B =0 C =0 A =0 B =0 A =0 C =0 B =0 C =0
A B C 0 0 0
F1
F1 0
F2 0
0 1 0 0 0 0
F2
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Analysis Procedure
A =0 B =0 C =1 A =0 B =0 C =1 A =0 B =0 A =0 C =1 B =0 C =1
F1
A B C 0 0 0 0 0 1
F1 0 1
F2 0 0
1 1 0 0 0 0
F2
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Analysis Procedure
A =0 B =1 C =0 A =0 B =1 C =0 A =0 B =1 A =0 C =0 B =1 C =0
F1
A 0 0 0
B 0 0 1
C 0 1 0
F1 0 1 1
F2 0 0 0
1 1 0 0 0 0
F2
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Analysis Procedure
A =0 B =1 C =1 A =0 B =1 C =1 A =0 B =1 A =0 C =1 B =1 C =1
F1
1 0 0 0 1 1
A 0 0 0 0
B 0 0 1 1
C 0 1 0 1
F1 0 1 1 0
F2 0 0 0 1
F2
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Analysis Procedure
A =1 B =0 C =0 A =1 B =0 C =0 A =1 B =0 A =1 C =0 B =0 C =0
F1
1 1 0 0 0 0
A 0 0 0 0 1
B 0 0 1 1 0
C 0 1 0 1 0
F1 0 1 1 0 1
F2 0 0 0 1 0
F2
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Analysis Procedure
A =1 B =0 C =1 A =1 B =0 C =1 A =1 B =0 A =1 C =1 B =0 C =1
F1
1 0 0 1 0 1
A 0 0 0 0 1 1
B 0 0 1 1 0 0
C 0 1 0 1 0 1
F1 0 1 1 0 1 0
F2 0 0 0 1 0 1
F2
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Analysis Procedure
A =1 B =1 C =0 A =1 B =1 C =0 A =1 B =1 A =1 C =0 B =1 C =0
F1
1 0 1 0 0 1
A 0 0 0 0 1 1 1
B 0 0 1 1 0 0 1
C 0 1 0 1 0 1 0
F1 0 1 1 0 1 0 0
F2 0 0 0 1 0 1 1
F2
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Analysis Procedure
A =1 B =1 C =1 A =1 B =1 C =1 A =1 B =1 A =1 C =1 B =1 C =1
F1
1 0 1 1 1 1
F2
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
F1 0 1 1 0 1 0 0 1
F2 0 0 0 1 0 1 1 1
B 0 A 1 1 0 C 0 1 1 0 A 0 0 0 1 C 1 1
B 0 1
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
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Design Procedure
Given a problem statement:
Determine the number of inputs and outputs
Derive the truth table Simplify the Boolean expression for each output
Produce the required circuit
Example:
Design a circuit to convert a BCD code to Excess 3 code
4-bits 0-9 values
4-bits Value+3
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Design Procedure
BCD-to-Excess 3 Converter
A B 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 w 0 0 0 0 0 1 1 1 1 1 x x x x x x x 0 1 1 1 1 0 0 0 0 1 x x x x x x y 1 0 0 1 1 0 0 1 1 0 x x x x x x z 1 0 1 0 1 0 1 0 1 0 x x x x x x
1 x 1 1 x x
C
1 1 x x 1 x x
C
1 x x
x 1
B A
1 x
x 1
w = A+BC+BD
C
1 1 x 1 1 1 x x
x = BC+BD+BCD
C
x x
B
A
1 1 x 1
x x
1 1 x x
D y = CD+CD
D z = D
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Design Procedure
BCD-to-Excess 3 Converter
A B 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 w 0 0 0 0 0 1 1 1 1 1 x x x x x x x 0 1 1 1 1 0 0 0 0 1 x x x x x x y 1 0 0 1 1 0 0 1 1 0 x x x x x x z 1 0 1 0 1 0 1 0 1 0 x x x x x x
A
x
B
y z
w = A + B(C+D) x = B(C+D) + B(C+D)
y = (C+D) + CD z = D
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Seven-Segment Decoder
a
w 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 abcdefg 1111110 0110000 1101101 1111001 0110011 1011011 1011111 1110000 1111111 1111011 xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx
w x y z
?
BCD code
y
1 x 1 1 x 1 1 1 x x 1 1 x x
a b c d e f g
f e
d
b c
z a = w + y + xz + xz
b=... c=... d=...
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Binary Adder
Half Adder
Adds 1-bit plus 1-bit
Produces Sum and Carry x y 0 0 1 1 0 1 0 1 C 0 0 0 1 S 0 1 1 0
x y
HA x + y C S
S C
x y
S C
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Binary Adder
Full Adder
Adds 1-bit plus 1-bit plus 1-bit
Produces Sum and Carry x y 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 z 0 1 0 1 0 1 0 1
x y z
FA x + y + z C S
S C
C 0 0 0 1 0 1 1 1
S 0 1 1 0 1 0 0 1
y 0 x 1 1 0 0 1 1 0
z S = xy'z'+x'yz'+x'y'z+xyz = x y z y 0 0 1 0 x 0 1 1 1 z C = xy + xz + yz
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Binary Adder
Full Adder
x y z x y z x y z x y z
S = xy'z'+x'yz'+x'y'z+xyz = x y z C = xy + xz + yz
x y z
x y x z y z
S x y z C
x y
x z y z
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Binary Adder
Full Adder
x y z x S y z
HA
HA
S C
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Binary Adder
x3x2x1x0 y3y2y1y0 Carry Propagate Addition
Cy
Binary Adder
S3S2S1S0
C0
c3 c2 c1 . + x3 x2 x1 x0 + y3 y2 y1 y0 Cy S3 S2 S1 S0
x3 y3
x2 y2
x1 y1
x0 y0
0 FA
C4 C3
FA
C2
FA
C1
FA
S3
S2
S1
S0
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Binary Adder
Carry Propagate Adder
x7 x6 x 5 x4
y7 y6 y5 y4
x3 x2 x1 x 0
y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0 Cy
A3 A2 A1 A0 B3 B2 B1 B0
Cy
CPA
S3 S2 S1 S0
C0
CPA
S3 S2 S1 S0
C0
S7 S6 S5 S 4
S3 S2 S1 S0
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Carry propagation
When the correct outputs are available The critical path counts (the worst case) (A1, B1, C1) C2 C3 C4 (C5, S4) When 4-bits full-adder 8 gate levels (n-bits: 2n gate levels)
Figure 4.10 Full Adder with P and G Shown

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Parallel Adders
Reduce the carry propagation delay
Employ faster gates Look-ahead carry (more complex mechanism, yet faster)
Carry propagate: Pi = AiBi

Carry generate: Gi = AiBi Sum: Si = PiCi
Carry: Ci+1 = Gi+PiCi

C0 = Input carry C1 = G0+P0C0 C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0 C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0
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Carry Look-ahead Adder (1/2)

Logic diagram
Fig. 4.11 Logic Diagram of Carry Look-ahead Generator

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Carry Look-ahead Adder (2/2)

4-bit carry-look ahead adder
Propagation delay of C3, C2 and C1 are equal.
Fig. 4.12 4-Bit Adder with Carry Look-ahead

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BCD Adder
4-bits plus 4-bits
+ x3 x2 x1 x0 + y3 y2 y1 y0 Cy S3 S2 S1 S0
Operands and Result: 0 to 9

X +Y x3 x2 x1 x0 0+0 0 0 0 0 0+1 0 0 0 0 0+2 0 0 0 0 0+9 1+0 1+1 1+8 1+9 2+0 9+9 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 y3 y2 y1 y0 Sum 0 0 0 0 =0 0 0 0 1 =1 0 0 1 0 =2 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 =9 =1 =2 Cy 0 0 0 0 0 0 S3 S2 S1 S0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0
=9 0 =A 0 =2 0
Invalid Code
Wrong BCD Value
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1 0 0 1 = 12 1
0001 1000 Eastern Mediterranean University
BCD Adder
X +Y 9+0 9+1 9+2 9+3 9+4 9+5 9+6 9+7 9+8 9+9 x3 x2 x1 x0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 =9 = 10 = 11 = 12 = 13 = 14 = 15 = 16 = 17 = 18 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 =9 = 16 = 17 = 18 = 19 = 20 = 21 = 22 = 23 = 24
+6
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BCD Adder
Correct Binary Adders Output (+6)
If the result is between A and F
If Cy = 1
S3 S2 S1 S0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Err 0 0 0 1 1 1 1 1 1
1 1 1 1
S1 S2
S3
1 1
S0 Err = S3 S2 + S3 S1
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BCD Adder
x3 x2 x1 x0 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0 Cy Binary Adder Ci S3 S2 S1 S0
Err
A3 A2 A1 A0 B3 B2 B1 B0 Cy Binary Adder Ci S3 S2 S1 S0 Cy S3 S2 S1 S0
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Binary Subtractor
Use 2s complement with binary adder
x y = x + (-y) = x + y + 1
x3 x2 x1 x0 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 Cy Binary Adder S3 S2 S1 S0 F3 F2 F1 F0
B0 Ci
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Binary Adder/Subtractor
M: Control Signal (Mode)
M=0 F = x + y
M=1 F = x y
x3 x2 x1 x0
y3
y2
y1
y0
A3 A2 A1 A0 B3 B2 B1 Cy Binary Adder S3 S2 S1 S0 F3 F2 F1 F0
B0 Ci
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Overflow
Unsigned Binary Numbers x
3
x2 y2
x1 y1
y3
x0 y0
0
FA FA FA FA
Carry
C4
S3 x3 y3
C3
S2 x2 y2
C2
S1 x1 y1
C1
S0 x0 y0 0
2s Complement Numbers
FA
FA
FA
FA
Overflow
C4
S3
C3
S2
C2
S1
C1
S0
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Magnitude Comparator
Compare 4-bit number to 4-bit number
3 Outputs: < , = , >
Expandable to more number of bits
x3 A3 B3 A3 B3
A3A2A1A0 B3B2B1B0 Magnitude Comparator
x2 A2 B2 A2 B2
x1 A1 B1 A1 B1
x0 A0 B0 A0 B0
( A B) x3 x2 x1 x0 ( A B ) A3 B3 x3 A2 B2 x3 x2 A1 B1 x3 x2 x1 A0 B0 ( A B ) A3 B3 x3 A2 B2 x3 x2 A1 B1 x3 x2 x1 A0 B0
A<B A=B A>B
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A3 x3 B3 A2 x2 B2 A1 x1 B1 A0 x0 B0 (A=B)
(A<B)
(A>B)
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x7 x6 x 5 x4
y7 y6 y5 y4
x 3 x2 x1 x0
y3 y2 y1 y0
0 1 0
I(A>B) Magnitude I(A=B) Comparator I(A<B) A<B A=B A>B
A3 A2 A1 A0 B3 B2 B1 B0
I(A>B) Magnitude I(A=B) Comparator I(A<B) A<B A=B A>B
A3 A2 A1 A0 B3 B2 B1 B0
A<B A=B A>B
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Decoders
Extract Information from the code
Only one lamp will turn on
Binary Decoder
Example: 2-bit Binary Number
x1
x0 0
1 0 Binary Decoder 0 0
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Decoders
2-to-4 Line Decoder
I1 y3 y2 y1 y0 Binary Decoder
Y3 Y2 Y1 Y0
I0 I1 I0
0 0 1 1 0 1 0 1
Y3 Y2 Y1 Y0
0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0
I1 I0
Y3 I1 I 0
Y1 I1 I 0
Y2 I1 I 0 Y0 I1 I 0
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Decoders
3-to-8 Line Decoder
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
I2 I1 I0
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
I 2 I1 I 0
I 2 I1 I 0 I 2 I1 I 0 I 2 I1 I 0 I 2 I1 I 0 I 2 I1 I 0 I 2 I1 I 0 I 2 I1 I 0
I2 I1 I0
Binary Decoder
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Decoders
Enable Control
I1 I0 E E 0 1 1 1 1 I1 I0 x 0 0 1 1 x 0 1 0 1 Y3 Y2 Y1 Y0 Binary Decoder
Y3 Y2 Y1 Y0
Y3 Y2 Y1 Y 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
I1 I0 E
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Decoders
Expansion
I2 I1 I0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 I2 I1 I0
I0 I1 E
Y3 Y2 Y1 Y0 Y3 Y2 Y1 Y0
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
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I0 I1 E
Binary Decoder
Binary Decoder
Decoders
Active-High / Active-Low
I1 I0 Y 3 Y 2 Y 1 Y 0 0 0 1 1 0 1 0 1 0 0 0 1 Binary Decoder 0 0 1 0 Y3 Y2 Y1 Y0 0 1 0 0 1 0 0 0 I1 I0 Y 3 Y 2 Y 1 Y 0 0 0 1 1 0 1 0 1 Binary Decoder 1 1 1 0 Y3 Y2 Y1 Y0 1 1 0 1 1 0 1 1 0 1 1 1
Y3 Y2 Y1 Y0
I1 I0
I1 I0
I1 I0
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Implementation Using Decoders

Each output is a minterm
Binary Decoder
All minterms are produced

Sum the required minterms
x y z
Example: Full Adder S(x, y, z) = (1, 2, 4, 7) C(x, y, z) = (3, 5, 6, 7)
I2 I1 I0
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
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Implementation Using Decoders

Binary Decoder Binary Decoder
x y z
I2 I1 I0
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
x y z
I2 I1 I0
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
C
C
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Uses of decoders
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Encoders
Put Information into code
Only one switch should be activated at a time x3 x2 x1 y1 y0
Binary Encoder
Example: 4-to-2 Binary Encoder x1
x2
x3
Binary Encoder
y1
y0
0 0 0 1
0 0 1 0
0 1 0 0
0 0 1 1
0 1 0 1
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Encoders
Octal-to-Binary Encoder (8-to-3)
I7 0 0 0 0 0 0 0 1 I6 0 0 0 0 0 0 1 0 I5 0 0 0 0 0 1 0 0 I4 0 0 0 0 1 0 0 0 I3 0 0 0 1 0 0 0 0 I2 0 0 1 0 0 0 0 0 I1 0 1 0 0 0 0 0 0 I0 1 0 0 0 0 0 0 0 Y2 Y1 Y0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 I7 I6 I5 I4 I3 I2 I1 I0
Binary Encoder
Y2 Y1 Y0
Y2 I 7 I 6 I 5 I 4 Y1 I 7 I 6 I 3 I 2 Y0 I 7 I 5 I 3 I1
I7 I6 I5 I4 I3 I2 I1 I0
Y2
Y1
Y0
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Priority Encoders
4-Input Priority Encoder
I3 I2 I1 I0 0 0 0 0 1
Y1
0 0 0 1 x
I1
0 0 1 x x
0 1 x x x
Y1 Y0 V 0 0 0 0 0 1 0 1 1 1 0 1 1 1 1
I3 I2 I1 I0
Priority Encoder
V Y1 Y0
I3 I2 I1
Y0
Y1 I 3 I 2
I2
1 1 1 1
Y1 I0 V
I3
1 1 1 1
Y0 I 3 I 2 I1 V I 3 I 2 I1 I 0
1 1 1 1
I0
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Encoder / Decoder Pairs

Binary Encoder
I7 I6 I5 I4 I3 I2 I1 I0
Binary Decoder
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Y2 Y1 Y0
I2 I1 I0
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Multiplexers
S1 S0
0 0 1 1
0 1 0 1
I0 I1 I2 I3
I0 I1 MUX Y I2 I3 S1 S0
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Multiplexers
2-to-1 MUX
I0
I0 MUX Y I1 S
Y I1 S
4-to-1 MUX
I0 I1 I2 I3 Y
S1
S0
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Multiplexers
Quad 2-to-1 MUX A
x3
3
Y3 A2
y3
I0 MUX Y I1 S
I0 MUX Y I1 S I0 MUX Y I1 S I0 MUX Y I1 S S
Y2 A1 A0 B3 B2 B1 Y1 Y0
x2
y2
x1
y1
B0
A3 A2 A1 A0
x0
y0
Y3 Y MUX 2 Y1 B3 Y0 B2 B1 B0 S E
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Multiplexers
Quad 2-to-1 MUX
A3 Y3 A2 Y2 A1 A0 B3 B2 B1 B0 Y1 Y0
A3 A2 A1 A0
Y3 Y2 MUX Y1 B3 Y0 B2 B1 B0 S E
Extra Buffers
S E
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Implementation Using Multiplexers

Example F(x, y) = (0, 1, 3)
x y 0 0 1 1 0 1 0 1 F 1 1 0 1 1 1 0 1 I0 I1 MUX Y I2 I3 S1 S0
x y
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Example F(x, y, z) = (1, 2, 6, 7)
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F 0 1 1 0 0 0 1 1
0 1 1 0 0 0 1 1
I0 I1 I2 I3 Y I4 MUX I5 I6 I7 S2 S1 S0
x y z
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Example F(x, y, z) = (1, 2, 6, 7)
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F 0 1 1 0 0 0 1 1
F=z F=z F=0 F=1
z z 0 1
x y
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Example F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1
F=D F=D F=D F=0 F=0
D D D 0 0 D 1 1
F=D
F=1 F=1
I0 I1 I2 I3 Y MUX I4 I5 I6 I7 S2 S1 S0 A B C
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Multiplexer Expansion
8-to-1 MUX using Dual 4-to-1 MUX
I0 I1 I2 I3
I0 I1 MUX Y I2 I3 S1 S0 I0 I1 MUX Y I2 I3 S1 S0
I4 I5 I6 I7
I0 MUX Y I1 S
1 0 0 S2 S1 S0 Eastern Mediterranean University
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DeMultiplexers
Y3 Y2 I DeMUX Y 1 S S Y0
1 0
Y3 Y2 I Y1 Y0
S1 S0
0 0 1 1 0 1 0 1
Y3 Y2 Y1 Y0
0 0 0 I 0 0 I 0 0 I 0 0 I 0 0 0
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S1 S0
Multiplexer / DeMultiplexer Pairs

MUX I7 I6 I5 I4 I3 I2 I1 I0 DeMUX Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
S2 S1 S0 Synchronize
S2 S1 S0
x2 x1 x0
y2 y1 y0
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DeMultiplexers / Decoders
Y3 Y2 I DeMUX Y 1 S S Y0
1 0
I1 I0 E
Y3 Y2 Y1 Y0
E
S1 S0 0 0 1 1 0 1 0 1 Y3 Y2 Y1 Y0 0 0 0 I 0 0 I 0 0 I 0 0 I 0 0 0 0 1 1 1 1
I1 I0
x 0 0 1 1 x 0 1 0 1
Binary Decoder 0 0 0 0 1 0 0 0 1 0
Y 3 Y2 Y1 Y0
0 0 1 0 0 0 1 0 0 0
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Three-State Gates
Tri-State Buffer
C A A Y 0 x 1 0 1 1 A Y Hi-Z 0 1 Y
Tri-State Inverter
C
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Three-State Gates
A C B Y C D 0 0 1 1 0 1 0 1 Y Hi-Z B A ? Not Allowed A
D C
Y= B
A
B
if C = 1
if C = 0
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Three-State Gates
I3
I2
Y I1
I0 S1 S0 E I1 I0 E Y3 Y2 Y1 Y0
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Binary Decoder
Binary multiplication
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2-bit by 2-bit
Binary Multiplication
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Digital Logic Design Combinational Logic: Mustafa Kemal Uyguroğlu

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Digital Logic Design Combinational Logic: Mustafa Kemal Uyguroğlu

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Digital Logic Design

Mustafa Kemal Uygurolu

When input changes, output may change (after a delay)

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Produce the required circuit

Eastern Mediterranean University

b=... c=... d=...

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Figure 4.10 Full Adder with P and G Shown

Carry propagate: Pi = AiBi

Carry: Ci+1 = Gi+PiCi

Carry Look-ahead Adder (1/2)

Fig. 4.11 Logic Diagram of Carry Look-ahead Generator

Carry Look-ahead Adder (2/2)

Fig. 4.12 4-Bit Adder with Carry Look-ahead

Operands and Result: 0 to 9

0001 1000 Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

A3A2A1A0 B3B2B1B0 Magnitude Comparator

A<B A=B A>B

I(A>B) Magnitude I(A=B) Comparator I(A<B) A<B A=B A>B

I(A>B) Magnitude I(A=B) Comparator I(A<B) A<B A=B A>B

A<B A=B A>B

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Implementation Using Decoders

All minterms are produced

Example: Full Adder S(x, y, z) = (1, 2, 4, 7) C(x, y, z) = (3, 5, 6, 7)

Eastern Mediterranean University

Implementation Using Decoders

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Encoder / Decoder Pairs

Eastern Mediterranean University

Eastern Mediterranean University

Eastern Mediterranean University

Implementation Using Multiplexers

Eastern Mediterranean University

Implementation Using Multiplexers

Eastern Mediterranean University

Implementation Using Multiplexers

F=z F=z F=0 F=1

Eastern Mediterranean University

Implementation Using Multiplexers