TCITSMCN40GGPMPLLA1_specs

*** True Circuits, Inc. Confidential ***

General-Purpose PLL Specifications:

- Divided reference frequency range
13.3MHz - 1.7GHz
- /1 output frequency range
340MHz - 1.7GHz
(VCO output internally divided by 2 for 50% DC)
- Reference divider values
1-16
- Feedback divider values
1-64
- Output divider values
1-16
- /1 output multiples of div. reference
1-64
- Bandwidth adjustment div. range
1-64
- Feedback signal delay (max)
NF/1.7GHz
- Output duty cycle (nom, tol)
50%, +/-2%
- Static phase error (max)
+/-1.25% div. reference cycle
- Period jitter (P-P) (max)
+/-3% output cycle
- Input-to-output jitter (P-P) (max)
+/-1.5% div. reference cycle
(jitter numbers are worst-case estimates with supply and
substrate noise levels below -- actual results will be better)
-

Power dissipation (nom)

Reset pulse width (min)
Reset /1 output frequency range
Lock time (min allowed)
(actual lock time will be much smaller)
- Freq. overshoot (full-/half-) (max)
- Area (including isolation) (max)

2.5mA @ 850MHz (/1 output)

5us
10MHz - 100MHz
500 div. reference cycles

1 VDDA, 1 VSSA (preferred)

10% VDDA
10% VDDA
2% div. reference cycle
150ps

Number of PLL supply pkg. pins

Low freq. supply noise est. (P-P) (max)
Low freq. sub. noise est. (P-P) (max)
Ref. input jitter (long-term, P-P) (max)
Reference/Feedback H/L pulse width (min)

- Process technology
- Supply voltage (VDD, VDDA) (nom, tol)
- Junction temperature (nom, min, max)
- Pin list:
- VDDA
- VSSA
- VDD
- VSS
- RCLK
- FCLK
- CLKOUT
- CLKR[0:3]
- CLKF[0:5]
- CLKOD[0:3]
- BWADJ[0:5]
- RESET
- PWRDN
- INTFB
own in diagrams below)
- BYPASS
- TEST
- RFSLIP
- FBSLIP

40%/50%
0.020mm^2

TSMC CLN40G 40nm

0.9V, +/-10%
70C, -40C, 125C

Analog VDD
Analog VSS
Digital VDD (connected to core VDD)
Digital VSS (connected to core VSS)
Reference clock input
Feedback clock input
PLL clock output
NR = CLKR[3:0] + 1, CLKR[0] is LSB
NF = CLKF[5:0] + 1, CLKF[0] is LSB
OD = CLKOD[3:0] + 1, CLKOD[0] is LSB
Loop BW adj.: NB = BWADJ[5:0] + 1, BWADJ[0] is LSB
Reset when high (also clears NR and NF counters)
Power down when high
Select internal feedback path when high rather than FCLK (not sh

Reference-to-output bypass when high

Reference-to-counters-to-output bypass when high
Reference cycle slip output (CLKOUT frequency high)
Feedback cycle slip output (CLKOUT frequency low)

TCITSMCN40GGPMPLLA1_specs
- Simplified block diagrams:
- Normal/BYPASS Mode (TEST=0)
(The multiplexers for TEST mode are not shown.)
+-----------------------------------------------------------+
|
|
|
+-----+
+-----+
+-----+
|
FCLK --|---->|
|----->|
|
|
|
+-----+ 0|\
|
|
| /NF |
| PFD | ... | VCO |----->|
|-->| |---|-CLKOUT
CLKF --|-/-->|
| /-->|
|
|
|
| /OD |
| |
|
| 6
+-----+ |
+-----+
+-----+ /-->|
|
| |
|
|
|
|
+-----+
| |
|
|
|
|
1| |
|
| /------------C------------------------C------------>| |
|
| |
|
|
|/
|
| |
+-----+ |
|
^
|
RCLK --|-+-->|
|--/
|
|
|
|
| /NR |
|
|
|
CLKR --|-/-->|
|
|
|
|
| 4
+-----+
|
|
|
|
|
|
|
CLKOD--|-/-------------------------------------/
|
|
| 4
|
|
|
|
|
BWADJ--|-/-- ...
|
|
| 6
|
|
|
|
|
RESET--|-- ...
|
|
|
|
|
PWRDN--|-- ...
|
|
|
|
|
BYPASS-|------------------------------------------------------/
|
|
|
TEST --|-- (=0)
... --|-RFSLIP
|
|
VDDA --|
... --|-FBSLIP
|
|
VSSA --|
|
|
|
VDD --|
|
|
|
VSS --|
|
+-----------------------------------------------------------+

TCITSMCN40GGPMPLLA1_specs
- TEST Mode (TEST=1)
(When NR=1, NF=1, or OD=1, outputs do not toggle.)
+-----------------------------------------------------------+
|
|
|
|
|
|
|
+-----+
|
FCLK --|-- ...
/------>|
|
+-----+
|
|
|
| /NF |----------------->|
|---------|-CLKOUT
CLKF --|-/--------/
/-->|
|
| /OD |
|
| 6
|
+-----+
/-->|
|
|
|
|
|
+-----+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-----+ |
|
|
RCLK --|---->|
|--/
|
|
|
| /NR |
|
|
CLKR --|-/-->|
|
|
|
| 4
+-----+
|
|
|
|
|
CLKOD--|-/-------------------------------------/
|
| 4
|
|
|
BWADJ--|-/-- ...
|
| 6
|
|
|
RESET--|-- ...
|
|
|
PWRDN--|-- ...
|
|
|
BYPASS-|-- ...
|
|
|
TEST --|-- (=1)
... --|-RFSLIP
|
|
VDDA --|
... --|-FBSLIP
|
|
VSSA --|
|
|
|
VDD --|
|
|
|
VSS --|
|
+-----------------------------------------------------------+