library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity squre is
Port ( clk,rst : in STD_LOGIC;
hs,vs,rout,bout,gout : out STD_LOGIC);
end squre;
architecture Behavioral of squre is
signal hcount,vcount: std_logic_vector(9 downto 0);
signal rin,gin,bin :std_logic;
signal hsy,vsy,hvv,vvv,temp:std_logic;
signal s: std_logic_vector(1 downto 0);
begin
process(clk,rst)
begin
if rst='1' then
s<="00";
elsif clk'event and clk='1' then
s<=s+"01";
if s="11" then
s<= not s;
end
end
end
temp

if;
if;
process;
<=s(0) ;

process(temp)
begin
if rst='1' then
hsy<='0';
vsy<='0';
hcount<="0000000000";
vcount<="0000000000";
elsif temp'event and temp='1' then
if hcount= 808 then
hcount<="0000000000";
if vcount=527 then
vcount<="0000000000";
else vcount<= vcount +'1';
end if;
else
hcount<=hcount+'1';
end if;

end if;
if hcount > 664 and hcount <= 760 then
hsy<='0';
else
hsy<='1';
end if;
if vcount > 482 and vcount <= 484 then
vsy<='0';
else
vsy<='1';
end if;
if hcount>0 and hcount<160 and vcount>0 and vcount<120 then
hvv<='1';
vvv<='1';
rin<='0';
gin<='0';
bin<='0';
elsif hcount>160 and hcount<320 and vcount>0 and vcoun
t<120 then
hvv<='1';
vvv<='1';
rin<='1';
gin<='1';
bin<='1';
elsif hcount>320 and hcount<480 and vcount>0 and vcoun
t<120 then
hvv<='1';
vvv<='1';
rin<='0';
gin<='0';
bin<='0';
elsif hcount>480 and hcount<640 and vcount>0 and vcount<120 then
hvv<='1';
vvv<='1';
rin<='1';
gin<='1';
bin<='1';
elsif hcount>0 and hcount<160 and vcount>120 and vcount<240 then
hvv<='1';
vvv<='1';
rin<='1';
gin<='1';
bin<='1';
elsif hcount>160 and hcount<320 and vcount>120 and vco
unt<240 then
hvv<='1';
vvv<='1';
rin<='0';
gin<='0';
bin<='0';
elsif hcount>320 and hcount<480 and vcount>120 and vco
unt<240 then
hvv<='1';

vvv<='1';
rin<='1';
gin<='1';
bin<='1';
elsif hcount>480 and hcount<640 and vcount>120 and vcount<240 then
hvv<='1';
vvv<='1';
rin<='0';
gin<='0';
bin<='0';
elsif hcount>0 and hcount<160 and vcount>240 and vcou
nt<360 then
hvv<='1';
vvv<='1';
rin<='0';
gin<='0';
bin<='0';
elsif hcount>160 and hcount<320 and vcount>240 and vco
unt<360 then
hvv<='1';
vvv<='1';
rin<='0';
gin<='0';
bin<='0';
elsif hcount>320 and hcount<480 and vcount>240 and vco
unt<360 then
hvv<='1';
vvv<='1';
rin<='1';
gin<='1';
bin<='1';
elsif hcount>480 and hcount<640 and vcount>240 and vco
unt<360 then
hvv<='1';
vvv<='1';
rin<='0';
gin<='0';
bin<='0';
elsif hcount>0 and hcount<160 and vcount>360 and vcoun
t<480 then
hvv<='1';
vvv<='1';
rin<='1';
gin<='1';
bin<='1';
elsif hcount>160 and hcount<320 and vcount>360 and vco
unt<480 then
hvv<='1';
vvv<='1';
rin<='0';
gin<='0';
bin<='0';
elsif hcount>320 and hcount<480 and vcount>360 and vco
unt<480 then
hvv<='1';
vvv<='1';
rin<='1';
gin<='1';
bin<='1';

elsif hcount>480 and hcount<640 and vcount>360 and vco

unt<480 then
hvv<='1';
vvv<='1';
rin<='0';
gin<='0';
bin<='0';
end if;

hs<=hsy;
vs<=vsy;
rout<=rin and hvv and vvv;
gout<=gin and hvv and vvv;
bout<=bin and hvv and vvv;
end process;
end Behavioral;