Part b) Clamping Circuits AIM: To study the working of positive and negative clampers (with and without DC bias).

COMPONENTS REQUIRED: Diode (IN !!")# $esistors #capacitors # DC regulated power supply# %ignal generator# DESIGN: &or proper clamping# ' ("!!T where T is the time period of input waveform If fre)uency is " k*+ with peak,peak input voltage of "!-# T."ms ' . $.C."!!/T . "!!ms 0et C."1& $0. "!!k2 %elect C ."u& and $0 ."!! k2 CIRCUIT DIAGRAM AND O SER!ATIONS "#P$siti%& Clamp&r at '!
1u Vin C1 V1 1N4001 D1 v out

3. Negative clamper at ! 1u Vin C1 V1 1N4001 D1 v out

4.5ositive Clamper at 64-

12 10

12.4V

1u Vin C1 V1 1N4001 D1
V

vout

v out

8 6 4
2.4V

Vin

3 V2

0 -2 -4 1 Time/mSecs 1.5 2 2.5 3 3.5 4 4.5 500uSecs/div

.5ositive Clamper at ,41u Vin C1 V1 1N4001 D1 -3 V2 v out

6.4V

4 vout 2 V

0 Vin -2
-3.6V

-4 1 Time/mSecs 1.5 2 2.5 3 3.5 4 4.5 5

500uSecs/div

7.Negative Clamper at 64-

1u Vin C1 V1 3 V2 v out 1N4001 D1

8.Negative Clamper at ,4T*9:$;

Vin 1u vout

The clamping network

1N4001 D1

C1

is one that will <clamp= a signal to a different DC level. The network must have a capacitor# a diode and a resistive element# but it can also employ an independent

V1 3 V2

DC supply (-ref) to introduce an additional shift. The magnitude of $ and C must be chosen such

that time constant ' . $0C is large enough to ensure the voltage across capacitor does not discharge significantly during the interval of the diode is non,conducting. 5$:C9D>$9? ". @ake the connections as shown in circuit diagram 3. >sing a signal generator apply a sine wave input (-i) of peak,to,peak amplitude of "!- (and fre)uency of "Ah+) to the circuit. (%)uare wave can also be applied) 4. :bserve the clamped output waveform on C$: &or different values of -ref. . Aeep the C$: in D>B0 mode and DC mode. Blso the grounds of both the channels can be made to have the same level so that the shift in DC level of the output can be observed. 7. &or negative clampers reverse the directions of both diode and reference voltage. $9%>0T?