ECE420: DIGITAL VLSI DESIGN LABORATORY

Practical No.: 8 Roll No.:A15 AIM:- Write Date:-19-march-2014 Registration No.:11103674

a program in verilog to implement Flip-Flops

SR FLIP FLOP:-

module flipflopsr(s,r,reset,clk, q); input s,r,reset,clk; output q; reg q; always@(posedge clk) begin if(reset==1) q=0; else if(s==0&r==0) q=q; else if(s==0&r==1) q=0; else if(s==1&r==0) q=1; else if(s==1&r==1) q=1'bx; end endmodule

test bench:- `timescale 1ns / 1ps

module flipflop123_v; reg s; reg r; reg reset; reg clk; wire q; flipflopsr a(s,r,reset,clk, q); initial begin // Initialize Inputs

s = 0; r = 0; reset = 1; clk = 0; #5 s=0; r=1;reset=0; #5 s=1; r=0;reset=0; #5 s=1;r=1;reset=0; #5 $stop; end always begin #2 clk=~clk; end initial #20 $stop; endmodule

Simulation:-

RTL:-

J-K FLIP FLOP:module flipflopjk(j,k,reset,clk, q); input j,k,reset,clk; output q; reg q; always@(posedge clk) begin if(reset==1) q=0; else if(j==0&k==0) q=q; else if(j==0&k==1) q=0; else if(j==1&k==0) q=1; else if(j==1&k==1) q=~q; end endmodule TEST BENCH:`timescale 1ns / 1ps module flipflopjk123_v; reg j; reg k; reg reset;

reg clk; wire q; flipflopjk a(j,k,reset,clk, q); initial begin j = 0; k = 0; reset = 1; clk = 0; #5 j=0; k=1;reset=0; #5 j=1; k=0;reset=0; #5 j=1;k=1;reset=0; #5 $stop; end always begin #2 clk=~clk; end initial #20 $stop; endmodule SIMULATION:-

RTL:-

D-FLIP FLOP:module flipflopd(reset,d, q); input reset,d; output q; reg q; always@(posedge clk) begin if(reset==1) q=0; else if(d==0) q=0; else if(d==1) q=1; end endmodule TEST BENCH:-`timescale 1ns / 1ps module flipflopd123_v; reg reset; reg clk; reg d; wire q;

flipflopd a(reset,clk,d, q); initial begin reset=1; d=0;clk=0; #5 reset=0;d=1; end always begin #2 clk=~clk; end initial #20 $stop; SIMULATION:-

RTL:-

T-FLIPFLOP:module flipflopt(t,reset, q); input t,reset; output q; reg q; always@(posedge clk) begin if(reset==1) q=0; else if(t==0) q=q; else if(t==1) q=~q; end TEST BENCH:`timescale 1ns / 1ps module flipflopd123_v; // Inputs reg reset;

reg clk; reg t; // Outputs wire q; // Instantiate the Unit Under Test (UUT) flipflopt a(t,clk,reset, q); initial begin // Initialize Inputs reset=1; t=0;clk=0; #5 reset=0;t=1; end always begin #2 clk=~clk; end initial #20 $stop; Endmodule

SIMULATION:-

RTL:-

Learning Out Comes:Verilog most commonly used in the design and verification of digital circuits at the register transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits. And we learnt how to implement all logic gates in verilog. Result:- We are able to design flip flop in verilog. And learn about programming language.