Professional Documents
Culture Documents
ECE 3561 - Lecture 16 VHDL Testbenches For State Machines
ECE 3561 - Lecture 16 VHDL Testbenches For State Machines
ECE 3561 - Lecture 16 VHDL Testbenches For State Machines
More examples
Note trade off and difference in Mealy vs Moore implementation from simulation results
More examples
Consider the state machine we designed earlier for detecting an input that ends in the sequence 101. Developed both Mealy and Moore implementations.
ENTITY mealy101 IS PORT (clk,x : IN bit; z : OUT bit); END mealy101; ENTITY moore101 IS PORT (clk,x : IN bit; z : OUT bit); END moore101;
Copyright 2012 - Joanne DeGroat, ECE, OSU 4
ARCHITECTURE one OF mealy101 IS TYPE state_type IS (s0,s1,s2); SIGNAL state,next_state : state_type; BEGIN ARCHITECTURE one OF moore101 IS TYPE state_type IS (s0,s1,s2,s3); SIGNAL state,next_state : state_type; BEGIN
Copyright 2012 - Joanne DeGroat, ECE, OSU 5
--state elements mealy PROCESS BEGIN WAIT UNTIL clk='1' AND clk'event; state <= next_state; END PROCESS; --state elements moore PROCESS BEGIN WAIT UNTIL clk='1' AND clk'event; state <= next_state; END PROCESS;
Copyright 2012 - Joanne DeGroat, ECE, OSU 6
--next state logic mealy PROCESS (state,x) BEGIN CASE state IS WHEN s0 => IF (x='0') THEN next_state <= s0; ELSE next_state <= s1; END IF; WHEN s1 => IF (x='0') THEN next_state <= s2; ELSE next_state <= s1; END IF; WHEN s2 => IF (x='0') THEN next_state <= s0; ELSE next_state <= s1; END IF; END CASE; END PROCESS;
Copyright 2012 - Joanne DeGroat, ECE, OSU 7
PROCESS (state,x) BEGIN CASE state IS WHEN s0 => IF (x='0') THEN next_state <= s0; ELSE next_state <= s1; END IF; WHEN s1 => IF (x='0') THEN next_state <= s2; ELSE next_state <= s1; END IF; WHEN s2 => IF (x='0') THEN next_state <= s0; ELSE next_state <= s3; END IF; WHEN s3 => IF (x='0') THEN next_state <= s2; ELSE next_state <= s1; END IF; END CASE; END PROCESS;
-- output logic - mealy machine PROCESS (state,x) BEGIN CASE state IS WHEN s0 => z<='0'; WHEN s1 => z<='0'; WHEN s2 => IF (x='1') THEN z<='1'; ELSE z<= '0'; END IF; END CASE; END PROCESS;
Copyright 2012 - Joanne DeGroat, ECE, OSU 9
--output logic - Moore machine PROCESS (state) BEGIN CASE state IS WHEN s0 => z <= '0'; WHEN s1 => z <= '0'; WHEN s2 => z <= '0'; WHEN s3 => z <= '1'; END CASE; END PROCESS;
Copyright 2012 - Joanne DeGroat, ECE, OSU 10
Creating a testbench
As the testbench is the top unit there is no interface. Process within testbench generate stimulus and possibly check response and generate reports. ENTITY tb101 IS END tb101;
11
Declarations
ARCHITECTURE one OF tb101 IS --declare units to be tested COMPONENT mealy101 PORT (clk,x : IN bit; z : OUT bit); END COMPONENT; FOR all : mealy101 USE ENTITY work.mealy101(one); COMPONENT moore101 PORT (clk,x : IN bit; z : OUT bit); END COMPONENT; FOR all : moore101 USE ENTITY work.moore101(one);
12
Declarative Region
BOTH stimulus and response -- delcare input signals and input stream SIGNAL xs : BIT_VECTOR (1 to 30) := ('0','0','0','1','0','1','0','0','0','1','0','1','0','1','0','1', '0','0','0','1','0','1','1','0','1','1','1','0','1','0'); SIGNAL x,z1,z2 : BIT; SIGNAL clk : BIT :='1';
Copyright 2012 - Joanne DeGroat, ECE, OSU 13
Wire in DUT
Instantiate components
BEGIN --Instantiate units ml : mealy101 PORT MAP (clk,x,z1); mo : moore101 PORT MAP (clk,x,z2);
14
Set up clocks
50% duty cycle clock is easy as above More complex clocks can be set up
15
Use a process
PROCESS -- clk starts set high BEGIN clk <= 1; WAIT FOR 5 ns; -- time high clk <= 0; WAIT FOR 15 ns; --time low END PROCESS;
This is a 25% duty cycle clock the is high 25% of the period. Easy to adapt for any duty cycle and clock period.
Copyright 2012 - Joanne DeGroat, ECE, OSU 16
--Stimulus process PROCESS BEGIN WAIT FOR 1 ns; FOR i IN 1 to 30 LOOP x <= xs(i); WAIT FOR 10 ns; END LOOP; WAIT FOR 10 ns; WAIT; END PROCESS;
Process grabs inputs from the input vector set up in the declarative region. A good option when a simple sequence on a single signal. More advanced techniques may be needed for complex machines.
Copyright 2012 - Joanne DeGroat, ECE, OSU 17
18
Simulation result 2
19
Demo of simulation
A look at a live demonstration of Model Sim for simulation of this machine. Note that in Moore implementation output seems to be delayed ~1 clock.
20
Lecture summary
21