4017 decade counter

The 4017 IC is a 16-pin CMOS decade counter from the 4000 series. It takes clock pulses from the clock input, and makes one of the ten outputs come on in sequence each time a clock pulse arrives. Pinout

Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13

Name 6 2 1 3 7 8 4 0 V, VDD 9 5 10 CO LE The 6th sequential output The 2nd sequential output The 1st sequential output The 3rd sequential output The 7th sequential output The 8th sequential output The 4th sequential output The connection to the 0 V rail The 9th sequential output The 5th sequential output The 10th sequential output

Purpose

Carry out output - outputs high on counts 0 to 4, outputs low on counts 5 to 9 (thus a transition from low to high occurs when counting from 9 back to 0) Latch enable - latches on the current output when high (i.e. the chip counts when LE is low)

14 15 16

CLK RST +9 V, VCC

Clock in Reset - sets output 1 high and outputs 2 through 10 low, when taken high The connection to the +VCC rail (voltage between +3 V and +15 V)

Example: Electronic Roulette

Electronic Roulette circuit diagram. The circuit diagram on the right shows how to create a game of roulette using the 4017 decade counter and various other electronic parts. The variable resistor adjusts the spin speed.

4026 counter and display decoder

The 4026 IC is a 16-pin CMOS seven-segment counter from the 4000 series. It counts clock pulses and returns the output in a form which can be displayed on a seven-segment display. This avoids using a binary-coded decimal to seven-segment decoder, but it can only be used to display the (decimal) digits 0-9. Pinout

Pin Name number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK Clock in CI DE

Purpose

Clock inhibit - when low, clock pulses increment the seven-segment Display enable - the chip outputs to the seven-segment when this is high (i.e. when it's low, the seven-segment is off) - useful to conserve battery life, for instance Carry out output - Is high when changing from 9 to 0. It provides an output at 1/10 of the clock frequency, to drive the clock input of another 4026 to provide multi-digit counting. Output for the seven-segment's F input Output for the seven-segment's G input The connection to the 0 V rail Output for the seven-segment's D input Output for the seven-segment's A input Output for the seven-segment's E input Output for the seven-segment's B input Output for the seven-segment's C input

DEO Display enable out - for chaining 4026s CO F G VDD D A E B C

Ungated C-segment - an output for the seven-segment's C input which is not UCS affected by the DE input. This output is high unless the count is 2, when it goes low. RST Reset - resets all outputs to low when taken high VSS The connection to the +9 V rail