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    Thiết Bị Logic Lập Trình Được

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    This document discusses programmable logic devices (PLDs) and different types of programmable logic arrays (PLAs) and programmable array logic (PALs). It provides examples of PLD structures including ROM, PLA, and PAL configurations. The key components and programming of AND gates, OR gates, and product terms are described for PLA and PAL devices. Truth tables and logic equations are given as examples of how inputs map to outputs in these programmable logic structures.

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    Thiết Bị Logic Lập Trình Được

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    9 views16 pages
    This document discusses programmable logic devices (PLDs) and different types of programmable logic arrays (PLAs) and programmable array logic (PALs). It provides examples of PLD structures including ROM, PLA, and PAL configurations. The key components and programming of AND gates, OR gates, and product terms are described for PLA and PAL devices. Truth tables and logic equations are given as examples of how inputs map to outputs in these programmable logic structures.

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    KTS_C5_PLD

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    This document discusses programmable logic devices (PLDs) and different types of programmable logic arrays (PLAs) and programmable array logic (PALs). It provides examples of PLD structures including ROM, PLA, and PAL configurations. The key components and programming of AND gates, OR gates, and product terms are described for PLA and PAL devices. Truth tables and logic equations are given as examples of how inputs map to outputs in these programmable logic structures.

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    © All Rights Reserved
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    9 views16 pages

    Thiết Bị Logic Lập Trình Được

    Uploaded by

    Tấn Phát Trần
    This document discusses programmable logic devices (PLDs) and different types of programmable logic arrays (PLAs) and programmable array logic (PALs). It provides examples of PLD structures including ROM, PLA, and PAL configurations. The key components and programming of AND gates, OR gates, and product terms are described for PLA and PAL devices. Truth tables and logic equations are given as examples of how inputs map to outputs in these programmable logic structures.

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    of 16

    PLD

    THIT B LOGIC LP TRNH C (Programmable Logic Device)

    NguyenTrongLuat

    BO NH BAN DAN
    Bo nh ban dan

    Bo nh bang

    Bo nh ham

    RAM tnh ong

    ROM

    PLD

    MROM PLA PAL LCA EPLD PEEL GAL PROM PPAL EPLPAL EPROM EEPROM EEPPAL
    2

    NguyenTrongLuat

    BO NH ROM
    Input: cac tn hieu a ch (Address) Output: cac tn hieu d lieu (Data) A0 INPUT (n ng) A1 D0 D1 OUTPUT (m ng)

    An-1

    Dm-1

    Kch thc ROM:


    NguyenTrongLuat

    2n

    m (bit)
    3

    Cau truc noi ROM 8 x 4 (bit)


    0 0 0 0 1 1 1 1

    Bang nap ROM


    A2 A1 A0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D3 D2 D1 D0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0

    1 0 1

    1 1 1 1 1 0 1 1 1

    0 1 0 0
    4

    word line bit line


    NguyenTrongLuat

    0 1 1

    ROM 128 x 1 (bit) giai ma 2 chieu

    NguyenTrongLuat

    ROM 32K x 8 (bit) = 32KB

    NguyenTrongLuat

    Cau truc ROM co ngo vao ieu khien

    NguyenTrongLuat

    Cong em ba trang thai (Tristate Output Buffer): - 3 trang thai (tristate): LOW / HIGH / HIGH impedance - Trang thai tong tr cao (HIGH impedance): ngo ra h mach - Ngo ieu khien 3 trang thai: * HIGH: The buffer is Active * LOW: HIGH impedance

    NguyenTrongLuat

    Cac EPROM thong dung

    NguyenTrongLuat

    (PROGRAMMABLE LOGIC ARRAY)

    PLA

    INPUT (n bit)

    Day AND

    Day OR

    OUTPUT (m bit)

    k product term (so hang tch)


    NguyenTrongLuat 10

    Day AND co the lap trnh

    NguyenTrongLuat

    Day OR co the lap trnh

    11

    A B C
    Input: 1: asserted in term 0: negated in term -: does not participate in term Output: 1: is connected to output 0: no connection to output

    Cau truc PLA 3 x 2, 4 so hang tch F1 = A B + A C + A B C F2 = A C + B C


    AB AC BC ABC 0 1

    Bang nap PLA C C B B A A


    A B C AB AC BC ABC 1 0 1 - 1 - 1 1 0 1 0 F2 (C) F1 (T) 0 1 1 0 1 1 0 1

    F1 F2

    NguyenTrongLuat

    12

    (PROGRAMMABLE ARRAY LOGIC )


    - Day AND lap trnh, day OR co nh - Moi ngo ra la cong OR co so ngo vao co nh - So hang tch khong s dung chung cho cac ngo ra - Cau truc PAL: so ngo vao, so ngo ra va so cong AND tren 1 cong OR

    PAL

    NguyenTrongLuat

    13

    Cau truc PAL 3 ngo vao, 3 ngo ra, 3 cong AND / OR


    1 2 3

    F1

    I1
    4 5 6

    F2

    I2
    7 8 9

    F3

    I3
    NguyenTrongLuat 14

    X=AB+BC

    Y=A+BC
    A A B B C C X X

    Z=AB+BC+BC+AC =X+BC+AC

    1 2 3

    A
    4 5 6

    B
    7 8 9

    C
    NguyenTrongLuat 15

    X=AB+BC

    Y=A+BC

    Z=AB+BC+BC+AC =X+BC+AC

    Bang nap PAL A B C X 1 2 3 4 5 6 7 8 9


    NguyenTrongLuat

    OUTPUT X = AB + BC A + BC X + BC + AC
    16

    1 1 1

    0 0 0 1 0 0 0 1

    Y =

    Z =

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