AIM:WRITE A PROGRAM IN VERILOG TO IMPLEMENT ALU

MAIN MODULE
`timescale 1ns / 1ps
module alu_operation(s, a,b, y);
input [2:0] s;
input a,b;
output y;
reg y;
always @(s,a,b)
begin
case(s)
3'b000:y=a+b;
3'b001:y=a*b;
3'b010:y=a-b;
3'b011:y=a&b;
3'b100:y=a|b;
3'b101:y=a&&b;
3'b110:y=~a;
3'b111:y=a^b;
endcase
end

endmodule
TEST BENCH
`timescale 1ns / 1ps
module alutb_v;

// Inputs
reg [2:0] s;
reg a;

reg b;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

alu_operation aluop(s,a,b,y);

initial begin
// Initialize Inputs
a = 1;
b = 1;
s = 3'b001;
#2 s = 3'b001;
#2 s = 3'b010;
#2 s = 3'b011;
#2 s = 3'b100;
#2 s = 3'b101;
#2 s = 3'b110;
#2 s = 3'b111;

// Wait 100 ns for global reset to finish

#2 $stop;

// Add stimulus here

end

endmodule

STIMULUS

RTL SCHEMATIC

LEARNING OUTCOMES:
I LEARNT TO IMPLEMENT ALU OPERATION.

RESULT:
AS A RESULT I GOT THE DIFFERENT RESULTS OF ALU LIKE ADDITION
,LOGICAL AND ,LOGICAL OR ETC.