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PLL
PLL
A.II.
Vng kha pha(Phase locked loop-PLL): ---------------------------------------------------------------------3
II.1.
Miu t thanh ghi: --------------------------------------------------------------------------------------------4
II.2.
Thanh ghi iu khin PLL(PLLCON - 0xE01FC080)----------------------------------------------------4
II.3.
Thanh ghi to cu hnh PLL(PLLCFG - 0xE01FC084) -------------------------------------------------5
II.4.
Thanh ghi trng thi PLL(PLLSTAT - 0xE01FC088)----------------------------------------------------5
+Ngt PLL: -----------------------------------------------------------------------------------------------------------6
II.5.
Cc ch hot ng ca PLL: ----------------------------------------------------------------------------6
II.6.
Thanh ghi cp nht gi tr PLL lin tc (PLLFEED - 0xE01FC08C) ---------------------------------6
II.7.
PLL v ch Power Down: -------------------------------------------------------------------------------6
II.8.
Tnh ton tn s hot ng ca PLL: ----------------------------------------------------------------------6
II.9.
Th tc xc nh cu hnh PLL: ----------------------------------------------------------------------------7
V d v PLL:
H thng thit k c Fosc=10MHz v cn CCLK=60MHz. -------------------------------7
A.III. iu khin ngun:------------------------------------------------------------------------------------------------7
III.1.
Din t thanh ghi: --------------------------------------------------------------------------------------------7
III.2.
Thanh ghi iu khin ngun (PCON-0xE01FC0C0): ----------------------------------------------------7
III.3.
Thanh ghi iu khin ngun cho ngoi vi(PCONP-0xE01FC0C4): -----------------------------------8
A.IV.
Reset: --------------------------------------------------------------------------------------------------------------8
A.V.
B chia VPB: -----------------------------------------------------------------------------------------------------9
+Thanh ghi ca b chia VPB (VPBDIV - 0xE01FC100):----------------------------------------------------------9
A.VI.
B.
Chn tn s dao ng
Trang 2
1:
2:
3:
4:
5:
6:
7:
Danh mc cc bng:
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Trang 3
Chn tn s dao ng
Trang 4
Tn gi
0xE01FC080
PLLCON
0xE01FC084
PLLCFG
0xE01FC088
PLLSTAT
0xE01FC08C
PLLFEED
Chc nng
Thanh ghi iu khin PLL. Thanh ghi ny gi gi tr cp nht cc bit iu
khin PLL. Gi tr ghi vo thanh ghi ny s c tc dng khi xy ra qu trnh
cp nht gi tr PLL mi hp l.
Thanh ghi cu hnh PLL. Thanh ghi ny gi gi tr cp nht cu hnh PLL
mi. Gi tr ghi vo thanh ghi ny s c tc dng khi xy ra qu trnh cp nht
gi tr PLL mi hp l.
Thanh ghi trng thi PLL. c ngc gi tr ca thanh ghi ny bit thng
tin iu khin v cu hnh ca PLL. Nu thanh ghi PLLCON hoc PLLCFG
c ghi gi tr mi, nhng qu trnh cp nht PLL lin tc(feed) khng xy
ra, n s khng nh hng ti trng thi PLL hin ti. c gi tr ca thanh
ghi ny s cho bit gi tr tht s iu khin PLL hoc trng thi tht s ca
PLL trong thi im .
Thanh ghi cp nht lin tc (feed) gi tr thanh ghi PLL. Feed Register. Thanh
ghi ny cho php load cc thng tin v iu khin v cu hnh ca thanh ghi
PLLCON v PLLCFG vo thanh ghi ph (shadow) c nh hng trc tip ln
hot ng ca PLL.
Truy cp
c/Ghi
c/Ghi
Ch c
Ch ghi
PLLCON
PLLE
PLLC
7:2
D tr
Trang 5
Gi tr Reset
Cho php PLL Enable. Khi PLLE=1 v sau khi qu trnh cp nht
gi tr PLL hp l, bit ny s cho php PLL n kha gi tr tn s
yu cu. Xem thm thanh ghi PLLSTAT.
Kt ni PLL. Khi [PLLC,PLLE]=11, sau khi qu trnh cp nht gi
tr PLL din ra hp l, ng ra xung nhp ca PLL c chn l xung
nhp ca h thng. Ngc li, xung nhp ca ngun dao ng l
xung nhp ca h thng<xem thm thanh ghi PLLSTAT>
D tr, khng c s dng.
0
NA
Tn chc nng
4:0
MSEL4:0
6:5
PSEL1:0
D tr
Gi tr reset
0
0
NA
Tn chc
nng
4:0
6:5
7
MSEL4:0
PSEL1:0
D tr
PLLE
PLLC
10
PLOCK
15:11
D tr
Gi tr
reset
0
0
NA
0
0
NA
Chn tn s dao ng
Trang 6
+Ngt PLL:
Bit PLOCK trn thanh ghi PLLSTAT c ni vi b iu khin ngt. n cho php
chng trnh phn mm tch cc PLL v tip tc thc hin cc chc nng khc m khng cn
i PLL xc lp ti tn s mong mun. Khi ngt xy ra (PLOCK=1), PLL c th c kt
ni, v khng cho php ngt.
II.5. Cc ch hot ng ca PLL:
PLLC
PLLE
1
1
0
1
Tn chc
nng
7:0
PLLFEED
Gi tr
Reset
Khng xc
nh
Trang 7
Gi tr ca P
00
01
10
11
Cc bit MSEL
CFG[4:0]
Gi tr ca M
00000
00001
00010
00011
...
11110
11111
1
2
3
4
...
31
32
V d v PLL:
H thng thit k c Fosc=10MHz v cn CCLK=60MHz.
Li gii:
M=CCLK/Fosc=6M-1=5PLLCFG[4:0]=00101
P= Fcco / (CCLK2), s dng iu kin: Fcco=[156MHz:320MHz]
P=[1.36:2.37]P=2PLLCFG[6:5] = 01.
A.III. iu khin ngun:
LPC2214 c 2 ch tit kim ngun: Idle v Power Down:
+Trong ch Idle, tt c cc ch lnh u tr hon ti khi qu trnh Reset xy ra,
ngoi vi vn hot ng trong ch Idle v c th sinh ra ngt a h thng tr li hot
ng bnh thng.
+Trong ch Power Down, xung nhp h thng khng cn hot ng, cc chn
ngoi vi trng thi tnh. Nng lng tiu th gn nh bng 0. C th phc hi h thng t
Power Down bng cch Reset hoc ngt ngoi.
Chc nng iu khin ngun cho ngoi vi cho php tng chn ngoi vi ring bit hot
ng, hoc khng hot ng, v h thng s tit kim nng lng hn na.
III.1. Din t thanh ghi:
a ch
Tn chc nng
0xE01FC0C0
PCON
0xE01FC0C4
PCONP
Truy cp
c/Ghi
c/Ghi
Tn chc
nng
IDL
PD
7:2
D tr
Gi tr
Reset
0
0
NA
Chn tn s dao ng
Trang 8
Tn chc
nng
0
1
2
3
4
5
6
7
8
9
10
11
12
31:13
D tr
PCTIM0
PCTIM1
PCURT0
PCURT1
PCPWM0
D tr
PCI2C
PCSPI0
PCRTC
PCSPI1
PCEMC
PCAD
D tr
A.IV. Reset:
C 2 ngun to reset h thng: trn chn RESET <Reset ngoi> v t ng h
Watchdog <Reset trong>. Tn hiu Reset hp l s khi ng ng h Wakeup Timer.
Vi qu trnh POR, chn Reset cn phi gi mc trong vng 10ms, vi qu trnh
Reset ngoi bnh thng khi MCU ang hot ng, ch cn 300ns.
Sau qu trnh Reset, vi x l bt u thc thi lnh ti vng a ch 0x0000 0000.
Vector ngt c nh vng a ch khi Boot, gi tr ca cc thanh ghi c khi to
nhng gi tr nh ngha trc.
Qu trnh Reset ngoi v reset trong <Watchdog Timer> c cht t khc bit, l do
thi im Reset ngoi ta hon ton bit c, cn Reset trong ta khng bit khi no th n
xy ra. Bi vy, vi qu trnh Reset ngoi, ta c th ch ng a n vo cc ch hot
ng mong mun bng cch kt ni ngoi vi, v phn mm.
Gi tr
Reset
0
1
1
1
1
1
0
1
1
1
1
1
1
NA
Trang 9
Tn
0xE01FC100
VPBDIV
Chc nng
iu khin tc tng i ca xung nhp VPB so vi xung nhp vi x l.
Truy cp
c/Ghi
Tn chc
nng
1:0
VPBDIV
3:2
D tr
5:4
XCLKDIV
7:6
D tr
Gi tr
Reset
0
0
Chn tn s dao ng
Trang 10
CCLK = M Fosc
Fcco
ta s tm c rng but ca P:
2P
= 2 P M Fosc
CCLK =
Fcco
156Mhz
320Mhz
78Mhz
160Mhz
P
P
, t c (M,P), suy ra
CCLK
CCLK
2CCLK
2CCLK
PLLCF [ 6:5] =P-1
.
Trang 11