PHASE LOCKED LOOP

Cch khi to v chn tn s dao ng trong Keil-uV3

---Cc mc chnh:
A.I.

Ngun dao ng: -------------------------------------------------------------------------------------------------3

A.II.
Vng kha pha(Phase locked loop-PLL): ---------------------------------------------------------------------3
II.1.
Miu t thanh ghi: --------------------------------------------------------------------------------------------4
II.2.
Thanh ghi iu khin PLL(PLLCON - 0xE01FC080)----------------------------------------------------4
II.3.
Thanh ghi to cu hnh PLL(PLLCFG - 0xE01FC084) -------------------------------------------------5
II.4.
Thanh ghi trng thi PLL(PLLSTAT - 0xE01FC088)----------------------------------------------------5
+Ngt PLL: -----------------------------------------------------------------------------------------------------------6
II.5.
Cc ch hot ng ca PLL: ----------------------------------------------------------------------------6
II.6.
Thanh ghi cp nht gi tr PLL lin tc (PLLFEED - 0xE01FC08C) ---------------------------------6
II.7.
PLL v ch Power Down: -------------------------------------------------------------------------------6
II.8.
Tnh ton tn s hot ng ca PLL: ----------------------------------------------------------------------6
II.9.
Th tc xc nh cu hnh PLL: ----------------------------------------------------------------------------7
V d v PLL:
H thng thit k c Fosc=10MHz v cn CCLK=60MHz. -------------------------------7
A.III. iu khin ngun:------------------------------------------------------------------------------------------------7
III.1.
Din t thanh ghi: --------------------------------------------------------------------------------------------7
III.2.
Thanh ghi iu khin ngun (PCON-0xE01FC0C0): ----------------------------------------------------7
III.3.
Thanh ghi iu khin ngun cho ngoi vi(PCONP-0xE01FC0C4): -----------------------------------8
A.IV.

Reset: --------------------------------------------------------------------------------------------------------------8

A.V.
B chia VPB: -----------------------------------------------------------------------------------------------------9
+Thanh ghi ca b chia VPB (VPBDIV - 0xE01FC100):----------------------------------------------------------9
A.VI.
B.

Chong trnh minh ha:-----------------------------------------------------------------------------------------9

Kt lun: ------------------------------------------------------------------------------------------------------------ 11

Ti liu tham kho chnh:------------------------------------------------------------------------------------------------ 11

Chn tn s dao ng

Trang 2

Danh mc cc hnh minh ha:

Hnh
Hnh
Hnh
Hnh
Hnh
Hnh
Hnh

1:
2:
3:
4:
5:
6:
7:

Chn dao ng t ngun ngoi (a).................................................................................................... 3

Chn tn s hot ng t ngun thch anh ngoi (b)......................................................................... 3
Thut ton chn tn s dao ng ca MCU....................................................................................... 3
Gin khi PLL .............................................................................................................................. 4
Gin khi reset bao gm c ng h Wakeup................................................................................ 8
Kt ni ca b chia VPB vi PLL ........................................................................................................ 9
Mn hnh lm vic khi chnh sa cc thng s MSEL, PSEL ca Keil-uV3 .............................................11

Danh mc cc bng:
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng
Bng

1: Cc thanh ghi PLL............................................................................................................................ 4

2: Thanh ghi iu khin PLL(PLLCON - 0xE01FC080) ............................................................................. 5
3: Thanh ghi cu hnh cho PLL(PLLCFG - 0xE01FC084) .......................................................................... 5
4: Thanh ghi trng thi PLL(PLLSTAT - 0xE01FC088) ............................................................................. 5
5: Kt hp cc bit iu khin PLL.......................................................................................................... 6
6: Thanh ghi cp nht gi tr PLL lin tc(PLLFEED - 0xE01FC08C) ......................................................... 6
7: Gi tri cc h s chia ca PLL ........................................................................................................... 7
8: Cc gi tr ca b nhn PLL .............................................................................................................. 7
9: Cc thanh ghi iu khin ngun........................................................................................................ 7
10: Thanh ghi iu khin ngun PCON.................................................................................................. 7
11: Thanh ghi iu khin ngun cho ngoi vi ........................................................................................ 8
12: Thanh ghi VPBDIV ......................................................................................................................... 9
13: Thanh ghi b chia VPB (VPBDIV - 0xE01FC100) ............................................................................... 9

Thnh ph H Ch Minh, thng 2 nm 2006

PHASE LOCKED LOOP

Trang 3

A.I. Ngun dao ng:

Cu hnh trn chip cho php chn dao ng tn s t 1MHz-30MHz. Thng gp dng
ngun dao ng ngoi nh hnh v di:

Hnh 1: Chn dao ng t ngun ngoi (a)

Hnh 2: Chn tn s hot ng t ngun thch anh ngoi (b)

Hnh 3: Thut ton chn tn s dao ng ca MCU

A.II. Vng kha pha(Phase locked loop-PLL):

PLL hot ng vi tn s dao ng t 1-25MHz. Ng vo tn s c nhn vo
CCLK trong tm t 10MHz n 60MHz s dng my dao ng iu khin tc thi (Current
Controlled Oscillator-CCO) Gi tr nhn vo c th trong phm vi t 1 n 32 (s nguyn)
<tht ra, vi LPC2214, h s ny nh hn 6 v b gii hn ngng trn ca tn s dao ng>
CCO hot ng trong tm tn s t 156MHz n 320MHz, bi vy, c thm mt b chia
trong vng (loop) gi gi tr CCO trong tm gii hn tn s khi PLL to tn s dao ng
mong mun. B chia ngoi c cc s chia l 2,4,8,16 to tn hiu xung nhp ng ra.
Nu s chia l 2, n m bo rng tn hiu ng ra ca PLL c gn 50%.
Hot ng ca PLL c iu khin bi thanh ghi PLLCFG. C 2 thanh ghi c bo
v chng li s c xy ra do thay i cc thng s ca PLL hoc PLL khng hot ng.V
tt c cc thnh phn trn chip, k c ng h Watchdog, u ph thuc vo PLL khi n cung
cp xung nhp cho chip, cc s c xy ra vi PLL c th gy ra cc hot ng khng mong
mun trn vi iu khin. Chc nng bo v ca PLL c thc hin bng cch cp nht gi
tr lin tc ging nh ng h Watchdog. PLL khng hot ng khi chip Reset hoc vo ch
Power Down. PLL ch hot ng khi ngi lp trnh cho php. Chng trnh lp trnh phi
nh cu hnh cho PLL, cho n hot ng, ch PLL kha pha, sau xem PLL nh l ngun
xung nhp.

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Chn tn s dao ng

Trang 4

II.1. Miu t thanh ghi:

PLL c iu khin bng cc thanh ghi trong bng di y.
Lu rng vic thit t cc gi tr PLL khng ph hp c th lm thit b hot ng
sai.
a ch

Tn gi

0xE01FC080

PLLCON

0xE01FC084

PLLCFG

0xE01FC088

PLLSTAT

0xE01FC08C

PLLFEED

Chc nng
Thanh ghi iu khin PLL. Thanh ghi ny gi gi tr cp nht cc bit iu
khin PLL. Gi tr ghi vo thanh ghi ny s c tc dng khi xy ra qu trnh
cp nht gi tr PLL mi hp l.
Thanh ghi cu hnh PLL. Thanh ghi ny gi gi tr cp nht cu hnh PLL
mi. Gi tr ghi vo thanh ghi ny s c tc dng khi xy ra qu trnh cp nht
gi tr PLL mi hp l.
Thanh ghi trng thi PLL. c ngc gi tr ca thanh ghi ny bit thng
tin iu khin v cu hnh ca PLL. Nu thanh ghi PLLCON hoc PLLCFG
c ghi gi tr mi, nhng qu trnh cp nht PLL lin tc(feed) khng xy
ra, n s khng nh hng ti trng thi PLL hin ti. c gi tr ca thanh
ghi ny s cho bit gi tr tht s iu khin PLL hoc trng thi tht s ca
PLL trong thi im .
Thanh ghi cp nht lin tc (feed) gi tr thanh ghi PLL. Feed Register. Thanh
ghi ny cho php load cc thng tin v iu khin v cu hnh ca thanh ghi
PLLCON v PLLCFG vo thanh ghi ph (shadow) c nh hng trc tip ln
hot ng ca PLL.

Truy cp
c/Ghi
c/Ghi

Ch c

Ch ghi

Bng 1: Cc thanh ghi PLL

Hnh 4: Gin khi PLL

II.2. Thanh ghi iu khin PLL(PLLCON - 0xE01FC080)

Thanh ghi iu kin PLL cha cc bit cho php v kt ni PLL. Cho php PLL n
th kha cc gi tr thit lp hin ti ca b chia v nhn tn s. Kt ni PLL vi x l hot
ng nh xung nhp ng ra ca PLL. S thay i ca thanh ghi PLL khng nh hng h
thng ti khi qu trnh cp nht gi tr tun t lin tc din ra ng. <Xem thm thanh ghi
cp nht gi tr PLL lin tc -PLL Feed Register(PLLFEED - 0xE01FC08C)>
Thnh ph H Ch Minh, thng 2 nm 2006

PHASE LOCKED LOOP

PLLCON

Chn chc nng

PLLE

PLLC

7:2

D tr

Trang 5

Din t chc nng

Gi tr Reset

Cho php PLL Enable. Khi PLLE=1 v sau khi qu trnh cp nht
gi tr PLL hp l, bit ny s cho php PLL n kha gi tr tn s
yu cu. Xem thm thanh ghi PLLSTAT.
Kt ni PLL. Khi [PLLC,PLLE]=11, sau khi qu trnh cp nht gi
tr PLL din ra hp l, ng ra xung nhp ca PLL c chn l xung
nhp ca h thng. Ngc li, xung nhp ca ngun dao ng l
xung nhp ca h thng<xem thm thanh ghi PLLSTAT>
D tr, khng c s dng.

0
NA

Bng 2: Thanh ghi iu khin PLL(PLLCON - 0xE01FC080)

PLL phi c thit t, cho php, v thit lp kha (to c tn s dao ng n

nh) trc khi n c th thnh ngun xung nhp h thng. khi chuyn t tn s dao ng
ngoi thnh xungnhp PLL hoc ngc li, mch dao ng ni c vn hnh m bo
rng khng to ra cc glitches. Phn cng th khng m bo rng PLL c kha (dao ng
n nh vi tn s mong mun) trc khi kt ni hay s t ng khng kt ni khi tn s dao
ng khng n nh. Nu xy ra li trn xung nhp PLL khi ang hot ng, kt qu ging
nh xung nhp my to dao ng khng n nh v vic khng kt ni PLL s phi bt buc
trong trng hp ny.
II.3. Thanh ghi to cu hnh PLL(PLLCFG - 0xE01FC084)
Thanh ghi PLLCFG cha cc gi tr ca b nhn v chia ca PLL. S thay i gi tr
ca thanh ghi ny ch c tc dng khi m vic cp nht gi tr PLL mi din ra hp
l<Xem thanh ghi cp nht gi tr PLL lin tc(PLLFEED - 0xE01FC08C)>
PLLCFG

Tn chc nng

4:0

MSEL4:0

6:5

PSEL1:0

D tr

Ch thch chc nng

Gi tr reset

Gi tr b nhn ca PLL. Multiplier value. a ra gi tr "M" php tnh

tn s PLL.
Gi tr b chia ca PLL. Multiplier value. a ra gi tr "P" php tnh
tn s PLL.
D tr, khng c s dng

0
0
NA

Bng 3: Thanh ghi cu hnh cho PLL(PLLCFG - 0xE01FC084)

II.4. Thanh ghi trng thi PLL(PLLSTAT - 0xE01FC088)

Thanh ghi ch c ny cho ta cc gi tr thng s ca PLL c tc ng ngay thi im c.
PLLSTAT

Tn chc
nng

4:0
6:5
7

MSEL4:0
PSEL1:0
D tr

PLLE

PLLC

10

PLOCK

15:11

D tr

Din gii chc nng

Gi tr b nhn hin ti ca PLL.
Gi tr b chia hin ti ca PLL.
D tr, khng c s dng
Gi tr bit cho php PLL hin ti.
+PLLE=1: PLL ang s dng.
+PLLE=0: PLL khng c s dng.
Bit ny s t ng xa khi vo ch Power Down.
Gi tr bit iu khin PLL hin ti.
+PLLC-PLLE=11: PLL ang s dng v c kt ni vo ngun xung nhp.
+PLLC-PLLE11: PLL khng c s dng, ngun dao ng lc ny ly
t xung nhp ngoi.
Bit ny s t ng xa khi vo ch Power Down.
Bit cho bit trng thi kha ca PLL.
+PLOCK=1: PLL hot ng n nh ti tn s mong mun.
+PLOCK=0: PLL cha hot ng n nh ti tn s mong mun.
D tr, khng c s dng

Bng 4: Thanh ghi trng thi PLL(PLLSTAT - 0xE01FC088)

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Gi tr
reset
0
0
NA
0

0
NA

Chn tn s dao ng

Trang 6

+Ngt PLL:
Bit PLOCK trn thanh ghi PLLSTAT c ni vi b iu khin ngt. n cho php
chng trnh phn mm tch cc PLL v tip tc thc hin cc chc nng khc m khng cn
i PLL xc lp ti tn s mong mun. Khi ngt xy ra (PLOCK=1), PLL c th c kt
ni, v khng cho php ngt.
II.5. Cc ch hot ng ca PLL:
PLLC

PLLE

Chc nng PLL

1
1

0
1

Tt PLL v khng kt ni vi ngun. H thng hot ng nh ng vo xung nhp c nh.

M PLL nhng cha chc kt ni vi ngun. PLL c th kt ni sau khi PLOCK c xc
nhn.
Ging trng hp 00.
Cho php v kt ni PLL vi ngun to dao ng. MCU hot ng nh ng ra xung nhp ca PLL.

Bng 5: Kt hp cc bit iu khin PLL

II.6. Thanh ghi cp nht gi tr PLL lin tc (PLLFEED 1 - 0xE01FC08C)

Gi tr cp nht lin tc phi c ghi vo cc thanh ghi PLLFEED nhm mc ch cc thay
i PLLCON v PLLCFG din ra, qu trnh cp nht gi tr y bao gm:
1. PLLFEED=0xAA
2. PLLFEED=0x55
Phi thc hin ng trnh t cp nht gi tr nh trn, v phi trong cc chu k xung nhp
lin tc. iu cn lu na l cc ngt trong qu trnh cp nht lin tip gi tr cho PLL u
khng c php xy ra. Nu 1 trong 2 gi tr cp nht l khng ng, hoc 1 trong nhng
lu khng c tun th nghim ngt, nhng thay i trn thanh ghi PLLCON hoc
PLLCFG s khng c tc dng.
PLLFEED

Tn chc
nng

7:0

PLLFEED

Din gii chc nng

Qu trnh cp nht lin tc PLL phi c ghi vo thanh ghi ny s
thay i cu hnh v iu khin thanh ghi PLL c tc dng.

Gi tr
Reset
Khng xc
nh

Bng 6: Thanh ghi cp nht gi tr PLL lin tc(PLLFEED - 0xE01FC08C)

II.7. PLL v ch Power Down:

Ch Power Down s t ng tt v khng kt ni PLL. Wakeup t Power Down
khng t ng cp nht li cc gi tr thit t ca PLL. iu phi c lm bng chng
trnh phn mm.Bi vy, cn c chng trnh gi ngay PLL khi cc ngt lm cho h thng
WakeUp t Power Down, lu l khng c dng cc thng s sn c trn PLL trc khi
vo Power Down, v n mt i hoc ty nh.
II.8. Tnh ton tn s hot ng ca PLL:
Cc thng s ng ch :
Fosc: Tn s dao ng ca tinh th.
Fcco: Tn s ca my dao ng c iu khin hin ti.
CCLK: ng ra PLL <chu k xung nhp ca h thng>
M: H s nhn ca PLL
P: H s chia ca PLL.
Tn s ng ra PLL c th tnh t cng thc:
f
CCLK = M f osc = osc
2P
Tn s CCO c th tnh nh cng thc:
f cco = CCLK 2 P = 2 P M f osc
Fosc=[[10 MHz:25 MHz].
CCLK=[10 MHz:Fmax] (tn s ti a cho php ca LPC2214)
Fcco =[156 MHz:320 MHz]
1

C ti liu dch feed=cho n

Thnh ph H Ch Minh, thng 2 nm 2006

PHASE LOCKED LOOP

Trang 7

II.9. Th tc xc nh cu hnh PLL:

Trong nhng ng dng c th s dng PLL, n c cu hnh nh sau:
1. Chn CCLK mong mun.
2. Chn Fosc.
3. Tnh M t cng thc: M=CCLK/Fosc. M=[1:32]. Gi tr vit vo bit MSEL trn thanh ghi PLLCFG=M-1.
4. Tnh P t cng thc.
Cc bit PSEL
PLLCFG[6:5]

Gi tr ca P

00

01

10

11

Bng 7: Gi tri cc h s chia ca PLL

Cc bit MSEL
CFG[4:0]

Gi tr ca M

00000
00001
00010
00011
...
11110
11111

1
2
3
4
...
31
32

Bng 8: Cc gi tr ca b nhn PLL

V d v PLL:
H thng thit k c Fosc=10MHz v cn CCLK=60MHz.
Li gii:
M=CCLK/Fosc=6M-1=5PLLCFG[4:0]=00101
P= Fcco / (CCLK2), s dng iu kin: Fcco=[156MHz:320MHz]
P=[1.36:2.37]P=2PLLCFG[6:5] = 01.
A.III. iu khin ngun:
LPC2214 c 2 ch tit kim ngun: Idle v Power Down:
+Trong ch Idle, tt c cc ch lnh u tr hon ti khi qu trnh Reset xy ra,
ngoi vi vn hot ng trong ch Idle v c th sinh ra ngt a h thng tr li hot
ng bnh thng.
+Trong ch Power Down, xung nhp h thng khng cn hot ng, cc chn
ngoi vi trng thi tnh. Nng lng tiu th gn nh bng 0. C th phc hi h thng t
Power Down bng cch Reset hoc ngt ngoi.
Chc nng iu khin ngun cho ngoi vi cho php tng chn ngoi vi ring bit hot
ng, hoc khng hot ng, v h thng s tit kim nng lng hn na.
III.1. Din t thanh ghi:
a ch

Tn chc nng

0xE01FC0C0

PCON

0xE01FC0C4

PCONP

Din t chc nng

Thanh ghi iu khin ngun. Thanh ghi ny cha cc bit iu khin
vn hnh 1 trong 2 ch Power down hoc Idle.
Thanh ghi iu khin ngun cho ngoi vi. Thanh ghi ny cha cc bit
iu khin cho php/khng cho php tng chc nng ring bit
ca ngoi vi.

Truy cp
c/Ghi
c/Ghi

Bng 9: Cc thanh ghi iu khin ngun

III.2. Thanh ghi iu khin ngun (PCON-0xE01FC0C0):

Thanh ghi ny cha 2 bit: IDL v PD. Chi tit xem bng di y:
PCON

Tn chc
nng

IDL

PD

7:2

D tr

Din t chc nng

Ch Idle. Khi IDL=1, mt s chn ngoi vi vn cn hot ng, ngun ngt ngoi
hoc Reset ngoi c s dng phc hi li trng thi hot ng.
Ch Power Down. Khi PD=1 s lm cho tt c cc dao ng trong chip dng
hn, iu khin wakeup s lm cho h thng khi ng li, xa PD v phc hi cc
lnh.
D tr, khng c s dng

Bng 10: Thanh ghi iu khin ngun PCON

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Gi tr
Reset
0
0
NA

Chn tn s dao ng

Trang 8

III.3. Thanh ghi iu khin ngun cho ngoi vi(PCONP-0xE01FC0C4):

PCONP

Tn chc
nng

0
1
2
3
4
5
6
7
8
9
10
11
12
31:13

D tr
PCTIM0
PCTIM1
PCURT0
PCURT1
PCPWM0
D tr
PCI2C
PCSPI0
PCRTC
PCSPI1
PCEMC
PCAD
D tr

Din t chc nng

D tr, khng c s dng
PCTIM0=1, TIMER0 c s dng-PCTIM0=0, khng s dng TIMER0
Tng t vi TIMER1
PCURT0=1, UART0 c s dng-PCURT0=0, khng s dng UART0.
PCURT1=1, UART1 c s dng-PCURT1=0, khng s dng UART1
PCPWM0=1, PWM0 c s dng-PCPWM0=0, khng s dng PWM0
D tr, khng c s dng
PCI2C =1, giao tip I2C c s dng- PCI2C =0 khng s dng giao tip I2C
Tng t vi giao tip SPI0
Tng t vi RTC
Tng t vi giao tip SPI1
Tng t vi EMC (iu khin b nh ngoi
Tng t vi b bin i ADC
D tr, khng c s dng

Bng 11: Thanh ghi iu khin ngun cho ngoi vi

A.IV. Reset:
C 2 ngun to reset h thng: trn chn RESET <Reset ngoi> v t ng h
Watchdog <Reset trong>. Tn hiu Reset hp l s khi ng ng h Wakeup Timer.
Vi qu trnh POR, chn Reset cn phi gi mc trong vng 10ms, vi qu trnh
Reset ngoi bnh thng khi MCU ang hot ng, ch cn 300ns.
Sau qu trnh Reset, vi x l bt u thc thi lnh ti vng a ch 0x0000 0000.
Vector ngt c nh vng a ch khi Boot, gi tr ca cc thanh ghi c khi to
nhng gi tr nh ngha trc.
Qu trnh Reset ngoi v reset trong <Watchdog Timer> c cht t khc bit, l do
thi im Reset ngoi ta hon ton bit c, cn Reset trong ta khng bit khi no th n
xy ra. Bi vy, vi qu trnh Reset ngoi, ta c th ch ng a n vo cc ch hot
ng mong mun bng cch kt ni ngoi vi, v phn mm.

Hnh 5: Gin khi reset bao gm c ng h Wakeup

Thnh ph H Ch Minh, thng 2 nm 2006

Gi tr
Reset
0
1
1
1
1
1
0
1
1
1
1
1
1
NA

PHASE LOCKED LOOP

Trang 9

A.V. B chia VPB:

B chia VPB cho bit mi quan h gia xung nhp h thng (CCLK) v xung nhp ca
ngoi vi (PCLK). B chia VPB c 2 nhim v:
Ngoi vi c th hot ng vi mt tn s thch hp mong mun theo CCLK.(1/4, 1/2)
B chia VPB cho php tit kim ngun khi ng dng khng i hi cc ngoi vi phi
hot ng tn s ca vi x l.
V b chia VPB ni kt vi ng ra PLL nn n vn hot ng ch Idle.
+Thanh ghi ca b chia VPB (VPBDIV - 0xE01FC100):
a ch

Tn

0xE01FC100

VPBDIV

Chc nng
iu khin tc tng i ca xung nhp VPB so vi xung nhp vi x l.

Truy cp
c/Ghi

Bng 12: Thanh ghi VPBDIV

VPBDIV

Tn chc
nng

1:0

VPBDIV

3:2

D tr

5:4

XCLKDIV

7:6

D tr

Din t chc nng

Gi tr
Reset

VPBDIV [1:0]=00Tc xung nhp VPB=1/4 xung nhp h thng.

VPBDIV [1:0]=01 Tc xung nhp VPB= xung nhp h thng.
VPBDIV [1:0]=10 Tc xung nhp VPB= xung nhp h thng.
VPBDIV [1:0]=11 Khng c nh ngha. Nu ghi gi tr ny vo 2 bit
tng ng, n khng c tc dng, v gi tr trc c s dng.
D tr, khng c s dng
iu khin xung nhp c th c ly ra chn A23/XCLK. N c gi tr
ging nh 2 bit VPBDIV. Phi chn chn A23 l ng ra xung nhp, nh
ngha chc nng thanh ghi PINSEL2
D tr, khng c s dng

Bng 13: Thanh ghi b chia VPB (VPBDIV - 0xE01FC100)

Hnh 6: Kt ni ca b chia VPB vi PLL

A.VI. Chong trnh minh ha:

thay i cc thng s ca CCCK theo Fosc, ta lm theo cc bc sau:
+Xc nh gi tr ca Fosc (v d ti s dng Fosc=11059200) <lu tm ca Fosc t 10Mhz
n 25Mhz>
+Xc nh gi tr CCLK mong mun <CCLK=MFosc> (10Mhz<Fcco<60Mhz)
+Tm PSEL(P) v MSEL(M) vi cc rng but: 156Mhz<Fcco<320Mhz; s dng cc mi
quan h:

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0
0

Chn tn s dao ng

Trang 10

CCLK = M Fosc
Fcco
ta s tm c rng but ca P:
2P
= 2 P M Fosc

CCLK =
Fcco

156Mhz
320Mhz
78Mhz
160Mhz
P

P
, t c (M,P), suy ra
CCLK
CCLK
2CCLK
2CCLK
PLLCF [ 6:5] =P-1
.

PLLCF [ 4:0] =M-1

+Cp nht thng tin thanh ghi PLLCF theo cc trnh t sau <ch khng ghi 1 vo bit 7 ca
thanh ghi ny>
{
PLLCFG &=0x80;
PLLCFG |= PLLCFG[6:0];
//Cp nht gi tr thanh ghi PLLCFG bng trnh t PLLFEED
PLLFEED = 0xaa;
PLLFEED = 0x55;
//Ch ti khi PLL kha pha c nh <bit PLOCK-bng 24, hng dn s dng, trang
63, bng thanh ghi PLLSTAT>
while((PLLSTAT & (1 << 10)) == 0);
//PLL kt ni v ng vai tr l xung nhp h thng
PLLCON = 3;
PLLFEED = 0xaa;
PLLFEED = 0x55;
}
+Cp nht thanh ghi VPBDIV theo cch thc sau (Bng):
VPBDIV|= XCLKDIVH- VPBDIVH
Gi s ta mun hot ng PCLK=CCLK, XCLK=1/2CCLK
VPBDIV=0x21;
Ch : Keil-uV3 c h tr ta thay i cc gi tr ny bng cch sa tp tin Startup.s, xem hnh
sau:

Thnh ph H Ch Minh, thng 2 nm 2006

PHASE LOCKED LOOP

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Hnh 7: Mn hnh lm vic khi chnh sa cc thng s MSEL, PSEL ca Keil-uV3

Cch thay i ny ch c th lm 1 ln ngay t u chng trnh.

B. Kt lun:
Trong bi vit ny, ti phn tch rt chi tit v r rng cc thng s lin quan ti PLL.
Chng trnh minh ha cng vit sn bn tham kho. Kt qu thc t c kim tra
khng c sai st.
Mi trao i khc<nu c> v ti ny, vui lng gi v:
Email
:
buitrunghieu@khvt.com
Cell
:
(+84)98.3210.906

Ti liu tham kho chnh:

Datasheets v User Manual ca LPC2214 Philips Semiconductors
Mt s ti liu t trang web: http://www.arm.com
S dng Keil-uV3 vit chng trnh. Giao tip ISP thng qua COM1 LPC2000 s
dng Flash Utility Ver2.1.0.

Bi Trung Hiu Webmaster: Khoa hc v tui tr