Digital System Design Example 1:

GCD Calculator
Design Specifications:
It computes the greatest common divisor (gcd) of a pair of 4bit binary positive numbers.
The operand registers are initialized with the activation of a
start signal, which commences the computation process.
On completion of the computation, a signal done is asserted
to indicate that the data on the gcd outputs are valid.

Chapter 6

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STEP 1: Algorithmic modelling

reset
S0

Pseudo-code of algorithm
start

INITIALIZE
IF p < q THEN
q = q p
ELSIF p > q THEN
p = p q
ELSE gcd = p
END

p
q

p0 ,
q0

S1
g

p
1

p=q
0

p<q

q-p

Chapter 6

p-q

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STEP 2: RTL Modelling

S0:
S1:

Chapter 6

(start)
(start)'
(eq)
(Lt)
(Lt)'
(eq)
(eq)'

/ P p0 , Q q0;
/ goto S0.
/ G P;
/ Q Q P;
/ P P Q;
/ goto S0;
/ goto S1.

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STEP 3: RTL Design

DU

selP0

selQ0
1

d
ldP

en

ldQ

en

regP

clk

clk
clr

regQ
clr

reset

q
Q

reset

selP

selQ
1

d
ldG

en

regG
q

COMP

clk
clr

a=b
Eq

a-b

a<b
Lt

alu

CU
Register Control

Bus Control

ldG, ldP, ldQ)

(selP0, selQ0, selP, selQ)

reset

FSM

clk

done

Chapter 6

start

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RTN
S0: (start)/P p0;
(start)/Q q0;
done 0;
(start)'/goto S0.
S1: (eq)/G P;
(Lt)/Q Q P;
(Lt)'/P P Q;
(eq)/done 1;
(eq)'/goto S1,
(eq)/goto S0

Chapter 6

Control
signals
activated

Control vector, CV[6:0]

[ldG,selP0,ldP,selQ0,ldQ,
selP,selQ]

selP0, ldP
selQ0, ldQ 0 1 1 1 1 0 0
done'
ldG
1 0 0 0 0 0 0
selQ0,ldQ, 0 0 0 0 1 0 0
selP,selQ
selP0,ldP, 0 0 1 0 0 1 1
selP,selQ
done

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-- DU of gcd calculator
VHDL
entity DU is port (
clk, rst
: in std_logic ;
p0, q0
: in std_logic_vector(3 downto 0) ;
ldG, selP0, ldP, selQ0, ldQ, selP, selQ : in std_logic;
G
: out std_logic_vector(3 downto 0) ;
Eq, Lt : out std_logic ;
P, Q, alu : buffer std_logic_vector(3 downto 0) ;
end DU ;
architecture DU_arch of DU is begin
regP: process (clk, ldP, selP0) begin
if rst = 1 then P <= (others => 0);
elsif (clkevent and clk = 1 then
if ldP = 1 then
if selP0 = 1 then P <= p0; else P <= alu; end if;
else P <= P;
end if;
end process regP;

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-- regQ:
-- same as regP, replace ldP with ldQ, selP0 with selQ0
regG: process (clk, ldG) begin
if (clkevent and clk = 1 then
if ldG = 1 then G <= P; else G <= G; end if;
end if;
end process regG;
ALU_module:
process (selP, selQ, P, Q)
variable sel : std_logic;
begin
sel := selP & selQ;
case sel is
when 00
=>
alu <= Q P;
when 01
=>
alu <= Q Q;
when 10
=>
alu <= P P;
when others
=> alu <= P Q;
end case ;
end process ALU_module;
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-- comparator:
Eq <= 1 when P = Q else 0 ;
Lt <= 1 when P < Q else 0 ;
end DU_arch;

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-- CU in gcd calculator VHDL

entity CU is port (
clk, rst, start : in std_logic ;
Eq, Lt : in std_logic ;
S : out std_logic_vector(1 downto 0) ;
CV : out std_logic_vector(6 downto 0) ;
done : out std_logic );
end CU ;
architecture CU_arch of CU is
type state is (S0, S1) ;
signal y : state;
begin

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state_transition: process (rst, clk) begin

if rst = 1
then y <= S0;
elsif (clkevent and clk = 0 then
case y is
when S0 =>
if start = 1 then y <= S1;
else y <= S0; end if;
when S1 =>
if Eq = 1 then y <= S0;
else y <= S1; end if;
end case ;
end if;
end process state_transition;

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output: process ( y ) begin

CV <= (others => 0);
done <= 0 ;
case y is
when S0 => if start = 1 then CV <= 0111100;
end if;
when S1 => if Eq = 1 then CV <= 1000000;
end if;
if Lt = 1 then CV <= 0000100;
else CV <= 0010011;
end if;
done<= 1;
end case ;
end process output;
end CU_arch;

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Digital System Design Example 2:

Sequential Multiplier
Design specifications:
Multiply two 4-bit unsigned numbers to produce an 8-bit
product.

Chapter 6

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STEP 1: Algorithmic Modelling

P = 0;
for i = 0 to 3 do
if bi = 1 then
P = P + A
end if;
A << 1 ;
end for;

multiplier

multiplicand

MU

P
product

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reset
loadA
loadB

S1
P
0

start
1

P
0

S2

P+A

A
B

1
LSB(B)?

A <<1
B >>1
B = 0?
1

S3
Done
1

start
0

Chapter 6

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STEP 2: RTL Modelling.

S1:

S2:

S3:

Chapter 6

P 0 ;
(start') / A (0 & dataA) , B dataB;
(start') / goto S0.
A A <<1 ;
B B >>1;
(z'b0) / P P + A;
(z') / goto S2.
done 1;
(start) / goto S3;
(start') / goto S1.

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STEP 3: RTL Design

RTL operation

Activated
Control Signals

Psel,ldP,ctrlA,
ldA,ctrlB,ldB

DU Control
Vector

Psel,ldP,ctrlA,
ldA,ctrlB,ldB

S1: P 0;
(start)'/ A 0&dataA
(start)'/ B dataB;
(start)'/ goto S1.
S2: A A <<1;
B B >>1;
(z'b0)/ P P + A;
(z')/ goto S2.
S3: done 1;
(start')/ goto S1.
(start)/ goto S3.

Chapter 6

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Chapter 6

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VHDL Coding of Sequential Multiplier MU

-- MU (top-level)
VHDL
Iibrary ieee;
use ieee.std_logic_1164.all; use
ieee.std_logic_unsigned.all;
entity MU is port (
clock, reset, start
: in std_logic ;
dataA, dataB : in std_logic_vector(3 downto 0) ;
CtrlVector : out std_logic_vector(5 downto 0) ;
done
: out std_logic ;
state
: out std_logic_vector(1 downto 0) ;
result
: buffer std_logic_vector(7 downto 0) ;
tpA
: out std_logic_vector(7 downto 0) ;
tpB
: out std_logic_vector(3 downto 0) ;
tpdataP
: out std_logic_vector(7 downto 0)
);
end MU ;
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architecture MU_arch of MU is
signal intb0, intz : std_logic;
signal intCtrlVec : std_logic_vector(5 downto 0);
component CU port (
clk, rst, start : in std_logic;
b0, z
: in std_logic;
done : out std_logic;
state
: out std_logic_vector(1 downto 0);
CtrlVector
: out std_logic_vector(5 downto 0) );
end component;
component DU port (
clk, rst
: in std_logic;
dataA, dataB : in std_logic_vector(3 downto 0);
P
: buffer std_logic_vector(7 downto 0);
Psel, ldP, ctrlA, ldA, ctrlB, ldB : in std_logic;
A_tp, B_tp
: out std_logic_vector(7 downto 0);
dataP_tp : out std_logic_vector(7 downto 0);
z, b0
: out std_logic );
end component;
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begin
CU port map ( clock, reset, start, intb0, intz, done,
state, intCtrlVec);
CtrlVector <= intCtrlVec;
DU port map ( clock, reset, dataA, dataB, result,
intCtrlVec(5),
intCtrlVec(4),
intCtrlVec(3),
intCtrlVec(2),
intCtrlVec(1),
intCtrlVec(0),
tpA, tpB, tpdataP, intz, intb0 );
end MU_arch;

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-- MU the Control Unit VHDL

Iibrary ieee;
use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity CU is port (
clk, rst, start, b0, z: in std_logic;
done : out std_logic;
state
: out std_logic_vector(1 downto 0);
CtrlVector
: out std_logic_vector(5 downto 0) );
end CU ;
architecture fsm of CU is
signal y : std_logic_vector(1 downto 0);
constant S1 : std_logic_vector(1 downto 0) := 00;
constant S2 : std_logic_vector(1 downto 0) := 01;
constant S3 : std_logic_vector(1 downto 0) := 10;
begin

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fsm_transitions: process ( clk, rst) begin

if (rst = 1) then
y <= S1 ;
elsif (clkevent and clk = 0) then
case y is
when S1 => if start = 0 then y <= S1;
else y <= S2; end if;
when S2 => if
z = 0 then y <= S2;
else y <= S3; end if;
when S3 => if start = 0 then y <= S1;
else y <= S3; end if;
when others => y <= S1;
end case;
end if;
end process fsm-transitions;

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fsm_outputs: process ( y, z, b0, start ) begin

CtrlVector <= (others => 0 );
done <= 0 ;
case y is
when S1 => CtrlVector <= 010000;
if start = 0 then
CtrlVector <= 011111;
end if;
when S2 => CtrlVector <= 000101;
if (z = 0 and b0 = 1) then
CtrlVector <= 110101;
end if;
when S3 => CtrlVector <= 000000;
done <= 1 ;
when others => CtrlVector <= ------;
end case;
end process;
state <= y ;
end fsm;
Chapter 6

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-- MU the Datapath UnitVHDL

Iibrary ieee;
use ieee.std_logic_1164.all;
ieee.std_logic_unsigned.all;

use

entity DU is port (
clk, rst
: in std_logic;
dataA, dataB : in std_logic_vector(3 downto 0);
P
: buffer std_logic_vector(7 downto 0);
Psel, ldP, ctrlA, ldA, ctrlB, ldB : in std_logic;
A_tp
: out std_logic_vector(7 downto 0);
B_tp
: out std_logic_vector(3 downto 0);
dataP_tp
: out std_logic_vector(7 downto 0);
z, b0
: out std_logic;
end DU;

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architecture DU_arch of DU is
signal Ain, A, sum, dataP : std_logic_vector(7 downto 0);
signal B : std_logic_vector(3 downto 0);
signal zero1 : std_logic;
component Reg8 port (
d : in std_logic_vector(7 downto 0);
en, clk, rst : in std_logic;
q : buffer std_logic_vector(7 downto 0) );
end component;
component ShiftLreg8 port (
d : in std_logic_vector(7 downto 0);
ldsh, en, w, clk, rst : in std_logic;
q : buffer std_logic_vector(7 downto 0) );
end component;
component ShiftRreg4 port (
d : in std_logic_vector(3 downto 0);
ldsh, en, w, clk, rst : in std_logic;
q : buffer std_logic_vector(3 downto 0) );
end component;
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begin
zero1 <= 0;
Ain <= 0000 & dataA;
ShiftRreg4 port map (dataB, ctrlB, ldB, zero1, clk,
rst, B );
ShiftLreg8 port map ( Ain, ctrlA, ldA, zero1, clk,
rst, A );
sum <= A + P ;
process (Psel, sum) begin
if Psel = 1 then dataP <= sum;
else dataP <= (others => 0);
end if;
end process;
reg8 port map ( dataP, ldP, clk, rst, P );
z <= 1 when B = 0000 else 0;
b0 <= B(0) ; A_tp <= A ; B_tp <= B ; dataP_tp <= dataP;
end DU_arch;

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-- VHDL declarations of the components in DU of MU

entity reg8 is
port (clk, en, rst : in std_logic;
d : in std_logic_vector (7 downto 0);
Q : buffer std_logic_vector (7 downto 0) );
end reg8;
architecture archreg of reg8 is begin
process (clk, rst ) begin
if rst = 1 then Q <= (others => 0);
elsif (clkevent and clk = 1) then
if en = 1 then Q <= d ; else Q <= Q;
end if; end if;
end process;
end archreg;

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entity shiftLreg8 is
port ( d : in std_logic_vector (7 downto 0);
ldsh, en, w, clk, rst
: in std_logic;
q : buffer std_logic_vector (7 downto 0) );
end shiftLreg8;
architecture Shift_arch of shiftLreg8 is begin
process (clk, rst) begin
if rst = 1 then q <= (others => 0);
elsif (clkevent and clk = 1) then
if en = 1 then
if ldsh = 1 then q <= d;
else
q(0) <= w;
for i in 1 to 7 loop
q(i) <= q(i - 1);
end loop;
end if; end if; end if;
end process;
end Shift_arch;
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entity shiftRreg4 is
port ( d : in std_logic_vector (3 downto 0);
ldsh, en, w, clk, rst
: in std_logic;
q : buffer std_logic_vector (3 downto 0)
end shiftLreg;
architecture Shift_arch of shiftRreg4 is
begin process (clk, rst) begin
if rst = 1 then
q <= (others => 0);
elsif (clkevent and clk = 1) then
if en = 1 then
if ldsh = 1 then q <= d;
else
q(3) <= w;
for i in 0 to 2 loop
q(i) <= q(i + 1);
end loop;
end if; end if; end if;
end process;
end Shift_arch;
Chapter 6

);

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Step 4 & 5: Synthesis & Simulation

Chapter 6

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Chapter 6

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