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© R.lauwereins Imec 2001
© R.lauwereins Imec 2001
R.Lauwereins
Imec 2001
Course contents
Digital
• Digital design
design
• Combinatorial circuits: without status
Combina-
torial • Sequential circuits: with status
circuits
• FSMD design: hardwired processors
Sequential
circuits
Language based HW design: VHDL
FSMD
design
VHDL
5/1
Language based HW design:
©
R.Lauwereins
Imec 2001
a VHDL primer
Digital
• Introduction
design
• A first look at VHDL
Combina-
torial • Signals and data types
circuits
• VHDL operators
Sequential
circuits • Concurrent versus sequential
statements
FSMD
design • Sequential construction statements
VHDL • Higher performance, less portability:
e.g. synthesis issues for Xilinx
5/2
Language based HW design:
©
R.Lauwereins
Imec 2001
a VHDL primer
Digital
Introduction
design
• A first look at VHDL
Combina-
torial • Signals and data types
circuits
• VHDL operators
Sequential
circuits • Concurrent versus sequential
statements
FSMD
design • Sequential construction statements
VHDL • Higher performance, less portability:
e.g. synthesis issues for Xilinx
5/3
©
R.Lauwereins
Imec 2001 VHDL primer: Introduction
• Acronym:
Digital VHDL = VHSIC Hardware Description Language
design
VHSIC = Very High Speed Integrated Circuit
Combina-
torial • What is VHDL?
circuits
A programming language for describing the behavior
of digital systems
Sequential
circuits Design entry language, used for
Unambiguous specification at behavioral and RTL
FSMD
design level
Simulation (executable specification…)
VHDL Synthesis
Documentation
• Standardisation: IEEE 1076
First version: 1986
Second version: 1993
New version about to appear
5/4
©
R.Lauwereins
Imec 2001
VHDL primer: Introduction
Digital
• When to use VHDL instead of
design
schematics?
Combina- Drawbacks:
torial
circuits VHDL is easy to learn but hard to master
(semantics are quite different from software
Sequential languages)
circuits
VHDL has a difficult syntax (Language sensitive
FSMD
editors with templates for all language
design constructs)
VHDL is very ‘wordy’: lots of code to type for just
VHDL
a few simple things
A list of instructions is less intuitive to
understand than a block diagram for a human
being
VHDL is designed to make simulation efficient:
contains aspects that have hardly anything to do
with hardware behavior, but is useful to speed-up
event driven simulation
5/5
©
R.Lauwereins
Imec 2001
VHDL primer: Introduction
Digital
• When to use VHDL instead of schematics?
design Easier to capture complex circuits: higher level of
abstraction with automated synthesis
Combina-
torial
circuits
you specify ‘add’ instead of jotting
down a specific type of adder: the
Sequential
circuits synthesis tool will instantiate the best
type of adder under timing, area &
FSMD
design power constraints
easy to parametrise (e.g. word length,
VHDL
queue depth)
easy to specify arrays of components
Portable across many tools for simulation,
synthesis, analysis, verification, … of different
vendors (e.g. Synopsys, Mentor Graphics, …)
5/6
©
R.Lauwereins
Imec 2001
VHDL primer: Introduction
Digital
• Limitations of VHDL
design
The standard only describes syntax and
Combina-
semantics, but not the coding style
torial you can specify the same behavior (e.g. MUX) in
circuits
an almost unlimited number of ways
Sequential each leading to a completely different
circuits implementation (e.g. Multiplexor or tri-state bus)
which is synthesis tool dependent.
FSMD
design You should do lots of experimentation with style-
tool combinations to be able to predict how the
VHDL hardware will look like that will be synthesised. Is
prediction necessary? You also do not predict the
ASM generated by C; C is less efficient than ASM
but faster to write. Currently, it is hard to tolerate
the inefficiency caused by the higher level
specification for hardware.
Note: for DSP processors programmed in C, we do
predict ASM and have to experiment with style-
5/7
compiler combinations for efficiency reasons!!
©
R.Lauwereins
Imec 2001
VHDL primer: Introduction
Digital
• Limitations of VHDL (ctud)
design
Only a subset of VHDL can be automatically
Combina-
synthesised; each vendor supports a different
torial subset
circuits
Only digital; special extension (not yet widely
Sequential adopted) for analog: VHDL-AMS (acronym for
circuits
VHDL Analog and Mixed Signal)
FSMD
design
IEEE standard 1076.1-1999
is a super-set of the full IEEE VHDL
VHDL
1076-1993 standard for digital design
5/8
©
R.Lauwereins
Imec 2001
VHDL primer: Introduction
Digital
• Abstraction levels
design
Behavioral
Combina- Interconnected functions
torial
circuits
Only info on functions or algorithms
Sequential (what)
circuits
Only timing needed to let the
FSMD
design
function work correctly
OK for VHDL
VHDL
Behavioral synthesisers immature;
used for high level executable
specification in top-down design and
manual synthesis into RTL
5/9
©
R.Lauwereins
Imec 2001
VHDL primer: Introduction
Digital
• Abstraction levels
design
RTL
Combina-
Interconnected registers and combinatorial units
torial Info on function (what) and architecture (how)
circuits
Cycle accurate
Sequential No technology dependent timing info
circuits
OK for VHDL
FSMD Good synthesisers
design
Gate level
VHDL Interconnected gates and flip-flops
Info on function and architecture
Info on technology dependent timing (gate delays)
Layout
Info on layout on silicon
Continuous timing
Analog effects
5/10
©
R.Lauwereins
Imec 2001
VHDL primer: Introduction
Digital
• Other hardware description languages
design
(HDL)
Combina- Verilog
torial
circuits More widespread in USA than in
Sequential
Europe
circuits
Often required for gate level or RTL
FSMD level ASIC sign-off
design
Never ending discussion which is
VHDL
better
PLD languages like ABEL, PALASM, …
These are more at the gate level,
capturing also technology dependent
features (e.g. detailed timing)
5/11
©
R.Lauwereins
Imec 2001
VHDL primer: Introduction
Digital
• Difference between HDLs and traditional
design
software programming languages
Combina- Concurrency: all hardware components operate
torial
circuits
in parallel
Data types: support is needed for arbitrary size
Sequential
circuits
integers, bit vectors, fixed point numbers
Concept of time
FSMD
design
VHDL
5/12
Language based HW design:
©
R.Lauwereins
Imec 2001
a VHDL primer
Digital
• Introduction
design
A first look at VHDL
Combina-
torial • Signals and data types
circuits
• VHDL operators
Sequential
circuits • Concurrent versus sequential
statements
FSMD
design • Sequential construction statements
VHDL • Higher performance, less portability:
e.g. synthesis issues for Xilinx
5/13
A First look at VHDL:
©
R.Lauwereins
Imec 2001
VHDL
5/14
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Schematic specification
Digital
• The circuit will be hierarchically
design
decomposed into a top level component
Combina- ‘Test’ containing 2 instantiations of a
torial
circuits comparator component ‘Compare’
Sequential
circuits Test
Compare
FSMD
In1 Out1
design A
EQ
VHDL
B
In2
Compare
A
In3 EQ Out2
B
5/15
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Schematic specification
Digital
• The comparator is then hierarchically
design
decomposed into a gate level
Combina- combinatorial circuit
torial
circuits
Compare
Sequential
circuits A[0] XNOR
A
FSMD B[0]
design
A[1] AND
VHDL EQ
B[1] EQ
B
A[7]
B[7]
5/16
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Comparison with C
Digital
• This is very similar to software
design
programming languages, e.g. C
Combina-
torial /* Eight bit comparator
circuits
*/ Interface to the function
int Compare
Sequential (int A, int B)
circuits
Inputs and outputs are
called ‘arguments’
{
FSMD
design
return (A == B); Behavior of the function
}
VHDL
Notes:
- Only one behavior per function possible
- Behavior is specified at rather high level and will be
automatically translated by the compiler into ASM instructions
- Function arguments do not have a direction and are of type int
5/19
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Comparison with C
Digital
• This is how the higher hierarchical level
design
looks like in C
Combina- /* Dual comparator Test program
torial */
circuits
main()
Sequential {
circuits
Two calls to the function
int In1, In2, In3; ‘Compare’ with its
int Out1, Out2; argument binding
FSMD
design
Out1 = Compare(In1, In2);
VHDL
Out2 = Compare(In1, In3);
}
Notes:
- The two ‘compare’ function calls are executed sequentially
- This main program is executed once and stops. In VHDL, all
components describe relations that are valid continuously and
forever
5/20
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Configuration
• When an entity has multiple architectures, how do you indicate
Digital which one to use?
design
• How do you bind ‘Components’ to ‘Entities’?
Combina-
torial
circuits
Sequential
circuits -- Configuration information: architecture selection
-- and component-entity binding
FSMD
Both ‘use entity’s could
design be combined in one:
configuration Build1 of Test is
for All: Comparator ...
for Struct1
VHDL
for Compare1: Comparator use entity Compare(Behav1)
port map (A => X, B => Y, EQ => Z);
end for;
for others: Comparator use entity Compare(Behav1)
port map (A => X, B => Y, EQ => Z);
end for;
end for;
end configuration Build1;
5/21
Note: ‘configuration’ corresponds in SW to ‘linking’
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Syntax
Digital
design
ENTITY:
Combina-
torial entity Entity_name is
circuits
port( Signal_name: in Signal_type;
Signal_name: out Signal_type);
Sequential
circuits
end entity Entity_name;
FSMD
design
ARCHITECTURE:
VHDL
5/22
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Syntax
Digital COMPONENT:
design component Component_name is
port( Signal_name: in Signal_type;
Combina- Signal_name: out Signal_type);
torial end component Component_name;
circuits
Name used in
SIGNAL LIST: component declaration
-- two variants:
-- variant 1: ordered list of signals as in software languages
-- e.g. (In1,In2,Out1)
-- variant 2: named list Locally used name
-- e.g. (B => In2, EQ => Out1, A => In1)
5/23
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Syntax
Digital
design CONFIGURATION:
VHDL
5/24
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Example 2
Digital
• Declare a 3-input AND gate
design
Combina- A
Y
torial B
circuits
C
Sequential
circuits
-- 3-input AND gate
entity AND3 is
FSMD
design port ( A,B,C: in bit;
Y: out bit);
VHDL end entity AND3;
5/25
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Example 2
Digital
• Declare a 3-input OR gate
design
Combina- A
Y
torial B
circuits
C
Sequential
circuits
-- 3-input OR gate
entity OR3 is
FSMD
design port ( A,B,C: in bit;
Y: out bit);
VHDL end entity OR3;
5/26
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Example 2
Digital
• Declare an INV gate
design
Combina-
torial A Y
circuits
Sequential
circuits
-- INV gate
entity INV is
FSMD
design port ( A: in bit;
Y: out bit);
VHDL end entity INV;
5/27
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Example 3
Digital
• Build a 2-to-1 MUX using both a
design
behavioral as well as a structural
Combina- description
torial A
circuits Y
B
Sequential
circuits S
entity MUX21 is The black box
port ( A,B,S: in bit; interface
FSMD
design Y: out bit);
end entity MUX21;
VHDL
5/28
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Example 3
Digital
• Build a 2-to-1 MUX using both a behav. as
design
well as a structural description A
Y
Combina- architecture Struct of MUX21 is B
torial signal U,V,W : bit;
circuits component AND2 is S
port ( X,Y: in bit;
Sequential Z: out bit); Structural description
circuits
end component AND2;
component OR2 is A
FSMD
design
port ( X,Y: in bit; W
Z: out bit);
S Y
end component OR2;
VHDL
component INV is U V
port ( X: in bit;
Z: out bit); B
end component INV;
begin
Gate1: component INV port map (X=>S,Z=>U);
Gate2: component AND2 port map (X=>A,Y=>S,Z=>W);
Gate3: component AND2 port map (X=>U,Y=>B,Z=>V);
Gate4: component OR2 port map (X=>W,Y=>V,Z=>Y);
5/29 end architecture Struct;
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Example 3
Digital
• Assume that we want to use the
design
previously declared AND3, OR3 and INV
Combina- for this structural description of MUX
torial
circuits
configuration Use3InputGates of MUX21 is
Sequential for Behav Entities
circuits A
end for; Y
for Struct B
FSMD for Gate1:INV use entity INV(RTL) C
design
port map (A=>X,Y=>Z);
end for; A Y
VHDL
for All:AND2 use entity AND3(RTL)
port map (A=>X,B=>Y,C=>’1’,Y=>Z);
end for;
for Gate4:OR2 use entity OR3(RTL) Components
port map (A=>X,B=>Y,C=>’0’,Y=>Z);
X
end for; Z
end for;
Y
end configuration Use3InputGates;
X Z
5/30
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Test bench
Digital
• How can we verify the circuit that we
design
made?
Combina- We have to apply representative stimuli
torial
circuits to the circuit
and check whether the outputs are correct
Sequential
circuits
• A VHDL ‘test bench’ can be considered to
FSMD be the top level of a design
design
It instantiates the Design Under Test (DUT)
VHDL applies stimuli to it
checks whether the stimuli are correct
or
captures the outputs for visualisation in a
waveform viewer
5/31
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Test bench
Digital
• Create a test bench for the behavioral
design
version of the MUX
Combina- entity Testbench is Testbench is A
torial
circuits end entity Testbench; self-contained: Y
B MUX21
no ports
Sequential
circuits S
5/32
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Re-use
Digital
• Often, parts of a design can be re-used in
design
another design
Combina- • New products in industry often contain
torial
circuits 95% of re-used parts and 5% is newly
Sequential
designed: evolutionary design
circuits
• VHDL encourages this by the concept of
FSMD ‘Packages’
design
• A ‘Package’ contains definitions of
VHDL constant values, component declarations,
user data types, and sub-programs of
VHDL code
• But first the concept ‘Library’: a library is
name of directory into which the binary
code resulting from analysis/compilation is
5/33
stored. Default: WORK
A First look at VHDL:
©
R.Lauwereins
Imec 2001
Re-use
Digital
Package interface declaration:
design
package Package_name is
Combina- -- constants
torial -- user defined types
circuits -- component declarations
-- sub programs
Sequential end package Package_name;
circuits
FSMD
design
VHDL
How to use a package?
use Library_name.Package_name.all;
5/34
Language based HW design:
©
R.Lauwereins
Imec 2001
a VHDL primer
Digital
• Introduction
design
• A first look at VHDL
Combina-
torial
Signals and data types
circuits
• VHDL operators
Sequential
circuits • Concurrent versus sequential
statements
FSMD
design • Sequential construction statements
VHDL • Higher performance, less portability:
e.g. synthesis issues for Xilinx
5/35
Signals and Data Types:
©
R.Lauwereins
Imec 2001
5/36
Signals and Data Types:
©
R.Lauwereins
Imec 2001
5/37
Signals and Data Types:
©
R.Lauwereins
Imec 2001
Examples of use:
waitfor 20 ns;
constant Sample_period: time := 2 ms;
constant Clock_period: time := 50 ns;
5/38
Signals and Data Types:
©
R.Lauwereins
Imec 2001
5/39
Signals and Data Types:
©
R.Lauwereins
Imec 2001
5/40
Signals and Data Types:
©
R.Lauwereins
Imec 2001
Array types
Digital
design
The user may define arrays of types:
type 1D_array is array (1 to 10) of integer;
Combina- type 2D_array is array (5 downto 0, 1 to 10) of real;
torial
circuits
5/41
Signals and Data Types:
©
R.Lauwereins
Imec 2001
Standard logic
Digital
• We have seen that we need more logic
design
levels than just ‘0’ and ‘1’ (e.g. don’t care,
Combina- unknown after setup violation, …)
torial
circuits • Therefore the IEEE defined in standard
Sequential
number 1164 9-valued logic signals and
circuits operations on them: use always those
FSMD
instead of ‘bit’!!
design
• Exists in unresolved form (std_ulogic) and
VHDL resolved form (std_logic) -- again: see later
for meaning
• Exists in single bit and array form:
constant A: std_ulogic := ‘U’; -- unitialized
constant B: std_logic := ‘U’;
constant C: std_ulogic_vector (0 to 15);
5/42
constant D: std_logic_vector (15 downto 0);
Signals and Data Types:
©
R.Lauwereins
Imec 2001
Standard logic
Digital
design library IEEE;
use IEEE.Std_logic_1164.All;
Combina-
torial type std_logic is (
circuits
‘U’, -- uninitialized e.g. after power-up
‘X’, -- strongly driven unknown e.g. after setup violation
Sequential
circuits ‘0’, -- strongly driven logic zero
‘1’, -- strongly driven logic one
FSMD
‘Z’, -- high impedance e.g. not driven at all
design ‘W’, -- weakly driven unknown
‘L’, -- weakly driven logic zero
VHDL ‘H’, -- weakly driven logic one
‘-’); -- don’t care
5/43
Signals and Data Types:
©
R.Lauwereins
Imec 2001
Assignment to signals
Digital Is the following code valid?
design
signal Z,A,B: std_ulogic;
Combina-
torial
Z <= A;
circuits
Z <= B;
Sequential
circuits No, because:
- all statements are concurrently valid and are not executed
FSMD sequentially as in SW languages
design
- when A=‘0’ and B=‘1’, we have a short circuit
VHDL
A A Resolver
circuit
R
Z Z
B B
5/44
Signals and Data Types:
©
R.Lauwereins
Imec 2001
Assignment to signals
Digital
• VHDL is a single assignment language for
design
unresolved data types
Combina-
torial
• For resolved data types (std_logic &
circuits std_logic_vector), the resolver circuit is
Sequential
inferred by the synthesis tool
circuits
FSMD
design
A Resolver
signal Z,A,B: std_logic; circuit
VHDL
Z <= A;
R
Z <= B;
B Z
5/45
Signals and Data Types:
©
R.Lauwereins
Imec 2001
Assignment to signals
Digital
• When an array is assigned to another
design
array, both arrays must have same size
Combina-
torial
• Assignment is by position, not by index!!!
circuits
signal Down: std_logic_vector (3 downto 0);
Sequential signal Up: std_logic_vector (0 to 3);
circuits
Up <= Down;
FSMD
design
Which of the two following interpretations is correct?
VHDL
Assignment to signals
Digital
• Assignment to a part of an array is
design
possible
Combina-
torial
• Make sure that the direction (to or
circuits downto) is the same as in the declaration
Sequential signal Bus: std_logic_vector (7 downto 0);
circuits
signal A: std_logic_vector (0 to 3);
Assignment to signals
Digital
• ‘Concatenation’: bring wire bundles
design
together to assign them to a bigger array
Combina- signal Byte_bus: std_logic_vector(7 downto 0);
torial
circuits
signal Nibble_busA, Nibble_busB: std_logic_vector(3 downto 0);
5/48
Signals and Data Types:
©
R.Lauwereins
Imec 2001
Assignment to signals
Digital
• ‘Aggregation’: alternative method to
design
assign multiple small arrays to a bigger
Combina- array
torial
circuits • Not supported by all synthesis tools!!
Sequential
circuits signal X,Y,Z,T: std_logic_vector(3 downto 0);
signal A,B,C: std_logic;
FSMD
design X <= (A,B,C,C); -- correspondence by position
5/49
Signals and Data Types:
©
R.Lauwereins
Imec 2001
Generic constants
Digital
• Allows to parameterize behavior
design
• Enables re-use of entities in slightly
Combina-
torial
changing environments
circuits
• Makes VHDL much more powerful than
Sequential schematic entry
circuits
• Generic constants need to have a value at
FSMD
design
synthesis time!
entity General_mux is
VHDL
generic (width : integer);
port ( Input : in std_logic_vector (width - 1 downto 0);
Select : in integer range 0 to width - 1;
Output : out std_logic);
end entity General_mux;
5/50
©
R.Lauwereins
Imec 2001
Generic constants
entity General_mux is
generic (width : integer);
port ( Input : in std_logic_vector (width - 1 downto 0);
Digital Select : in integer range 0 to width - 1;
design Output : out std_logic);
end entity General_mux; This is not valid VHDL:
Combina- index is not known at
torial architecture Behav of General_mux is design time! We will
circuits
begin replace this by valid
Output <= Input(Select); code later!
Sequential
circuits
end architecture Behav;
entity Testbench is
FSMD
design
end entity Testbench;
a VHDL primer
Digital
• Introduction
design
• A first look at VHDL
Combina-
torial • Signals and data types
circuits
VHDL operators
Sequential
circuits • Concurrent versus sequential
statements
FSMD
design • Sequential construction statements
VHDL • Higher performance, less portability:
e.g. synthesis issues for Xilinx
5/52
©
R.Lauwereins
Imec 2001
Logical Operators
Digital
• List of logical operators: not, and, or, xor,
design
nand, nor
Combina-
torial
• Precedence:
circuits ‘not’ has highest precedence
Sequential
all others have equal precedence, lower than
circuits ‘not’
FSMD • Logical operators are predefined for
design
following data types: bit, bit_vector,
VHDL boolean, std_logic, std_logic_vector,
std_ulogic, std_ulogic_vector
• A logical operator may work on an array:
arrays should have same size
elements are matched by position
5/53
©
R.Lauwereins
Imec 2001
Logical Operators
Digital
design
library IEEE;
Combina- use IEEE.Std_Logic_1164.All;
torial
circuits
entity Gate is
Sequential port( A,B,C: in std_logic;
circuits Z: out std_logic);
end entity Gate;
FSMD
design architecture Logical of Gate is
begin
VHDL Z <= A and not(B or C);
end architecture Logical;
5/54
©
R.Lauwereins
Imec 2001
Logical Operators
Digital
design
library IEEE;
Combina- use IEEE.Std_Logic_1164.All;
torial
circuits entity Gate is
generic(width : integer range 0 to 31);
Sequential port( A,B,C: in std_logic_vector(width-1 downto 0);
circuits
Z: out std_logic_vector(width-1 downto 0));
end entity Gate;
FSMD
design
architecture Logical of Gate is
begin
VHDL
Z <= A and not(B or C);
end architecture Logical;
5/55
©
R.Lauwereins
Imec 2001
Relational Operators
Digital
• List of relational operators: <, <=, =>, >,
design
=, /=
Combina- • Relational operators return a boolean
torial
circuits
• Both operands need to be of the same
Sequential type
circuits
• A relational operator may work on an
FSMD
design
array:
arrays may have different size!!
VHDL
They are left alligned and the number of bits
equal to the smallest array are compared; the
comparison is done bit by bit, from left to right
Remember: vectors of bits do not have a
numerical meaning!! However, this comparison
works on vectors of bits with the meaning of an
unsigned integer when both vectors have equal
5/56
length
Relational Operators
©
R.Lauwereins
Imec 2001
library IEEE
use IEEE.Std_Logic_1164.All;
Digital
What is the
design entity Compare is value of Z?
port( A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(0 to 4); TRUE?
Combina-
torial Z: out boolean); FALSE?
circuits end entity Compare;
Digital
• List of arithmetic operators: +, -, *, /, **
design
(exponential), abs (absolute value), mod
Combina- (modulus), rem (remainder)
torial
circuits • They are defined on types integer and
Sequential
real (except mod and rem) and not on
circuits
vectors of bits; use overloading package
FSMD for the latter (vendor dependent)
design
• Both operands have to be of same type;
VHDL different ranges are allowed
• A variable of physical type (e.g. time) may
be multiplied by an integer or real and will
still return a variable of the physical type
5/58
©
R.Lauwereins
Imec 2001
Arithmetic Operators
VHDL
5/59
Language based HW design:
©
R.Lauwereins
Imec 2001
a VHDL primer
Digital
• Introduction
design
• A first look at VHDL
Combina-
torial • Signals and data types
circuits
• VHDL operators
Sequential
circuits
Concurrent versus sequential
statements
FSMD
design • Sequential construction statements
VHDL • Higher performance, less portability:
e.g. synthesis issues for Xilinx
5/60
©
R.Lauwereins
Imec 2001
Concurrent Statements
Digital
• All statements are concurrent and are
design
continuously valid: this mimics the
Combina- behavior of hardware, where all gates
torial
circuits operate concurrently
Sequential
circuits entity Concurrent is
port ( A,B,C,D: in std_logic; Schematic:
FSMD Y,Z: out std_logic);
design
end entity Concurrent;
A
VHDL
architecture Struct of Concurrent is Y
B
begin
NAND1: entity NAND2 port map (A,B,Y); C
Z
NAND2: entity NAND2 port map (C,D,Z); D
end architecture Struct;
Digital
• All statements are concurrent and are
design
continuously valid: this mimics the
Combina- behavior of hardware, where all gates
torial
circuits operate concurrently
Sequential
circuits entity Concurrent is
port ( A,B,C,D: in std_logic; Schematic:
FSMD Y,Z: out std_logic);
design
end entity Concurrent;
A
VHDL
architecture Struct of Concurrent is Y
B
begin
NAND2: entity NAND2 port map (C,D,Z); C
Z
NAND1: entity NAND2 port map (A,B,Y); D
end architecture Struct;
5/62
©
R.Lauwereins
Imec 2001
Concurrent Statements
Does this schematic specify sequential Behavior?
Digital
design
Yes Schematic:
Combina- No
torial
circuits
A
entity Concurrent is B T1
Sequential
port ( A,B, D: in std_logic;
circuits Z: out std_logic); Z
end entity Concurrent; D
FSMD
design architecture Struct of Concurrent is
signal T1: std_logic;
VHDL begin
NAND2: entity NAND2 port map (T1,D,Z);
NAND1: entity NAND2 port map (A,B,T1);
end architecture Struct;
5/63
©
R.Lauwereins
Imec 2001
Simulation
Digital
• This continuously updating of outputs
design
poses problems to the simulator: even if
Combina- nothing in the circuit changes, the
torial
circuits simulator has to compute continuously
the ‘new’ outputs of all gates
Sequential
circuits
• Solution: event-driven simulation
FSMD a statement is only re-evaluated when one or
design more of its input signals changes (i.e. when an
event occurs at one of its inputs)
VHDL
we say that a statement is sensitive to all its
input signals, because an event at any input
signals triggers a re-evaluation
keep in mind that this mechanism is only for
making simulation fast while maintaining the
same behavior as in reality, where all gates
work continuously!!
5/64
©
R.Lauwereins
Imec 2001
Simulation
Digital
• How is an event-driven simulator
design
practically implemented?
Combina- 1. Put all statements with at least one changed input in the
torial
circuits ‘process execution queue’
2. Execute all statements in the process execution queue
Sequential one by one (or concurrently if the simulator is executed
circuits
on a parallel computer) without updating the output signals
Delta cycle
Delta cycle convergence
5/65
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2
B NAND1 NAND1
NAND2
Q
Q’
Step 1: Put statements with input
T1 T2 event in PEQ
5/66
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q’ <= 1
B NAND1 NAND1
NAND2
Q
Q’
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/67
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q’ <= 1
B NAND1
NAND2 NAND1
NAND2
Q
Q’
Step 3: Update outputs
T1 T2
5/68
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2
B NAND2 NAND1
NAND2
Q
Q’
Step 4: Add statements with event
T1 T2 to PEQ
5/69 End Delta cycle 1 of T1
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q <= 0
B NAND2 NAND1
NAND2
Q
Q’
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/70
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q <= 0
B NAND2 NAND1
NAND2
Q
Q’
Step 3: Update outputs
T1 T2
5/71
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2
B NAND1 NAND1
NAND2
Q
Q’
Step 4: Add statements with event
T1 T2 to PEQ
5/72 End Delta cycle 2 of T1
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q’ <= 1
B NAND1 NAND1
NAND2
Q
Q’
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/73
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q’ <= 1
B NAND1 NAND1
NAND2
Q
Q’
Step 3: Update outputs
T1 T2
5/74 Output does not change
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2
B NAND1
NAND2
Q
Q’
Step 4: Add statements with event
T1 T2 to PEQ
5/75 End Delta cycle 3 of T1: convergence
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2
B NAND1
NAND2
Q
Q’
Step 6: Advance system time
T1 T2
5/76
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q’ <= 1
B NAND1
NAND2
Q <= 1
NAND2
Q
Q’
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/77 NAND2 computed using this Q’, not the remembered
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q’ <= 1
B NAND1
NAND2
Q <= 1
NAND2
Q
Q’
Step 3: Update outputs
T1 T2
5/78
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2
B NAND1
Q’
Step 4: Add statements with event
T1 T2 to PEQ
5/79 End Delta cycle 1 of T2
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q’ <= 0
B NAND1
Q’
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/80
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q’ <= 0
B NAND1
Q’
Step 3: Update outputs
T1 T2
5/81
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2
B NAND2
Q’
Step 4: Add statements with event
T1 T2 to PEQ
5/82 End Delta cycle 2 of T2
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q <= 1
B NAND2
Q’
Step 2: Execute statements in PEQ
T1 T2 and remember output
5/83
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Remembered Execution Execution
VHDL Outputs Queue Queue
A T1 T2
Q <= 1
B NAND2
Q’
Step 3: Update outputs
T1 T2
5/84 Output does not change
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2
Q’
Step 4: Add statements with event
T1 T2 to PEQ
5/85 End Delta cycle 3 of T2: convergence
©
R.Lauwereins
Imec 2001
Simulation
entity Flipflop is A
Q’
Digital port ( A,B: in std_logic;
design Q,Q’: out std_logic);
end entity Flipflop; Q
Combina- B
torial architecture Struct of FlipFlop is
circuits
begin
NAND2: entity NAND2 port map (Q’,B,Q);
Sequential
circuits
NAND1: entity NAND2 port map (A,Q,Q’);
end architecture Struct;
FSMD
design Process Process
Execution Execution
VHDL Queue Queue
A T1 T2
Q’
Step 6: Advance system time
T1 T2
5/86
©
R.Lauwereins
Imec 2001
Process
Digital
• Sometimes, the combinatorial equation in
design
a single statement becomes very
Combina- complicated:
torial A
circuits B
C
Sequential
circuits D Y
entity Complex is E
FSMD
design
port( A,B,C,D,E,F,G,H,I,J: F S
in std_logic; G
Y,Z: out std_logic);
VHDL H
end entity Complex;
I Z
architecture Struct of Complex is J
begin
Y <= ((A nand B) nand (C nand D))
when (S = ‘1’) else
((E nand F) nand (G nand H));
Z <= I nand J;
end architecture Struct;
5/87
©
R.Lauwereins Unfortunately, in VHDL
Imec 2001
Process terminology they are
also called ‘Statements’
Digital
• Therefore a process has been defined:
design
a process acts as a single statement that is
Combina-
executed concurrently with all other statements
torial inside a process, commands are executed
circuits
sequentially in the order they are listed. This
Sequential
makes it easy to break down a very complicated
circuits statement into a list of smaller commands
to pass data from one command to the other,
FSMD
design we may declare temporary variables; they do
not have necessarily a physical realization
VHDL a statement, and hence also a process, is
sensitive to all its input signals; to facilitate
finding out what the input signals of a process
are, since they can occur in any command, we
have to explicitly add them to a sensitivity list.
A process is recalculated when a signal in the
sensitivity list has an event.
5/88
©
R.Lauwereins
Imec 2001
Process
Digital
Syntax of process:
design
Process_name: process (sensitivity_list) is
Combina- -- variable declarations;
torial begin
circuits -- sequential commands
end process Process_name;
Sequential
circuits
Variable_name := expression;
Digital
• Processes and delta cycle convergence.
design
What is the behavior of following process:
Combina- Example: process (A,B,M) is
torial
circuits begin
Y <= A; Old M!!! M gets
M <= B; only new value
Sequential at end of process
circuits Z <= M;
end process Example;
FSMD
design 1. Assume event at B with new value B’
2. Process Example is executed once sequentially. Following
VHDL outputs are remembered: Y’ <= A; M’ <= B’; Z’ <= M;
3. Process Example suspends (i.e. is executed once completely).
Y, M and Z get their new values Y’, M’, Z’.
4. Since M is in the sensitivity list, the Example process is
placed again in the Process Execution Queue.
5. Process Example is executed: Y” <= A; M” <= B’; Z” <= M’;
6. Outputs Y, M and Z get their new values Y”, M”, Z”.
7. No signals of the sensitivity list changed => delta cycle
5/91 convergence
©
R.Lauwereins
Imec 2001
Process
Digital
• Processes and delta cycle convergence.
design
What is the behavior of following process:
Combina-
torial Example: process (A,B,C,D) is
circuits begin
Z <= A + B;
Sequential Z <= C + D;
circuits
end process Example;
FSMD
design 1. Assume event at B with new value B’
2. The commands of Process Example are executed
VHDL sequentially. First following output is remembered:
Z’ <= A + B’;
3. Next, the second command is executed and following output
is remembered: Z’ <= C + D. This overwrites the previously
remembered Z’
4. Process Example suspends and hence signal Z is updated
with its new value C + D
When the same two statements would have occurred outside a
process, both would drive signal Z and a resolver would be
necessary
5/92
Language based HW design:
©
R.Lauwereins
Imec 2001
a VHDL primer
Digital
• Introduction
design
• A first look at VHDL
Combina-
torial • Signals and data types
circuits
• VHDL operators
Sequential
circuits • Concurrent versus sequential
statements
FSMD
design Sequential construction statements
VHDL • Higher performance, less portability:
e.g. synthesis issues for Xilinx
5/93
Sequential construction
©
R.Lauwereins
Imec 2001
statements
Sequential construction statements are only allowed within a process!!!
•
Digital There are 3 sequential construction statements: IF, CASE, FOR
•
design
Combina-
torial
circuits
Sequential IF statement:
circuits
if condition then
FSMD -- sequential statements
design multiple IF statements:
else
-- sequential statements
VHDL
end if; if condition1 then
-- sequential statements
elseif condition2 then
-- sequential statements
The first condition which elseif condition3 then
turns out to be TRUE -- sequential statements
determines which else
sequential statements are -- sequential statements
executed: built-in priority end if;
5/94
Sequential construction
©
R.Lauwereins
Imec 2001
statements
case Expression is
Digital when Value_1 =>
design
-- sequential statements
when Value_2 =>
Combina-
torial -- sequential statements
circuits -- etc.
end case; Requirements:
Sequential
circuits
1. All possible values should
be specified
FSMD Example: process (A,B,C,X) is
design begin 2. The values should be
case X is constant and known at
VHDL when 0 to 4 => design time
Z <= B; 3. The values should have the
when 5 => same type as the
Z <= C; expression
when 7 | 9 =>
Z <= A;
when others =>
Z <= ‘0’;
end process Example;
5/95
Sequential construction
©
R.Lauwereins
Imec 2001
statements
Digital
design for I in 0 to 3 loop
-- sequential statements
Combina- end loop;
torial
circuits Remarks:
VHDL
5/96
Sequential construction
©
R.Lauwereins
Imec 2001
statements
entity General_mux is
Digital generic (width : integer);
design
port ( Input : in std_logic_vector (width - 1 downto 0);
Select : in integer range 0 to width - 1;
Combina-
torial Output : out std_logic);
circuits end entity General_mux;
5/97
Sequential construction
©
R.Lauwereins
Imec 2001
statements
Digital
design entity General_mux is
generic (width : integer);
Combina- port ( Input : in std_logic_vector (width - 1 downto 0);
torial Select : in integer range 0 to width - 1;
circuits Output : out std_logic);
end entity General_mux;
Sequential
circuits
architecture Behav of General_mux is
begin
FSMD Selector: process (Input, Select) is
design
begin
for I in 0 to width-1 loop
VHDL
if Select=I then
Output <= Input(I);
end if;
end loop;
end process Selector;
end architecture Behav;
5/98
©
R.Lauwereins
Imec 2001
Variables
Digital
• A variable can only be used within a
design
process
Combina-
torial
• A variable is updated immediately; a
circuits signal is stored in the signal update
Sequential
queue till the process suspends
• Variables may be assigned to signals and
circuits
5/99
©
R.Lauwereins
Imec 2001
Variables
With which hardware schematic does following code correspond?
Digital
design entity Parity is
generic (width : integer);
Combina- port (A: in std_logic_vector (0 to width-1);
torial
circuits
Odd: out std_logic);
end entity Parity; This is the HW structure
as it is given to the synthesis
Sequential
circuits architecture Struct of Parity is tool. The synthesis tool
begin will optimize away the xor
FSMD Parity: process(A) is with constant ‘0’ input
design variable Temp: std_logic; and will transform it to
begin a binary tree of less depth
VHDL Temp := ‘0’;
for I in A’low to A’high loop
Temp := Temp xor A(I); 0 Temp
end loop; A(0)
Odd <= Temp;
end process Parity; Temp
end architecture Struct; A(1)
Odd
A(2)
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Imec 2001
Rising clock edge
With which function does following code correspond?
Digital
design
entity What is
port (D,Clk: in std_logic;
Q: out std_logic);
Combina-
torial end entity What;
circuits Since there is no ELSE part
architecture RTL of What is the previous Q value has
Sequential begin to be remembered for the case
circuits process (D, Clk) is where Clk=‘0’.
begin The synthesis tool will hence
FSMD if (Clk=‘1’) then infer a latch instead of just
design
Q <= D; combinatorial logic!!!
end if;
VHDL end process; Beware of unintended latches
end architecture RTL; when ELSE parts are omitted
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©
R.Lauwereins
Imec 2001
Rising clock edge
How do we describe a rising clock edge?
Digital
design Method 2: Sensitivity list Preferred method!
5/103
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Imec 2001
Rising clock edge
How do we describe combinatorial circuits with registered outputs?
Digital
design
A
Combina- B Z
torial
circuits
C
Sequential Method 1: WAIT UNTIL
circuits
D
entity RegisteredCircuit is
FSMD port (A,B,C,D,Clk: in std_logic;
design Z: out std_logic);
end entity RegisteredCircuit; ‘Wait until’ has to be
VHDL first line of process,
architecture RTL of RegisteredCircuit is followed by
begin the description of the
process is combinatorial circuit
begin
wait until Clk’event and Clk=‘1’;
-- combinatorial circuit
Z <= (A and B) or (C and D);
end process;
end architecture RTL;
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Imec 2001
Rising clock edge
How do we describe combinatorial circuits with registered outputs?
Digital
design
A
Combina- B Z
torial
circuits
Method 2: Sensitivity list
C
Sequential
circuits entity RegisteredCircuit is D
port (A,B,C,D,Clk: in std_logic;
FSMD
Z: out std_logic);
design end entity RegisteredCircuit;
‘if Clk’event’ has to be
first line of process,
VHDL architecture RTL of RegisteredCircuit is
with the description
begin
of the combinatorial
process (A,B,C,D,Clk) is
circuit in the THEN
begin
part and with no
if (Clk’event and Clk=‘1’) then
ELSE part
-- combinatorial circuit
Z <= (A and B) or (C and D);
end if;
end process;
end architecture RTL;
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Imec 2001
Rising clock edge
Digital
• The amount of logic we describe in the
design
combinatorial part, determines the
Combina- combinatorial delay
torial
circuits • It hence determines the maximum clock
Sequential
frequency with which we can clock the
circuits
flip-flop
FSMD • Re-timing requires re-writing the VHDL
design
code
VHDL
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Imec 2001
Rising clock edge
How do we describe flip-flops with asynchronous reset?
Digital
design
entity DFlipFlop is
Combina-
torial
port (D,Clk, Reset: in std_logic;
circuits Q: out std_logic);
end entity DFlipFlop;
Sequential
circuits architecture RTL of DFlipFlop is
begin
FSMD process (D, Clk, Reset) is
design begin
if (Reset = ‘1’) then
VHDL Q <= ‘0’;
elseif (Clk’event and Clk=‘1’) then
Q <= D;
end if;
end process;
end architecture RTL;
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Imec 2001
Rising clock edge
How do we describe flip-flops with synchronous reset?
Digital
design
entity DFlipFlop is
port (D,Clk, Reset: in std_logic;
Combina-
torial
Q: out std_logic);
circuits end entity DFlipFlop;
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Imec 2001
Finite State Machine
Digital Start=0
design
Wait
Combina- Reset Start=1 00
torial Out Output Start=1
circuits Up=1 Up=0
put
logic
Sequential
circuits
Up1 Down3
State 01 11
Reg CurrentState
FSMD
design
Up3 Down1
11 01
Start Up
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Imec 2001
Finite State Machine
entity FSM is
Digital
port ( Start, Up, Reset, Clk: in std_logic; Start=0
design Output: out std_logic_vector(0 to 1));
end entity FSM;
Wait
Combina- 00
torial architecture Behav of FSM is Start=1 Start=1
circuits type FSM_States = (Wait,Up1,Up2, Up=1 Up=0
Up3,Down1,Down2,Down3);
Sequential signal CurrentState, NextState : Up1 Down3
circuits
FSM_States; 01 11
begin
FSMD
design
OutputLogic:
process(CurrentState) is
… Up2 Down2
VHDL
end process OutputLogic; 10 10
NextStateLogic:
process(CurrentState,Start,Up) is
…
end process NextStateLogic; Up3 Down1
StateRegister: 11 01
process(NextState,Clk,Reset) is
…
end process StateRegister;
5/110 end architecture Behav;
©
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Imec 2001
Finite State Machine
Digital Start=0
design
Wait
Combina- 00
torial OutputLogic: Start=1 Start=1
circuits process(CurrentState) is Up=1 Up=0
begin
Sequential case CurrentState is Up1 Down3
circuits
when Wait => 01 11
Output <= “00”;
FSMD
design
when Up1|Down1 =>
Output <= “01”;
when Up2|Down2 => Up2 Down2
VHDL
Output <= “10”; 10 10
when Up3|Down3 =>
Output <= “11”;
end case;
end process OutputLogic; Up3 Down1
11 01
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Imec 2001
Finite State Machine
NextStateLogic:
Digital
process(CurrentState,Start,Up) is Start=0
design begin
case CurrentState is
Wait
Combina- when Wait =>
Start=1 00 Start=1
torial if (Start=‘0’) then
circuits NextState <= Wait; Up=1 Up=0
elseif (Up=‘1’) then
Sequential NextState <= Up1; Up1 Down3
circuits
else 01 11
NextState <= Down3;
FSMD
design
end if;
when Up1 =>
NextState <= Up2; Up2 Down2
VHDL
when Up2 => 10 10
NextState <= Up3;
when Up3|Down1 =>
NextState <= Wait;
when Down3 => Up3 Down1
NextState <= Down2; 11 01
when Down2 =>
NextState <= Down1;
end case;
5/112 end process NextStateLogic;
©
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Imec 2001
Finite State Machine
Digital Start=0
design
Wait
Combina- 00
torial Start=1 Start=1
circuits Up=1 Up=0
Sequential StateRegister:
circuits process(NextState,Clk,Reset) is Up1 Down3
begin 01 11
FSMD if Reset=‘1’ then
design CurrentState <= Wait;
elseif (Clk’event and Clk=‘1’) then
VHDL CurrentState <= NextState; Up2 Down2
end if; 10 10
end process StateRegister;
Up3 Down1
11 01
5/113
Language based HW design:
©
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Imec 2001
a VHDL primer
Digital
• Introduction
design
• A first look at VHDL
Combina-
torial • Signals and data types
circuits
• VHDL operators
Sequential
circuits • Concurrent versus sequential
statements
FSMD
design • Sequential construction statements
VHDL Higher performance, less portability:
e.g. synthesis issues for Xilinx
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Imec 2001
Resource sharing
What is the circuit corresponding to: A B A C
Digital
design
if Sel = ‘1’ then
Z <= A + B;
Combina-
else + +
torial
circuits Z <= A + C;
end if;
Sequential Sel
circuits MUX
This is kind of stupid, since both
FSMD additions are mutually exclusive: Z
design it is hence not necessary to
implement 2 adders.
VHDL
B C A
Some synthesis tools are capable
to recognize this (often only within MUX
Sel
the scope of a process) and
transform this into the shared use
of one adder for both additions.
Xilinx Foundation Series performs
+
this optimization within a
hierarchical level.
5/115 Z
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Imec 2001
Resource sharing
If the synthesis tool does not do B C A
Digital
design this optimization automatically,
you should re-write your code: MUX
Sel
Combina-
torial
circuits
if Sel = ‘1’ then
X := B;
else
Sequential +
circuits X := C;
end if;
Z <= A + X; Z
FSMD
design
VHDL
The VHDL coding style together with the capabilities of the
synthesis tool determine the circuit that is eventually
synthesized.
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Imec 2001
Using LogiBLOX in VHDL
Digital
• LogiBLOX modules lead to highly efficient
design
FPGA implementations
Combina-
torial
• The LogiBLOX module generator creates,
circuits apart from the FPGA implementation, also
Sequential
a behavioral level VHDL module for
circuits
simulation!
FSMD • How to use LogiBLOX modules in your
design
VHDL code:
VHDL use the package containing the LogiBLOX
modules: library My_Library; use
My_Library.My_Package.all;
instantiate the entity
• Using LogiBLOX makes your VHDL
implementation more efficient on Xilinx
FPGA but less portable to other devices!!
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Imec 2001
Encoding of State Machines
Digital
• The default encoding in Foundation
design
Express is one-hot since this matches
Combina- well with the structure of a CLB (little bit
torial
circuits of combinatorial logic in front of a D-flip-
flop)
Sequential
circuits
• The encoding can be specified in the
FSMD VHDL code:
design
type State_Type is (S1, S2, S3, S4);
VHDL attribute ENUM_ENCODING: string;
attribute ENUM_ENCODING of State_Type: type is “11 10 01 00”;
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Imec 2001
Safe state machines
Digital
• Assume a state
design
machine of three
Combina- states, encoded with
NextStateLogic:
torial
circuits 2 bits process(CurrentState) is
Sequential
• What would happen begin
case CurrentState is
circuits
when the state when Idle =>
FSMD machine enters the NextState <= S1;
when S1 =>
design
4th state, due to NextState <= S2;
VHDL some error (noise, when S2 =>
NextState <= Idle;
power-up, …)? Will it when others =>
be able to recover? NextState <= Idle;
end case;
• Make provisions for end process NextStateLogic;
this situation in your
VHDL code:
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Family specific issues
Digital
• Not all families provide per flip-flop both
design
asynchronous set as well as reset.
Combina-
torial
• Check what your family provides before
circuits you write VHDL
Sequential
circuits process (Clk, Rst, Set) is Can only be implemented
begin efficiently when the
FSMD if Rst = ‘1’ then family has both an
design
Q <= ‘0’; asynchronous set
elseif Set = ‘1’ then as well as reset
VHDL
Q <= ‘1’;
elseif Clk’event and Clk = ‘1’ then
-- actions
end if;
end process;
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Family specific issues
Digital
• Always use LogiBLOX for RAM, because
design
RAM would otherwise be created out of
Combina- separate flip-flops
torial
circuits
Sequential
circuits
FSMD
design
VHDL
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Imec 2001
I/O buffer types
Digital
• Put all the core logic in one entity
design
• In a higher hierarchical level, instantiate
Combina-
torial
the I/O buffers as well as the core logic
circuits
• The hierarchy hence becomes
Sequential Top level: test bench instantiating DUT
circuits
DUT: Instantiation of core logic and I/O buffers
FSMD Core logic: real design
design
VHDL
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Imec 2001
I/O buffer types
How to force a 3-state output buffer:
Digital Enable
design if (Enable = ‘1’) then
Out_pad
Out_pad <= Bus_out; Bus_out
Combina- else
torial
circuits
Out_pad <= ‘Z’;
end if;
Sequential
circuits
FSMD
design
How to force a bidirectional buffer:
VHDL
Bus_in <= Bidi_pad;
process (Enable, Bus_out) is Enable
begin
if (Enable = ‘1’) then Bus_out
Bidi_pad <= Bus_out; Bidi_pad
else
Bidi_pad <= ‘Z’;
end if; Bus_in
end process;
5/123
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Imec 2001
I/O buffer types
How to force a bidirectional buffer with registered output:
Digital
design
Bus_in <= Bidi_pad;
process (Enable,Q) is
begin
Combina-
torial if (Enable = ‘1’) then
circuits Bidi_pad <= Q;
else
Sequential Bidi_pad <= ‘Z’;
circuits end if;
end process;
FSMD process (Clk, Bus_out) is
design
begin
if Clk’event and Clk = ‘1’ then
VHDL Q <= D;
end if;
end process; Clk Enable
Bus_out
D Q Bidi_pad
Bus_in
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Imec 2001
I/O buffer types
How to force a pull-up resistor at an input:
Vcc
Digital entity Pullup_in is
design
port ( In_pad: in std_logic; In_pad
Core_in: out std_logic); Core_in
Combina- end entity Pullup_in;
torial
circuits
architecture RTL of Pullup_in is
Sequential
circuits component PULLUP
port (O: out std_logic);
FSMD end component PULLUP;
design
component IBUF
VHDL port (I: in std_logic; O: out std_logic);
end component IBUF;
begin
Dummy <= In_pad;
PU: component PULLUP port map (Dummy);
Buf: component IBUF port map (Dummy,Core_in);
end architecture RTL;
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Imec 2001
Using the Global Set Reset block
Digital
design entity OneHot is
port ( Rst, Clk: in std_logic;
Combina- Q: out std_logic_vector (0 to 3));
torial end entity OneHot;
circuits
architecture Behav of OneHot is
Sequential
circuits
component STARTUP
port (GSR: out std_logic);
FSMD end component STARTUP;
design
begin
VHDL
U1: component STARTUP port map (Rst => GSR);
if Rst = ‘1’ then
Q <= “0001”;
elseif Clk’event and Clk = ‘1’ then
Q <= Q(1 to 3) & Q(0);
endif;
end architecture RTL;
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Clock Networks
Digital
• Foundation Express synthesizes
design
automatically clock buffers
Combina-
torial
• Check whether you do not need more
circuits clock buffers than are available in the
Sequential
target family
circuits
FSMD
design
VHDL
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