LAB MANUAL ON VLSI

LTIET/EC/VLSI/EXP.03

EXPERIMENT -03
AIM:
Implementation and verification of basic logic gates in Xilinx Spartan-3 FPGA using Xilinx ISE 13.4 tool.

OBJECTIVE: To write the VHDL code for AND, OR, NOT and ALL LOGIC GATE
and verify the result on output LEDs:

EQUIPMENTS:
1. FPGA-A board and its power supply.

THEORY:
1. VHDL SOURCE CODE: AND GATE:

2.

OR GATE:
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3.

NOT GATE:

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4.

ALL LOGIC GATE:

1.

WAVEFORM: AND GATE:

2.

OR GATE:

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LTIET/EC/VLSI/EXP.03

3.

NOT GATE:

4.

ALL LOGIC GATE:

1.

SCHEMATIC: AND GATE:

2.

OR GATE:

3.

NOT GATE:
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4.

ALL LOGIC GATE:

PROCEDURE:
1. Following files are provided that is useful for the design and implementation of basic logic gates: 1.BIT file. 2. UCF file. 3. VHDL file. Launch Impact and select output cable setup menu item. Select open cable plug-in and type in digilent_plugin. Right click in the Boundary Scan window to initialize Chain. The device is detected, give path for .bit file. Right click on the device and click on program. The output is mapped on the LED1. Switch IL0 and IL1 represents the input. Verify the truth table given below.

2. 3. 4. 5. 6. 7. 8. 9.

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CONCLUSION:

Date:

Signature of Faculty
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