Tng quan v thit k h thng s trn FPGA

Khi nim c bn So snh gia FPGA v ASIC Cc ngn ng m t phn cng (verilog v VHDL) Cc bc thit k Cc tools dng trong qu trnh hc tp Cch s dng cc tools ( gii thiu ISE v lSim)

M u
Theo truyn thng, thit k s (digital design) l qu trnh thit k v t c cc mch in theo phng php th cng bng cch s dng cc cng c nhp s mch. Do tch hp, phc tp ca mch ngy cng tng, thm vo mc cnh tranh trn th trng i hi ngi sn xut phi a sn phm ra mt cch nhanh chng v vi chi ph nh nht nn phng php th cng khng cn ph hp, thay vo l cc phng php thit k mi vi vic dng cc ngn ng m t phn cng trong qu trnh thit k.

Mt s thun li
Chu k pht trin nhanh, a ra th trng nhanh. Gim cc chi ph k thut. Cho php ti s dng thit k. Tng tnh linh ng. Dng phn mm trong qu trnh thit k. Kim tra, xc minh thit k tt hn, d dng hn.

FPGA (field-programable gate aray) Mch tch hp nhng cu hnh c th thay i ty thuc vo nh ca ngi dng sau khi sn xut.

ASIC (application-specific integrated circuit )

Mch tch hp m cu hnh khng th thay i sau khi sn xut. Mch c sn xut nhm p ng mt ng dng c th no .

 Ngay bc tng hp (synthesis) ASIC i hi rt cht ch, thm vo phn DFT (design for test) dng kim tra ring thit k chnh. ASIC i hi qu trnh kim tra rt nghim ngt, cn FPGA c th kim tra trc tip, sai lm li, kim tra tip.

FPGA (field-programable gate aray) Trn nn FPGA sn phm d dng ti s dng, nng cp. Sn phm cui cng l cc file np (nhng trn FPGA)

ASIC (application-specific integrated circuit ) Sau khi ch to khng c kh nng thay i. Sn phm cui cng l chp. Khi sn xut vi s lng ln th gi thnh r hn rt nhiu FPGA.

Vi mt s l do nu trn, cc thit k ban u hng n linh kin FPGA kim tra h thng v c thi gian sn xut nh, sau thit thit k c nh hng trn ASIC sn xut quy m ln hn.

Phn so snh FPGA vs. ASIC

ASIC: Thit k ng dng -> Thit k mch logic -> M phng -> Kim tra chc nng codes -> P&R (Place & Route bt k) -> Lm wafer (silicon) -> Test prototype (nu li quay li sa bn thit k logic) -> Sn xut hng lot (dng chip) -> Trin khai ng dng trn board.

FPGA: Nh sn xut: Thit k platform ca FPGA -> M phng + Kim tra chc nng ca platform -> P&R -> Lm wafer -> Sn xut chp FPGA hng lot + Tool h tr => Ngi s dng: Thit k ng dng -> Thit k mch logic -> M phng -> Kim tra chc nng code -> P&R (theo quy nh ca platform) -> codes ln platform FPGA -> trin khai ng dng trn board.

Quy trnh thit k h thng s trn FPGA

1. Ly kin, nhu cu th trng. 2. Hnh thnh mt bn bo co v sn phm d kin. 3. Chuyn n b phn nghin cu pht trin, hnh thnh specifications, nh hnh cc khi chc nng chnh. 4. Chuyn qua b phn RTL code, m t khi chc nng. 5. Chuyn nhm verification chun b cc cng c kim tra, khng t quay li 3. 6. Chuyn nhm lm layout. 7. Chuyn li nhm verification kim tra li. 8. Chn cng ngh ca nh sn xut. 9. Tapeout ti nh my, o kim nh gi sn phm.

Ngn ng m t phn cng HDL

Hc phn ny chng ta s tp trung vo vic tm hiu ngn ng m t phn cng HDL.

Khi nim HDL: l ngn ng lp trnh dng m hnh ha hot ng mong mun ca phn cng.
Hai ngn ng m t phn cng c s dng trong cng nghip v nghin cu l Veriog v VHDL. Verilog: c bt u pht trin t nm 1981 bi cng ty Gateway, n nm 1995 th c IEEE cng nhn. VHDL: bt u hnh thnh t nm 1981 theo chng trnh hp tc ca b quc phng M v c ng dng v cc thit b qun s.

Tm quan trng ca ngn ng HDL

Thit k c m t mc rt tru tng bng cch dng ngn ng HDL, ngi thit k c th vit ngn ng m t RTL m khng cn quan tm n cng ngh ch to. Cc cng c logic c th t ng chuyn i thit k n cng ngh ch to bt k. Nu mun dng mt cng ngh mi th ch cn nhp m t RTL vo cng c tng hp v to ra netlist mc cng mi, dng cng ngh ch to mi.

Qu trnh pht trin ca Verilog

Verilog HDL ra i vo u nm 1984 bi Gateway Design Automation, Ban u ch dng m phng v kim tra, n 1987 thm cng c tng hp, 1987 VHDL tr thnh 1 chun ngn ng m t phn cng ca IEEE, n 1993 th verilog c cng nhn bi IEEE, ngy nay trong lnh vc cng nghip th VHDL chim ~60% cn Verilog chim ~40%.

Verilog vs. VHDL

Kh nng: V kh nng m hnh tru tng cao th VHDL c u th hn so vi Verilog. Kiu d liu: Kiu d liu ca Verilog n gin hn VHDL. Tnh d hc: Verilog d hc vi ngi bt u. VHDL nh kiu mnh, nhiu cch m hnh mt mch in. Th vin: Verilog khng c khi nim v th vin. Cu trc mc thp, cao: VHDL c nhiu cu trc cho cu hnh mc cao. Verilog c cc cu trc rt tt cho m hnh mc thp. Cc ton t: Phn ln l ging nhau.

Nhng c tnh ca verilog

L mt ngn ng m t phn cng dng c t phn cng t mc transistor n mc hnh vi. H tr nh thi cho vic m t ti mc thut ton tru tng.

Cc cng c phc v thit k

M t thit k: microsoft office, open office RTL code: Notepad ++ EmEditor ISE Synthesis: Quartus (Altera) LEDA (Synopsys) Design Compiler (Synopsys) FPGA Compiler Synplify Leonardo Spectrum (Mentor Graphics) ISE Design Suite (Xilinx) Simulation: ModelSim (Mentor Graphics) VCS (Synopsys) ISE

H phng php thit k

C hai h phng php thit k: t trn xung di (top-down) v t di ln trn (bottom-up). Trong thit k top-down, chng ta thit k khi nh trc, sau tin hnh xy dng cc khi chc nng con. Ngc li, vi thit k bottom-up, trc tin xy dng thit k cc khi con, sau ghp chung li vi nhau. Thng thng 2 phng php trn s c kt hp vi nhau d pht huy u im ca nhau

Top-down
Top level block

Sub-block 1

Sub-block 2

Sub-block 3

Sub-block 4

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Bottom-up
Top level block

Macrocell 1

Macrocell 2

Macrocell 3

Macrocell 4

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Leaf cell

Dn nhp thit k
bc ny thit k c m t bng Verilog theo phng php phn cp t cao xung thp (top-down) Mt thit k hon chnh c th bao gm: Nhng linh kin mc cng hoc mc transistor. Cc module, c chc nng phc tp c m t mc hnh vi. Nhng linh kin c lit k bi cu trc bus.

RTL code
y l im khi u ca giai on thit k, cc vi kin trc c bin i thnh mt thit k bng cch m t n di dng ngn ng RTL (thc ra ch l m t li s khi mch, chc nng no bng ngn ng HDL), C nhiu cch to ra m RTL, nh dng cng c ha (gin nt, thi lung) to ra m Verilog (hay VHDL) hoc vit m RTL thay v dng ha, c hai phng php u kt thc vi vic m RTL tng hp c.

Testbench trong verilog

H thng khi thit k phi c kim tra xem thit k ng chc nng cha trc khi to ra phn cng, Nu m RTL c vit bng Verilog thi testbench cng vit bng Verilog va vi VHDL cng vy, Trong qu trnh chy m phng, nhng li thit k v s khng tng thch gia nhng linh kin dng trong thit k c pht hin, y cc kch thch (tn hiu ban u) vo u vo v kim tra ng ra xem dng sng hay vector kt qu c nh mong mun hay khng, D dng cng c m phng no th kt qu cui cng l kim tra m RTL ca thit k.

Tng hp
Trong bc ny m RTL c tng hp, y l qu trnh m trong m RTL c bin i thnh cng logic, cng logic c tng hp c cng chc nng ging nh c m t trong m RTL, Bc ny rt quan trng trong lung thit k, m bo cho c c kt qu ti u nht c th. Bc thit k ny i hi vic m t phn cng ca thit k phi c nhn ra, ch n mt ASIC, FPGA c th nh l thit b phn cng mc ch ca thit k thng tin v nh thi v m t chc nng cho qu trnh bin dch, tng hp sp xp v kt ni, thc hin chc nng ca phn cng mong mun

 Verilog l mt ngn ng m t phn cng dng c t phn cng t mc transistor n mc hnh vi. Ngn ng ny h tr nhng cu trc nh thi mc chuyn mch v tc thi, n cng c kh nng m t phn cng ti mc thut ton tru tng. Verilog HDL p ng tt c nhng yu cu cho vic thit k tng hp nhng h thng s. Ngn ng ny h tr vic m t cu trc phn cp ca phn cng t mc h thng n mc cng hoc n c mc cng tc chuyn mch.

S dng ISE trong thit k FPGA

Quy trnh thit k FPGA vi ISE Verilog
Nhp thit k mch in (s nguyn l, m ngun HDL ..) M phng chc nng (s dng Modelsim, Isim..) Tng hp (SynplifyPro, XST ca ISE)

Download, iu chnh (s dng chipscope phn tch, tm li)

Thc hin (gm ba bc: Translate, Map, Place&Route)

M phng thi gian (m phng sau tng hp, c gi chm cng)

To Project mi
M ISE Project Navigator Click FileNew Project...

Nhp m ngun thit k

Ca s qun l project->Chut phi->Newsource. Chn verilog module Chn ng dn v t tn->Next->Next->Finish.

 Giao din m ngun: Nhp m ngun->Save

Chc nng m phng thit k

1. Nhp kch thch m phng testbench bng verilog Ca s qun l project->Chut phi->Newsource. Chn Verilog Test Fixture t tn->Next->chn file ngun gn kt->Next->Finish

 Nhp m kch hot vo ca s->Save

2. M phng cp hnh vi Ca s Design->Simulation Kim tra li: Processes->Behavioral Check Syntax Kch hot: Kch p Simulate Behavior Model

3. S dng m phng ISim thit lp th t thi gian Thay i thi gian m phng: Nhp gi tr mi Thc hin chy nhiu ln: Kch nt Run All (F5)

Tng hp thit k
Ca s Design->Implementation Chn file nh->Chy Synthesize-XST

 Kim tra cnh bo, li trong ca s Console Kch p View RTL Schematic->OK

 Quan st cu trc ca thit k Kch p xem cc lp su bn trong

M phng thi gian

Ca s Design->Simulation Chn Post-Translate Ca s Processes->Simulate Post-translate Model

 Thit lp thi gian Quan st kt qu m phng. So snh.

Implementation
1. Gn chn tn hiu vi chn FPGA Ca s Design->Newsource Chn implementation Constraints File, t tn->Next

 Ca s lp trnh: Nhp gn chn tn hiu I/O Vic gn chn c th thc hin thng qua User ConstraintsI/O Pin Planning trong PlanAhead

2. Thc hin implement design Gm 3 thao tc: translate, Map, Place & Route Kch p Implement Design trong ca s Processes

Download v iu chnh
Ca s Processes: Kch p Configure Target Device To file .bit, m ca s iMPACT Qut thit b ni qua JTAG: Kch p Boundary Scan

 Initialize Chain Gn file cu hnh .bit vi FPGA tng ng

 Np chng trnh: IC->chut phi->Program Xut hin thng bo: Program Succeeded Quan st kt qu trn bo mch.