IN T S

Chng 5

Mch logic dy

M hnh mch logic dy

Mch logic dy (Sequential logic) l mch logic c tnh cht nh, c khu tr Trng thi tip theo ca mch logic dy ph thuc vo gi tr ca tp bin kch thch li vo v trng thi hin ti ca mch Mch logic dy thng hot ng ng b theo s iu khin ca tn hiu nhp clock

Flip-flop
Flip-flop l mch logic c hai trng thi n nh (bi-stable), n c th thay i hoc gi nguyn trng thi tu thuc vo cc tn hiu kch thch cc li vo ca n. Cc flip-flops c th c ng b t mt dy tn hiu nhp gi l clock (theo mc hoc sn xung clock) Dng flip flop n gin nht l R-S flip flop - c hai li vo R (Reset) v S (Set), c m t nh sau:

Tng hp R-S Flip flop

M t quan h gia bin ra Q (tip theo) vi cc bin vo S, R v bin ra Q (hin ti) Bin i biu thc v thc hin R-S flip flop bng cc cng logic c bn

Tn hiu ng b Flip flop

Cc Flip flop thng c hot kch nhn thng tin nh mt tn hiu ng b gi l clock Tn hiu clock c th tch cc:
theo mc (cao, thp) theo sn (ln, xung)
CLK 0 1 S x 0 0 1 1 R x 0 1 0 1 Q Q Q 0 1 x Q Q Q 1 0 x

Flip flop ch c th trao i thng tin khi tn hiu clock tch cc. Khi clock khng tch cc th Flip flop gi nguyn trng thi

Cc R-S Flip flop

Cc FF thng c ng b bng tn hiu clock Dng FF kiu MasterSlave m bo truyn tin cy

Flip Flop hot kch theo sn

J-K Flip flop

So snh J-K Flip flop vi RS Flip flop:

S = J.Q v R = K.Q

C th to J-K FF t mt RS FF theo s sau:

To J-K Flip flop

m bo truyn tn hiu tin cy, thng to J-K flip flop t R-S flip flop kiu Master-Slave Khi J-K flip flop c hot kch theo sn

D Flip flop v T Flip flop

Theo bng trng thi ca cc FF, c th to DFF v TFF t J-KFF nh sau:

DFF: TFF: D = J = K T=J=K

Phn bit flip-flop hot kch theo mc v hot kch theo sn

Tn hiu iu khin trc tip cc flip-flop

Mi flip-flop u c cc tn hiu:
Tn hiu vo, v d J, K Tn hiu ng b clock Tn hiu ra Q

Ngoi ra, nhiu flip-flop cn c thm cc tn hiu trc tip c tc dng iu khin cng bc trng thi ra ca flip-flop. l:
Clear (CLR), c tc dung iu khin Q = 0 Preset (PR), lm cho Q = 1

Quan h thi gian Flip Flop

Ca s thi gian ca Flip flop c xc nh bi:
tsu: thi gian chun b (Setup) tn hiu vo cn phi xc lp n nh mt khong thi gian tsu, trc khi c s kin clock th: thi gian duy tr (Hold) tn hiu vo cn phi duy tr n nh thm mt khong thi gian th, sau khi kt thc s kin clock

y l mt trong nhng yu t hn ch tn s ca mch logic dy

Kch thch cho cc flip flop

Khi thit k mch logic dy, ta cn phi xc nh iu kin kch thch cho cc flip-flop tu theo p ng cn c ca chng. Vi hai gi tr logic 0 v 1 cho mi bin, mi flip-flop c th c mt trong bn p ng l: S0, S1, T0, v T1 Bng di y m t cc iu kin kch thch cho cc loi flip-flop khc nhau
p ng
K hiu S0 T1 T0 S1 Q Q+ 0 0 0 1 1 0 1 1 S 0 1 0 x R x 0 1 0 J 0 1 x x

Kch thch
K x x 1 0 T 0 1 1 0 D 0 1 0 1

Thanh ghi (Storage Register)

Thanh ghi cha s liu (Data Storage Register) c to ra bng cch dng cc D flip-flop ni song song vi nhau C th dng thm cc buffer 3-trng thi to c ch c (Read) cho cc thanh ghi V d: 74273, 74373, 74374

Mt s vi mch thanh ghi

Thanh ghi dch (Shift Register)

Thanh ghi dch c dng :
Bin i m song song ni tip To tr cho cc dy tn hiu s

Phn t c bn ca thanh ghi dch l cc D flip flop ni chui ni tip vi nhau

Cc loi thanh ghi dch

Cc thanh ghi dch c phn chia thnh cc loi sau:
Vo ni tip ra ni tip (SISO), v d: 4006 (18 nhp), 4517 (64 nhp), 4557 (64 nhp), 4562 (128 nhp) Vo ni tip ra song song (SIPO), v d: 4015 (4 bit), 4094 (8 bit), 74164 (8 bit) Vo song song ra ni tip (PISO), v d: 4014, 4021, 74165, 74166... u l cc thanh ghi 8 bit Vo song song ra song song (PIPO), v d: 7495, 74195, 74395, 4035 (4 bit), 74323 (8 bit)... Thanh ghi dch vn nng c th dch theo hai chiu, v d 74194, 4194 (4 bit)

V d v cc thanh ghi dch

Thanh ghi dch PIPO

Thanh ghi dch vn nng

Hot ng ca thanh ghi dch

B m Khng ng b
m khng ng b (Ripple Counter): tn hiu clock cho cc flip flop khc nhau ly t cc ngun khc nhau, thng l t li ra Q ca flip flop tng trc Mi flip flop lt trng thi khi flip flop tng trc n chuyn t 1 sang 0
COUNT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

OUTPUTS QD
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

QC
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

QB
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

QA
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

B m ng b
m ng b (Synchronous Counter): tn hiu clock cho cc flip flop c ly t mt ngun chung, iu kin lt ca cc flip flop c xc nh bi mc logic li vo T Flip flop u tin (A) chuyn trng thi vi mi nhp clock, mi flip flop pha sau s chuyn trng thi nu khi c s kin clock tt c cc flip flop trc n u c mc logic 1

B m c s N

n 2

B m t trc gi tr

B m thun nghch

S dng b m
Vi cc b m thun nghch t trc c gi tr, ta c th to ra b m c chu k m t N1 n N2. Trong , N1 v N2 l cc gi tr nguyn bt k

Locked-out mch logic dy

IN T S
Chng 6

Phn tch, thit k mch logic dy

M hnh mch logic dy

C th coi m hnh tng qut nht ca mch logic dy gm: cc bin vo, cc bin ra v cc trng thi bn trong ca mch. C th s dng m hnh my trng thi (Finite State Machine FSM) phn tch v tng hp mch logic dy Ti mi nhp clock, mch logic t hp xc nh cc bin ra v trng thi tip theo thng qua cc bin vo v trng thi hin ti

Cc m hnh FSM
Hai m hnh FSM thng dng phn tch v tng hp mch logic dy l m hnh Moore v m hnh Mealy

Trnh t thit k mch logic dy

1. M t hot ng ca mch logic dy cn thit k (biu trng thi, biu thi gian, hoc cc thng tin thch hp khc) 2. Lp bng chuyn trng thi (state table) 3. Gn gi tr nh phn cho mi trng thi 4. Xc nh s flip-flop cn dng v gn cho mi flip-flop mt k hiu bng ch 5. La chn kiu flip-flop cn dng 6. T bng chuyn trng thi, xc nh kch thch cho mi flip-flop v biu thc ca mi bin ra 7. Lp s mch logic t cc phn t c bn

Biu trng thi

C th m t hot ng ca cc mch logic dy bng biu trng thi (state diagram):
Vng trn m t trng thi ca mch Mi tn trn c ghi gi tr ca tn hiu vo dng m t qu trnh chuyn trng thi

V d:

V d thit k: To xung n
Mch to ca ra mt xung n c rng c nh mi khi c xung bt k ca vo

S dng m hnh FSM Moore

Tng hp mch theo m hnh FSM Moore

S dng m hnh FSM Mealy

Tng hp mch theo m hnh FSM Mealy

V d thit k: B m
B m thun nghch 3 bit
M t b m v cc trng thi
Hin ti
A 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Vo (I)
U/D A 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1

Tip theo
B 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 C 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

V d thit k: B m
S Flip-Flop cn dng l 3 Gi s ta chn s dng JK Flip-Flop Khi , p ng ca cc Flip-Flop c m t nh sau:

Xc nh iu kin kch thch cho cc Flip-Flop

xc nh iu kin kch thch cho cc Flip-Flop tu theo p ng cn c ta s dng bng sau: Vi JK Flip-Flop, iu kin kch thch tng ng l:
S0: J = 0 v K = x T0: J = x v K = 1
p ng
K hiu S0 Q Q+ 0 0 S 0 R x J 0

S1: T1:
Kch thch
K x

J = x v K = 0 J = 1 v K = x

T 0

D 0

T1
T0 S1

0 1
1 0 1 1

1
0 x

0
1 0

1
x x

x
1 0

1
1 0

1
0 1

V d thit k: B m
Xc nh iu kin vo (J, K) cho cc Flip-Flop:

V d thit k: B m
Tng hp b m t cc JK Flip-Flop iu kin kch thch vo cho cc JK Flip-Flop tho mn cc biu thc logic trn

Kim tra hot ng ca b m

Cho I = 1, kim tra cc trng thi
Cho I = 0, tip tc kim tra cc trng thi

Thit k b m vi cc T Flip-Flop hoc D Flip-Flop

IN T S
Chng 8

Mch bin i tn hiu

Bin i tn hiu trong h thng

Trong cc h thng x l thng tin hin i, v d cc h thng o lng - iu khin cng nghip, vic p dng k thut x l tn hiu s ngy cng tr nn ph bin Tn hiu cn phi c biu din dng s ph hp vi tro lu ny

 ADC (Analog Digital Converter) bin i mt tn hiu vo analog thnh tn hiu ra digital DAC (Digital Analog Converter) bin i mt tn hiu vo digital thnh tn hiu ra analog Tn hiu digital ADC v DAC l m nh phn, cn tn hiu analog l in p hoc dng in

Chc nng ca ADC v DAC

c tnh ca ADC v DAC

c c tnh truyn t vo-ra l tng, b bin i cn phi c phn gii v cng ln. phn gii ca b bin i tn hiu c th hin thng qua s bit dng m ho tn hiu analog. Vi ADC/DAC s dng n bit, phn gii ca n l 2n. Tc l, tn hiu analog c th nhn mt trong 2n gi tr khc nhau. Mi mt gi tr ri rc c gi l mt mc lng t Mi mt gi tr m s tng ng vi mt khong gi tr ca tn hiu analog, ch khng phi ch mt gi tr c th. c tnh vo-ra thc t ca ADC/DAC c dng bc thang. S bc ca ng c tnh ny tu thuc vo s bit ca m s, n cho bit phn ly cng nh chnh xc ca ADC/DAC Khong gi tr ca mt mc lng t V = VFS/2n

V d v bin i ADC

V d: vi ADC 3-bit, c th c 8 t hp m khc nhau ca ra tng ng vi tm mc gi tr lng t ca tn hiu vo analog. Tronh v d ny, nu in p vo l 5.5V v in p chun so snh l 8V, th m nh phn li ra s l 101. Bc lng t trong trng hp ny l VREF/8 = 1V, ADC cng nhiu bit c bc lng t cng nh v do vy c kh nng phn ly v chnh xc cao hn.

Bc lng t ca ADC
Bc lng t ca ADC (bng ln ca 1 LSB) ph thuc vo s bit ca ADC v ln ca in p chun so snh VREF

Sai s lng t ca ADC

ln ca sai s lng t c th thay i t 0 n 1 LSB

Sai s tng i do vic lng t ho l 1/2n, trong n l s bit ca b bin i

Gim sai s lng t

C th gim ln ca sai s lng t bng cch cng thm mt lng offset bng LSB khi bin i

Cc sai s khc
Sai s offset (sai lch zero, cng tnh) Sai s khuch i (nhn tnh) Sai s tuyn tnh (tnh phi tuyn) ca c tnh truyn t

Bin i DAC
DAC bin i m nh phn li vo thnh tn hiu analog ca ra VOUT = NVREF/2m , m l s bit ca m nh phn li vo Cc phng php bin i
Mch phn p Li in tr c trng s Li in tr R-2R

DAC dng mch phn p

in p chun so snh VREF c chia thnh 2n mc nh b phn p gm 2n in tr. Tu theo gi tr ca m nh phn li vo m c mt mc in p tng ng c chn a ti ca ra (VOUT = NVREF/2n). Tr khng vo ca mch m (Op-Amp) cn phi rt ln. c im:
S dng rt nhiu in tr v switch (2n) Sai s do offset ca Op-Amp Tr do c nhiu switch ni tip

DAC dng in tr c trng s

in p ra VOUT:

Bit cao nht (MSB): Bit tip theo: Bit thp nht (LSB):

VOUT = - VREF/2n (bn-12n-1 + bn-22n-2 ++ b020) = - NVREF/2n c im:

S dng t in tr (n in tr cho DAC n bit) Tr s cc in tr rt khc nhau

VOUT(bn-1) = -VREF/2 bn-1 VOUT(bn-2) = -VREF/4 bn-2 VOUT(b0) = -VREF/2n b0

DAC dng li in tr R-2R

in p sau mi mt li in tr gim cn in p ra ca ton mch: VOUT = - VREF/2n (bn-12n-1 + bn-22n-2 ++ b020) = - NVREF/2n c im:
S in tr s dng khng nhiu (2n in tr cho DAC n bit) Tr s cc in tr gn nhau R v 2R

c im chung ca DAC
Tc : thi gian thc hin php bin i DAC rt ngn, ph thuc thi gian truyn ca cc phn t mch chnh xc: th hin qua s bit m nh phn C tn hiu LE khi cn ghp ni vi BUS Yu cu i vi mch khuch i OpAmp:
in p sai lch ca vo VIO phi nh Dng phn cc li vo IB phi nh Di in p ra ca OpAmp phi ln hn hoc bng di thay i n y thang ca in p ra DAC Tc (di thng, Slew Rate) ca OpAmp phi ln m bo tc bin i ca DAC

D/A Dynamic conversion parameters

Conversion time Latency time Settling time Hysteresis Glitches

Bin i ADC
ADC bin i tn hiu analog li vo thnh m nh phn ca ra N = VIN2m/VREF, m l s bit ca m nh phn li vo Cc phng php bin i:
Bin i trc tip (Flash ADC) SAR (Xp x dn) Tch phn v m xung

Flash ADC
S dng 2n in tr v 2n comparator bin i Tn hiu ra t cc comparator c m ho bng mt Priority ENCODER c im:
Tc cao Mch phc tp gm qu nhiu phn t

ADC bin i xp x dn

u tin SAR a ra N=1000 v VDAC=VREF/2 Qu trnh tip din theo cch n khi ht n bit c im:
Mch khng phc tp lm Tc va phi (n ln so snh cho n bit) Nu VDAC<VIN N=1100 v VDAC=VREF3/4 Nu VDACVIN N=0100 v VDAC=VREF1/4

ADC tch phn

Trn y l mt kiu ADC tch phn (tch phn hai sn dc dual slope)
in p vo VIN c tch phn trong thi gian Tn c nh. Sau thi gian ny VC= VIN Tn = VIN 2n.Tclock in p VREF c tch phn trong thi gian Tp. Sau thi gian ny t phng ht. Do vy, Tp = VIN 2n.Tclock /VREF S m c trong thi gian ny l N= Tp /Tclock = 2n VIN/VREF Mch n gin Tc rt thp (c 2 2n.Tclock cho mt php bin i n bit)

c im:

c im chung ca ADC
chnh xc
Ph thuc vo cc phn t mch Th hin qua s bit

Tc
ADC cn qua trnh so snh nn thng chm hn nhiu so vi DAC

Cc tn hiu
Khi ng ADC: START Bo kt thc php bin i: EOC iu khin ba trng thi khi ghp ni vi BUS: OE

IN T S
Chng 7

B nh bn dn

Phn loi v nh gi

Cc ch tiu nh gi: 1. Mt (s bits/m2) v Dung lng (tng s bit) 2. Tc (thi gian c/vit) 3. Cng sut tiu th

Cc tn hiu ca b nh

Address: Xc nh a ch ca nh cn trao i Data: Ni dung thng tin cn trao i vi nh c chn Chip Enable: Cho php (chn) chip nh Write Enable: Cho php vit vo nh c chn Output Enable (Read): c ni dung nh c chn

Tc ca b nh
Tc hot ng ca b nh c nh gi thng qua thi gian truy nhp (access time), bao gm:
Read access Write access

T chc b nh

T chc b nh

Xc nh khi nh c chn

c/vit b nh
Cc bit a ch chia lm hai nhm (hng v ct) Cc chn data c th trao i hai chiu Cc tn hiu Chip Enable, Write Enable v Output Enable iu khin vic trao i d liu

Phn t nh
Phn t nh l n v lu gi thng tin c bn trong cc chip nh Cc tn gi:
Memory Cell Storage Cell Bit Cell

Word Line: ng chn nh c gii m t cc bit a ch Bit Line: ni dung thng tin trao i ca tng bit trong mi nh

B nh ch c - ROM
B nh ROM (Read Only Memory): ni dung khng thay i ngay c khi ct ngun cung cp. B nh ROM gm cc loi sau:
MROM (Mask ROM): ni dung c np trong qu trnh ch to PROM (Programmable ROM): ni dung c vit mt ln, s dng cu ch EPROM (Erasable PROM): ni dung c th vit/xo c nhiu ln, s dng tia cc tm EEPROM (Electrically EPROM): vit/xo nhiu ln. Xo bng in. Flash ROM: EEPROM nhng c tc c/vit v mt ln hn nhiu

Phn t nh ROM
B nh ROM s dng Diode hoc Transistor (BJT/MOS) lm n v nh c bn C cc kiu phn t nh:

Cu ni (E)EPROM

Phn t nh PROM, EPROM, v EEPROM

B nh MOS ROM 1

B nh MOS ROM 2

B nh c/vit - RAM
B nh RAM (Read - Write Memorie) gm: STATIC RAM (SRAM)
D liu c lu gi vnh vin mt khi cn c ngun cung cp duy tr Kch thc ln (6 transistors/cell) Tc cao Cu trc vi sai (Differential)

DYNAMIC RAM (DRAM)

Cn c chu k lm ti ni dung phn t nh Kch thc nh (1-3 transistors/cell) Tc thp Cu trc n (Single Ended)

Phn t nh SRAM
Phn t nh SRAM dng ti in tr
Tiu th cng sut trng thi tnh, cn RL ln

Phn t nh SRAM
Phn t nh RAM tnh dng 6 transistor:

Qu trnh vit SRAM

Qu trnh c SRAM

Phn t nh DRAM 3 transistor

Write: Gi tr bit t BL1 c np ln t CS Read: Ni dung nh t t CS c a ln BL2

Phn t nh DRAM 1 transistor

Write: CS c np bi WL v BL. Read: Phn b li in tch gia t cha CS v t in ng dy bit CBL

So snh cc b nh
Kiu b nh (M)ROM PROM EPROM EEPROM FLASH SRAM DRAM S ln vit/xo 0 1 1000 10.000 1.000.000 100.000 Thi gian vit - 100 ms 100 s 50 ms 3 10 ms 10 s 10 ns 100 ns Kch thc 100 m2 -200 m2 400 m2 200 m2 10001700 m2 200500 m2

S dng b nh

IN T S
Chng 9

Mch to xung

Xung v cc tnh cht c bn

Xung in: tn hiu in c thi gian tn ti xc lp ngn (c thi gian qu ca mch) Cc c trng c bn ca tn hiu xung
Digital:
Mc (cao, thp) Sn (ln, xung)

Analog:
Bin rng Chu k lp y (Duty Cycle)

Mch to xung
Cc xung in c to ra t nhng mch in t c hai trng thi xc lp ng vi hai mc cao (H) v thp (L) ca in p ra Cc mch in t nh vy c th c chia thnh cc nhm nh sau:
Mch t dao ng, c hai trng thi u khng n nh (Astable). Mch t chuyn t trng thi ny sang trng thi khc. Mch i, c mt trng thi n nh (Monostable). Khi c kch thch mch chuyn sang trng thi khng n nh sau t ng tr v trng thi n nh ban u. Vi mt xung kch thch ca vo mch to mt xung n ca ra (One-shot). Mch trigger, c hai trng thi u n nh (Bistable). Mch c th chuyn t trng thi ny sang trng thi khc tu thuc vo tn hiu kch thch t bn ngoi. Loi mch ny cn c gi l mch Flip-Flop

To xung bng cng NOT

Khi u VC=0V, VOUT=VOH5V Qu trnh np t C: VC(t) = A+Be-t/RC Qu trnh phng t C:

A=VOL, B = VT+ - VOL Kt thc t2, vi: A = VOH, B = VT- - VOH Kt thc t1, vi: VOH+(VT- - VOH)e-t1/RC = VT+

VC(t) = A+Be-t/RC

VOL+(VT+ - VOL)e-t2/RC = VT-

Mch One-shot dng cng NOT

Trng thi n nh: VOUT = VOL Khi c kch thch vo: VC = VOL, VOUT = VOH Sau : VC = A + Be-t/RC
Vi A = VCC, B = VOL - VCC

Kt thc tx, vi VCC + (VOL - VCC)e-tx/RC = VT+

To xung nh hiu ng tr

Vi mch logic to xung 74xx123

Vi mch TIMER 555

Mch nh thi chnh xc:

Thi gian xung, tn s xung c iu chnh bng in tr/t in mch ngoi.

Cung cp t ngun DC 5V15V, khi ngun cung cp l 5V th mc in p ra tng thch TTL Mch c th sink/source dng in c 200mA

One-shot dng 555

in p chn 2 c duy tr mc V2>VCC/3 Mch n nh trng thi c VOUT = 0V Khi c kch thch lm cho V2<VCC/3 th mch chuyn sang trng thi khng n nh vi VOUT = VCC Mch t tr v trng thi n nh sau khong thi gian tx=1,1RC

One-shot dng 555

VC = VCC(1 e-t/RC) Ti tx: VCC(1 e-tx/RC) = VCC2/3 e-tx/RC = 1/3 tx = RCln3 = 1,1RC

Mch t dao ng dng 555

Trng thi VOUT=0V, t C c np vi hng s thi gian Tn=(RA+RB)C, n mc VC=VCC2/3 Mch chuyn sang trng thi VOUT=VCC, t C phng vi hng s thi gian Tp=RBC, n mc VC=VCC1/3 th tr v trng thi trc Tn s dao ng: f=1,44/[(RA+2RB)C]

Mch t dao ng dng 555

VOUT = VCC:

VC = A + Be-t/Tn = VCC e-t/TnVCC2/3

Vi A = VC() = VCC, B = VCC/3 VCC = VCC2/3 VCC2/3 = VCC - e-t1/TnVCC2/3 t1 = Tnln2 0,695(RA+RB)C

VOUT = 0V:

VC = A + Be-t/Tp =e-t/TpVCC2/3

Vi A = VC() = 0V, B = VCC2/3 VCC/3 = e-t2/TpVCC2/3 t2 = Tpln2 0,695RBC

Mch iu ch rng xung PWM Pulse Width Modulation

in p iu ch c a ti chn 5 ca timer Xung nhp (carrier) c tn s f a ti chn 2 (trigger) rng ca xung to ra ph thuc vo in p iu ch

Phase Locked Loop - PLL

S dng ca PLL

Tn s ca tn hiu ra: fO = f S

Tng hp tn s