EE3353 Assignment #1

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EE3353: ASIC Design & FPGA
Assignment # 1
(Due-Date: March 18
th
, 2014, Due in Class)

NOTE: This is an individual assignment. You have to submit it in handwriting. No
Computer print outs will be accepted. No Late Submission is allowed!!

Q # 1.
(a). Draw the Circuit Schematic of a 4 to 16 decoder using 2 to 4 decoders . If this 4 to 16
decoder is part of a ROM , how many memory locations ROM will have ? (10-Points)
(b). Draw the Circuit Schematic of an 8 to 1 MUX using only 2 to 1 MUXs .
(10-Points)
Q # 2. If Q2 , Q1 and Q0 are the outputs of a 3-bit binary counter ? Draw the timing diagram
of clock and counter bits Q
2
, Q
1
, Q
0
(15-Points)

(a) If counter changes its state on posedge clock
(b) If counter changes its state on negedge clock

Q # 3. (30-Points)
(a). Write Verilog Module for 4 to 1 MUX in Gate Level Modeling ?
(b). Write Verilog Module for 4 to 1 MUX in Data Flow Modeling ?
(c ). Write Verilog Module for an 8 to 1 MUX which instantiates multiple instances of 4 to 1
MUX module
EE3353 Assignment #1
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Figure 1. 4 to 1 MUX
Q # 4. (30-Points)
(a). Write Verilog Module for 2 to 4 Decoder with enable in Gate Level Modeling ?
(b). Write Verilog Module for 2 to 4 Decoder with enable in Data Flow Modeling ?
(c ). Write Verilog Module for Stimulus that will instantiate and test 2 to 4 decoder module?

Figure 2. 2 to 4 Decoder with Enable

Q # 5. (20 Points)
(a). Write Verilog module in Behavioral Modeling for a 4-bit binary counter. Counter works on
pos-edge of clock and reset signal is an active low reset signal.
(b). Write Stimulus module for testing 4-bit binary counter which gives Clock and Reset signals
to Counter module and also displays inputs and outputs of binary counter using $monitor.