MMA7455L

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3.1.1 Cm bin accelerometer MMA7455L:
Gii thiu:
MMA7455 l cm bin o gia tc 3 trc X, Y, Z, l sn phm ca hng Freescale, ng ra
Digital, cng sut thp, c nhng c trng c bn sau:
- Ng ra Digital (I2C/SPI) 10-bit Mode 8g (g l gia tc trng trng)
- Kch thc: 3mm x 5mm x 1mm, ng gi 14 chn LGA
- Dng tiu th thp 400A
- Chc nng Self Test trc Z
- in p vn hnh thp 2.4V 3.6V
- S dng cc thanh ghi User Assigned chnh Offset
- Lp trnh gi tr ngng cho php ngt
- Pht hin chuyn ng: Shock, dao ng, ri.
- Pht hin xung: xung n v xung kp
- nhy: 64 LSB/g @ 2g v @ 8g 10-Bit Mode
- C th chn tm o (2g, 4g, 8g)
- Chu shock ti 10000g

Hnh 3.1.1: Hnh dng MMA7455

3.1 Cm bin
accelerometer
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ng dng ph bin:
- Cell Phone/PMP/PDA: Image Stability, Text Scroll, Motion Dialing, E-Compass, Tap
to Mute
- HDD: pht hin trng thi ri t do (Freefall Detection)
- Laptop PC: pht hin ri hay b ly cp (Freefall Detection, Anti-Theft)
- B chnh nghing cho la bn in t (E-Compass Tilt Compensation)
- 3D Gaming: Cm bin o nghing v chuyn ng (Tilt and Motion Sensing), Ghi s
kin (Event Recorder)

M t cc chn:

#1: DVdd_IO, cp ngun digital cho cc chn I/O.
#2: GND, ni ground.
#3: NC, khng dng, h hoc ni t.
#4:IADDR0, Bit 0 ca a ch I2C.
#5: GND, ni t.
#6: AVdd, ngun Analog.
#7: CS, Chip Select, chn kiu truyn thng: mc 0 cho SPI, mc 1 cho I2C.
#8: INT1/DRDY, ngt 1 v bo Data Ready.
#9: INT2, Ngt 2.
#10: NC, khng dng, h hoc ni t.
#11: Reserved, d tr, ni t.
#12: SDO, d liu ra trong truyn thng ni tip kiu SPI.
#13: SDA/SDI/SDO, d liu truyn thng ni tip kiu I2C (SDA) / d liu vo ca truyn
thng SPI (SDI) / d liu ra ca truyn thng ni tip kiu 3-wire.
#14: SCL/SPC, xung clock ca truyn thng ni tip I2C (SCL) hay SPI (SPC).

Bng 3.1.1: M t chc nng cc chn MMA7455

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S khi:

Hnh 3.1.2: S khi dng n gin ca accelerometer

Thng s hot ng:
Bng 3.1.2: Cc gi tr ti a cho php

- Ngun Analog: AV
DD
2.4 V - 3.6 V (tiu chun 2.8V)
- Ngun digital: DV
DD_IO
1.71 V AV
DD
(tiu chun 1.8 V)
- Dng tiu th: I
DD
khong 400A, ti a 490A. ch Stand by I
DD
khong 10A.
- Tm o gia tc trn c 3 trc X, Y, Z: c 3 mode 2, 4, 8
- Nhit lm vic: -40 80 C
- in p ng vo mc cao: 0.7 x V
DD
, mc thp: 0.35 x V
DD


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Nguyn l hot ng:
MMA7455 l mt cm bin vi c b mt (surface-micromachined integrated-circuit
accelerometer) thuc loi in dung.
Di tc dng ca gia tc, khong cch gia cc vch ngn thay i, s thay i ny dn
n s thay i gi tr in dung theo cng thc quen thuc:

Vi A l din tch cc ming ngn, l hng s in mi, D l khong cch gia cc tm.

Gi tr in p ng ra t l vi gia tc o c.
T gi tr gia tc, ta c th tch phn n c gi tr vn tc hay tch phn 2 lp xc nh
v tr ca vt th.
Gia tc tnh do lc hp dn c th c dng xc nh gc v nghing.

3.1.2 Phng php calibrate cho cm bin accelerometer:
im offset ca accelerometer b tri do nh hng ca nhit , s lo ho v cc bin
ng trong mi trng lm vic. S tri offset ny nh hng ln n cc ng dng, c th
nht l trong xc nh gc nghing (tilt), sai s do sai offset c th ln ti 12 khi c c
trn mt phng nhn iu ny l khng th chp nhn c.
Do ta lun phi tin hnh calibrate cho accelerometer trc khi a vo s dng, tc l
tm cc gi tr hiu chnh tnh ton c gi tr o chnh xc.
Cc gi tr cn xc nh l gi tr 0g zero g, v nhy sensitivity thc t.

Cc phng php xc nh gi tr zero g c ngh nh sau:
1. Manual 0g X, Y, Z Full Range Calibration: Quay accelerometer t v tr +1g ti -1g, ghi
nhn gi tr nh nht v ln nht. Do tnh i xng, im 0g s nm chnh gia khong
ny.
Tin hnh vi c 3 trc X,Y,Z c gi tr offset cho mi trc.
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2. Simple 0g X, Y, Z calibration: Cho rng khi accelero nm trn mt phng, ta c gi tr
trn trc X, Y ti l 0g, quay accelerometer 90 ti v tr 0g ca trc Z (trc Z nm song
song vi mt phng), ghi nhn gi tr zero ca trc Z.
Phng php ny n gin nhng khng c chnh xc cao nh phng php 1.

3. Freefall Calibration: Cho cm bin ri t do. Thun li ca phng php ny l ta c
th c c gi tr 0g ca 3 trc cng mt lc. Tuy nhin khi cn calibrate li, khng phi
lc no cng d dng cho thit b ri t do c.

4. Simple 0g X, 0g Y, +1g Z calibration: t cm bin trn mt mt phng nhn, c gi tr
0g ca cc trc X, Y ti y v +1g ca trc Z. Gi tr +1g Z tr i nhy bit trc, ta c
0g Z. Vi phng php ny c th gi tr 0g X, Y l kh chnh xc (vi mt gn nh phng
hon ton), nhng gi tr 0g Z th khng c m bo v n khng c c ti ng v tr
0g. Thun li ca phng php ny l khng cn phi dch chuyn hay xoay thit b, ph hp
vi trng hp calib li sau mt thi gian hot ng m accelerometer c gn cng
trn thit b.

Ngoi ra, vi cc dng c, thit b th nghim chnh xc nh my to xung, dao ng k,
ta c cc phng php calibrate hiu qu hn.

c gi tr sau khi c calibrate:
- Xc nh khong di offset CZ
OFF
ca mi trc
- c gi tr o c CA
- Gia tc thc:

Vi S l nhy.
Nu s dng phng php Simple 0g X, 0g Y, +1g Z calibration th gia tc thc c tnh
nh sau:

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Gii thut calibrate t-chnh-zero c m t bng s khi nh sau, trong chng
trnh c d liu t accelerometer s chy bnh thng cho n khi nhn c lnh chnh
zero:

Tnh gi tr gia
tc thc A
MEA
Gi tr offset
hin ti, CZ
OFF
Gi tr gia tc
c v CA
Calib li?
Start
End
YES NO

Hnh 3.1.3: Lu gii thut t-chnh-zero cho accelerometer

Cm bin accelerometer MMA7455L, c 6 thanh ghi dng cha gi tr offset, sau khi
xc nh c cc gi tr offset ca mi trc ta lu chng vo cc thanh ghi ny v gi tr
c c ra t cc thanh ghi d liu l gi tr c hiu chnh.
Cn lu rng, gi tr c lu vo 6 thanh ghi ny l gi tr offset tnh c nhn vi 2.
Mi trc X, Y, Z c 2 thanh ghi cha gi tr offset, ng vi High byte v Low byte. Nu dng
mode 8-bit th ta ch cn quan tm ti thanh ghi Low Byte.
V d, ta tnh c offset ca trc X l -12, nh vy cn phi ghi gi tr -24 vo thanh ghi
XOFFL ( a ch $10).

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p dng cho accelerometer MMA7455L, chng hn v tr chn chnh offset l 0g X, 0g
Y, +1g Z, sau khi nhn c lnh chnh offset, gii thut chnh offset s c dng nh sau:

Tnh offset: Xoffset = X avg - 0,
Yoffset = Yavg - 0, and Zoffset = Zavg - 63
Gi thit b v tr X = 0g, Y =
0g, Z = 1g.
Ly mu nhiu gi tr (vd: 64 gi tr),
tnh tr trung bnh Xavg, Yavg, Zavg
Start
Tnh di ghi vo thanh ghi:
Xshift = -2 * X0g,
Yshift = -2 * Y0g,
Zshift = -2 * (Z1g - 63).
Ghi gi tr di vo cc thanh ghi
OFFSET tng ng

Hnh 3.1.4: Lu gii thut chnh offset cho MMA7455L
Trong s 63 l gi tr chun ca gia tc = 1g, cng chnh l nhy.

Code mu:
1.Simple 0g X, 0g Y, +1g Z calibration
S = Sensitivity;
X0g_current = XCZOFF;
Y0g_current = YCZOFF;
Z1g_current = ZCZOFF;
XCA = XCA_val;
YCA = YCA_val;
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ZCA = ZCA_val;
AmeasX = (XCA-X0g_current)/S;
AmeasY = (YCA-Y0g_current)/S;
AmeasZ = (ZCA-(Z1g_current-S))/S;

2.Cc phng php c 0g khc:
S = Sensitivity;
X0g_current = XCZOFF;
Y0g_current = YCZOFF;
Z0g_current = ZCZOFF;
XCA = XCA_val;
YCA = YCA_val;
ZCA = ZCA_val;
AmeasX = (XCA-X0g_current)/S;
AmeasY = (YCA-Y0g_current)/S;
AmeasZ = (ZCA-Z0g_current)/S;

Xc nh li nhy:
nhy danh nh c quy nh bi nh sn xut, tuy nhin do nh hng ca iu kin
mi trng, tui th v cc yu t khc, khi accelerometer hot ng, nhy thc t c th
thay i. xc nh li nhy lm vic ca acclerelometer, ta tnh nh sau:

2
/
Gi tr nhy c ngha ln trong nhng tnh ton v sau, chng hn nh tnh gc
nghing tilt trn 3 trc.

3.1.3 Xc nh gc nghing Tilt bng gi tr gia tc trn 1 trc:
Xc nh gc tilt l mt trong nhng ng dng ph bin ca accelerometer, gc nghing
c xc nh da vo gi tr gia tc tnh.
Ta bit, gia tc trng trng g lun khng i. Khi cm bin accelerometer thc hin
chuyn ng quay, h trc xyz gn lin vi n cng quay theo, vi mi v tr khc nhau ca
accelerometer trong khng gian, hnh chiu ca gia tc trng trng g ln h trc xyz s
cho ra nhng gi tr khc nhau ph thuc vo gc hp bi phng ngang v phng ca mi
trc.
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Tilt chnh l gc nghing ca mi trc x,y,z so vi mt phng ngang. Ta gi trc nm
ngang l (), vi chiu dng ca gc nghing (tilt) l chiu kim ng h (chiu hng v
gia tc trng trng g).
Ta c:

Gi tr gia tc tnh c c t cc ng ra ca accelerometer chnh l hnh chiu ca ln
mi trc tng ng. Nh vy ta s xc nh c:

arcsin

arcsin

arcsin

Vi nm trong khong -90 +90.
H trc to gn vi accelerometer MMA7455L c quy nh nh sau:











Hnh 3.1.5: H trc to xyz trn MMA7455L

()

+
X



Top
Bottom
Z
Y
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Cc p ng ng ra ti 6 v tr c bit ca acclero nh sau (mode 2g):


Hnh 3.1.6: Cc p ng ng ra ti 6 v tr c bit ca MMA7455L ti mode 2g

Ng ra ca cc loi accelerometer l tuyn tnh, k c dng analog hay digital, vi
MMA7455L nhy danh nh mode 2g l 64 count/g, 4g l 32 count/g, 8g l 16
count/g mode 8-bit d liu, 64 count/g mode 10-bit.
Khi lm vic, di tc ng ca mi trng v do s lo ho ca cm bin, nhy s l
mt gi tr khc vi gi tr danh nh ny.
Khi calibrate cho cm bin, ta ng thi cng cn xc nh li nhy ca n.

2
/





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Bng sau cho bit gi tr gia tc tng ng vi ng ra:
Bng 3.1.3: Acceleration vs. Output (8-bit data)


Vy ta thy, bit c trng s ln nht (MSB) l bit du, MSB = 1 vi cc gi tr gia tc m,
v MSB = 0 cho cc gi tr dng.
T y ta c gii thut xc nh gc nghing Tilt:
Vi S l nhy.










Hnh 3.1.7: Gii thut xc nh gc nghing Tilt bng 1 trc

0
NO

YES
0

MSB=0

256

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Nhn xt:
y chnh l phng php xc nh gc nghing da vo gi tr gia tc tnh o c trn
mt trc. Phng php ny p dng cho cc loi cm bin accelerometer 1 trc to , hoc
trong trng hp accelerometer c gn vo thit b m ta khng th da thm kt qu o
trn cc trc khc xc nh gc nghing, chng hn nh trng hp sau:

Hnh 3.1.8: Accelerometer 2 trc to , trong ch c 1 trc X c kh nng quay

Gi tr gc Tilt tnh theo phng php ny cng chnh xc khi cng gn 0, v sai s rt ln
khi cng gn 90.

Hnh 3.1.9: Gi tr gc nghing tnh theo hm arcsin ca gia tc
Theo th trn, ta thy, khi gi tr gc ln cn 0, dc p ng nh hn nhiu so vi
khi gc theta tin ti 90. Chnh v dc ln vng gn 90 lm gi tr gc nghing c
vng ny thiu chnh xc.
Gi s nhy l 63 count/g. Vi gi tr gia tc c vo c l 0x01 v 0x02, tng ng
l 1 v 2 trong h thp phn, ta tnh xem gc nghing chnh lch bao nhiu.
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1
1
63
0.9
2
2
63
1.8
Trong khi , vi cc gi tr gia tc rt gn vi 1g (tc l gi tr output gn vi 64 hay
0x40) th chnh lch li rt ln.
63
63
63
90
62
62
63
79
Nh vy phn gii ln nht cho mi LSB c th ln hn 10 (!!!).
t chnh xc chp nhn c, phng php ny khuyn co ch nn dng khi o di
gc t -45 n +45.
Mt bt li na ca cch o ny l, do tnh gc tilt bng hm arcsin nn khng phn bit
c 2 gc b nhau, chng hn nh 30 v 150, kt qu lun tr v 30.

Khi cn phi o gc ngoi phm vi -45 n +45 v c cm bin accelerometer loi 2 hay
3 trc to , hn na li khng b gii hn v kh nng quay ca thit b, phng php sau
c ngh dng:
3.1.4 Xc nh gc nghing tilt bng gi tr gia tc 2 hay 3 trc:
Cng vi loi cm bin gia tc 2 trc to nh hnh 3.2.8 nhng c lp t theo
chiu dc, nh vy c 2 trc X,Y u c kh nng quay:

Hnh 3.1.10: Accelerometer 2 trc to quay c

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Phn tch gia tc tnh ln 2 trc to X, Y nh sau:

Hnh 3.1.11:

Ta c:
A

sin
A

cos
T y, thit lp cng thc tnh gc nghing :
arctan
A

Tnh gc nghing da vo 2 trc to dng hm acrtan c chnh xc cao hn phng
php dng hm arcsin rt nhiu. Trc ht ta kho st p ng ca gc nghing theta vi hm
arctan:

Hnh 3.1.12: Gi tr gc nghing tnh theo hm arctan

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dc khi theta tin cng gn 90 cng gim, do gi tr gc nghing c c cng
chnh xc. Vi cch tnh ny phn gii ln nht khng vt qu 1.5.
So snh phn gii ca 2 phng php tnh gc nghing: dng 1 trc v 2 trc to
bng th sau thy r phng php th 2 hiu qu nh th no:

Hnh 3.1.13: S thay i phn gii gc nghing theo gi tr ng ra
phn gii ca phng php dng 2 trc to o gc nghing ch dao ng trong
khong 0-1.5 cho mi gi tr thay i ca ng ra, tt hn nhiu ln so vi phng php o
gc nghing ch dng mt trc to .
Trong phn gii ln nht (tc l kt qu o km chnh xc nht) nm trong tm o
gc 35-55, nhng ch sai lch khong 1.5.

Dng c 3 trc to X, Y, Z xc nh gc nghing:
Accelerometer 3 trc to c th dng xc nh gc nh hng ca vt th trong
khng gian 3 chiu.
1 trc
2 trc
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Hnh 3.1.14: Cc gc pitch, roll v theta
nh ngha Pitch (), Roll (), Theta () ln lt l gc hp bi trc X, Y, Z vi mt t,
cc gc ny c tnh t gi tr gia tc trn 3 trc nh sau:
arctan
A

arctan
A

arctan
A

3.1.5 Lp trnh truyn thng SPI vi MMA7455L:
MMA7455 c th thc hin giao tip theo c 2 chun SPI v I2C. Vic chn chun
truyn thng c thc hin bng vic thit lp gi tr cho chn CS (pin 7). Khi CS mc
thp (0) SPI c chn, v khi CS mc cao (1) MMA7455 thc hin giao tip ni tip theo
chun I2C (ng thi SPI b cm).
Cn lu nu ta chn CS mc 0 cho giao tip SPI th cn phi cm I2C bng cch set bit
I2CDIS trong thanh ghi I2C Device Address.
Cn nu khng kt ni chn CS vi mass th ta c th dng MCU iu khin vic
chn SPI mode.
Trong giao tip SPI hay I2C, MMA7455L ch c th ng vai tr Slave, thng thng
Master l mt vi iu khin (MCU).
Trong ti ny, ta dng vi iu khin AVR Atmega16 lm Master thu thp d liu t
MMA7455L.

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3.1.4.1 S lc v chun truyn thng SPI:
SPI (Serial Peripheral Interface) c t tn bi Motorola, l 1 chun truyn thng ni
tip s dng 4 dy tn hiu nn cn c gi l bus ni tip 4-wire. SPI hot ng ch
song cng (full duplex mode) tc l c th truyn v nhn ng thi trn ng truyn.

Hnh 3.1.15: SPI bus vi 1 Master v 1 Slave
4 dy tn hiu l:
SCLK Serial Clock (output from master)
MOSI/SIMO Master Output, Slave Input (output from master)
MISO/SOMI Master Input, Slave Output (output from slave)
SS Slave Select (tch cc thp, output from master)
Cc tn gi khc:
SCK, CLK, SPC Serial Clock (output from master)
SDI, DI, SI Serial Data In, Data In, Serial In
SDO, DO, SO Serial Data Out, Data Out, Serial Out
nCS, CS, nSS, STE Chip Select, Slave Transmit Enable.
Qu trnh truyn nhn d liu thng qua SPI bus:
Chn CS c iu khin bi Master, c li v mc 0 bt u v mc 1 kt
thc mt phin truyn d liu.
SPC (SCK) l tn hiu clock c iu khin bi Master.
Lnh c v ghi d liu vo cc thanh ghi ca Slave hon thnh trong 16 chu k xung
Clock nu c/ghi 1 byte, hoc nhiu hn nhng l 1 bi s ca 8 trong trng hp c/ghi
nhiu byte.
Khung truyn ca lnh c d liu bao gm 1 bit Read/Write (mc cao c), 6 bits a
ch v 1 bit Dont care.
Cc bit d liu s c gi v trn dy SDO (hay MISO).
Khung truyn ca lnh ghi cng gm 1 bit Read/Write (mc thp ghi), 6 bits a ch v
1 bit Dont care. Theo sau l 8-bit d liu.
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Hnh 3.1.16 Biu thi gian qu trnh c thanh ghi 8-bit (Mode 4 wire)

3.1.4.2 Kt ni SPI MMA7455L vi MCU:

Hnh 3.1.17 S kt ni MMA7455L vi MCU