Tutorial 6 KE26403

1. Sketch 3-input CMOS NAND and NOR gates.

2. Sketch 4-input CMOS NAND and NOR gates.
3. Sketch a complementary CMOS gate computing D C B A Y ) ( .
4. Sketch a transistor-level schematic for a single-stage CMOS logic gate for each of the
following functions:
a. D ABC Y
b. D C AB Y ) (
c. ) ( B A C AB Y
5. Sketch a transistor-level circuit for the following CMOS gates. Use a minimum number of
transistors.
a. A 3-input OR-AND-INVERT gate
b. A 3-input AND-OR gate
6. Implement the following three-input gates using only pseudo-nMOS logic gates. Your gates
receive three inputs, A, B, and C. Use a minimum number of transistors.
a. 3-input NOR gate
b. 3-input NAND gate
c. 3-input AND gate
7. Write a truth table for the function performed by the gate in figure below. The truth table
should have two inputs, A and B. What is the name of this function?


A
A
A
B
B
B
A
B
Y