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Bi tp
Bi 1:
Thanh ghi biu din s thc di dng chun IEEE FP 754 (single precision) nh sau:
1 1000 0101 10111000100000000000000
Xc nh gi tr s thc.
Bi 2:
Xem xt mt chng trnh chy trn mt b x l MIPS. Ngi ta thng k c kt
qu ca chng trnh ny nh bng sau:
Loi lnh T l thc thi
Load (lw) 15%
Store (sw) 10%
Cc lnh s hc R-Format (ALU) 45%
Lnh r nhnh (beq) 30%
Gi s thi gian thc thi ca cc khi chc nng nh sau:
Memory (c v ghi): 150ps
Register File (c v ghi): 30ps
ALU v cc b cng: 40ps
B qua thi gian thc thi i vi cc khi chc nng cn li
Kin trc ca b x l MIPS c thit k tin ha qua cc phin bn sau:
Kin trc A: b x l MIPS c thit k theo kin trc single-cycle (mi lnh c
thc hin trong mt chu k n), single-clock (xung nhp dng chung cho tt c cc
lnh).
Kin trc B: b x l MIPS c thit k theo kin trc single-cycle (mi lnh c
thc hin trong mt chu k n), multi-clock (xung nhp c th thay i cho tng lnh).
Kin trc C: b x l MIPS c thit k theo kin trc multi-cycle (cc lnh c
thc hin trong nhiu chu k), single clock (xung nhp dng chung cho tt c cc lnh).
Kin trc D: b x l MIPS c thit k theo kin trc multi-cycle (cc lnh c
thc hin trong nhiu chu k), single clock (xung nhp dng chung cho tt c cc lnh).
Cc lnh c thc hin theo k thut pipeline (Gi s chng trnh trn khi thc thi
pipeline khng gy ra stall hoc harzards).
a) Xc nh tc xung nhp (clock rate) ti a c th cp cho b x l MIPS theo kin
trc A.
b) Xc nh speedup gia cc kin trc A v B, C v D.
Bi 3:
Xt b x l thc hin lnh theo pipeline 5 giai on.
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a) Xc nh tt c ph thuc d liu (data dependency) trong on chng trnh sau.
Ph thuc no trong cc ph thuc trn c th c gii quyt bng k thut
forwarding?
add $s2,$s5,$s4
add $s4,$s2,$s5
sw $s5,100($s2)
add $s3,$s2,$s4
b) Trong on chng trnh sau, thanh ghi no c c trong chu k clock th 5,
thanh ghi no c ghi khi kt thc chu k clock th 5?
add $s1,$s2,$s3
add $s4,$s5,$s6
add $s7,$s8,$s0
add $t0,$t1,$t2
add $t3,$t4,$t5




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Bi gii
Bi 1:
Thanh ghi single precision l
1 1000 0101 10111000100000000000000
S = 1
Ereal= E bias = 133 127 = 6
S thc l: 1.101110001 x 2
^6
= -110.125
Bi 2:
a) Xc nh tc xung nhp (clock rate) ti a c th cp cho b x l MIPS theo kin
trc A.
Lnh load c thi gian thc thi lu nht nn CC = thi gian thc hin lnh load
Lnh load qua 5 giai on: np lnh + Thao tc trn register file (read) + thao
tc ALU + B nh + Thao tc trn register file (write)
Thi gian = 150 + 30 + 40 + 150 + 30 = 400ps
CC = 400ps => Clock rate = 1/CC = 2.5GHz
b) Xc nh speedup gia cc kin trc A v B, C v D.
Execution Time (A) = 400 * IC
Execution Time (B) = (0.15 * 400 + 0.1 *370 + 0.45 * 250 + 0.3 * 220) * IC =
275.5 * IC
=> speedup (B vs A) = 1.45
Execution Time (C) = CPI * IC * CC = (0.15 * 5 + 0.1 *4 + 0.45 * 4 + 0.3 * 3) * IC
* CC
= 3.85 * IC * CC
Vi kin trc D, v khng c stall v harzards nn CPI = 1
Execution Time (D) = 1 * IC * CC
=> speedup (D vs C) = 3.85
Bi 3:
a) Xc nh tt c ph thuc d liu (data dependency) trong on chng trnh sau.
Ph thuc no trong cc ph thuc trn c th c gii quyt bng k thut
forwarding?
add $s2,$s5,$s4
add $s4,$s2,$s5 # ph thuc lnh 1 (v S2)
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sw $s5,100($s2) # ph thuc lnh 1 (v S2)
add $s3,$s2,$s4 # ph thuc lnh 1 (v S2)
# ph thuc lnh 2 (v S4)
Tt c cc ph thuc trn u c th gii quyt bng k thut forwarding
b) Trong on chng trnh sau, thanh ghi no c c trong chu k clock th 5,
thanh ghi no c ghi khi kt thc chu k clock th 5?
add $s1,$s2,$s3
add $s4,$s5,$s6
add $s7,$s8,$s0
add $t0,$t1,$t2
add $t3,$t4,$t5
Thanh ghi t1, t2 c c trong chu k clock th 5
Thanh ghi s1 c ghi khi kt thc chu k clock th 5