SUBIECTE PROPUSE PENTRU EXAMENUL VLSI sem II

1. Folosind numai instructiuni VHDL concurente, se va modela un registru de

deplasare stanga dreapta cu autoblocare i tergere sincron.
entity reg is_
Port ( iData : in STD_LOGIC_VECTOR(0 to 7);
iClk : in STD_LOGIC;
iC1 : in STD_LOGIC;
iC0 : in STD_LOGIC;
oOut : out STD_LOGIC_VECTOR(0 to 7));
end reg;
architecture Behavioral of reg is
signal tmp,tmp1: STD_LOGIC_VECTOR(0 to 7);
begin

tmp <= "00000000" when iC1 = '0' and iC0 = '0' else -- stergere sincrona
iData when iC1 = '0' and iC0 = '1' else -- incarcare paralela
0&iData(0 to 6) when iC1 = '1' and iC0 = '0' else -- deplasare dreapta
iData(1 to 7)&0; --deplasare stanga

tmp1 <= tmp when rising_edge(iClk) else
tmp1;

oOut <= tmp1;

end Behavioral;

TESTBENCH


ENTITY testDeplasare_vhd IS
END testDeplasare_vhd;

ARCHITECTURE behavior OF testDeplasare_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT regDeplasare4biti
PORT(
iD : IN std_logic_vector(3 downto 0);
iClk : IN std_logic;
iSel : IN std_logic_vector(1 downto 0);
oQ : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
SIGNAL iClk : std_logic := '1';
SIGNAL iD : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL iSel : std_logic_vector(1 downto 0) := (others=>'0');

--Outputs
SIGNAL oQ : std_logic_vector(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: regDeplasare4biti PORT MAP(
iD => iD,
iClk => iClk,
oQ => oQ,
iSel => iSel
);

tb : PROCESS
BEGIN

-- Wait 100 ns for global reset to finish
wait for 100 ns;

iD <= "0100";
iSel <= "10"; --deplasare stanga

assert oQ = "1000";
report "eroare deplasare stanga" severity note;

wait for 100 ns;

iD <= "0100";
iSel <= "11"; --autoblocare

assert oQ = "1000";
report "eroare deplasare autoblocare" severity warning;

wait for 100 ns;

iD <= "0100";
iSel <= "01"; --deplasare dreapta

assert oQ = "0010";
report "eroare deplasare dreapta" severity warning;

wait for 100 ns;


iD <= "0100";
iSel <= "00"; --stergere sincrona

assert oQ = "0000";
report "eroare deplasare stergere" severity warning;

wait for 100 ns;

iD <= "1101";
iSel <= "10"; --deplasare stanga

assert oQ = "1010";
report "eroare deplasare stanga" severity warning;

wait for 100 ns;

iD <= "1101";
iSel <= "01"; --deplasare dreapta

assert oQ = "0110";
report "eroare deplasare dreapta" severity warning;

wait for 100 ns;

iD <= "0110";
iSel <= "11"; --autoblocare

assert oQ = "0110";
report "eroare deplasare autoblocare" severity warning;

wait for 100 ns;

iD <= "1101";
iSel <= "00"; --stergere sincrona

assert oQ = "0000";
report "eroare deplasare stergere" severity warning;

wait for 100 ns;


wait; -- will wait forever
END PROCESS;


process
begin
wait for 50 ns;
iClk <= not(iClk);
end process;

END;

2. Folosind numai instructiuni VHDL concurente, se va modela un
registru tampon pe 16 biti. Semnalul OC controleaza iesirile
dupa regula OC=0 iesiri in logica normala iar OC=1 iesiri in
stare de impedanta ridicata.

entity RegTampon16Biti is
Port ( iD : in STD_LOGIC_VECTOR (15 downto 0);
iOC : in STD_LOGIC;
oQ : out STD_LOGIC_VECTOR (15 downto 0);
iClk : in STD_LOGIC);
end RegTampon16Biti;

architecture Behavioral of RegTampon16Biti is

signal sD : STD_LOGIC_VECTOR(15 downto 0);

begin

process(iClk)
begin
if rising_edge(iClk)then
if(iOC = '1') then
sD <= iD;
else
sD <= "ZZZZZZZZZZZZZZZZ";
end if;
end if;
end process;
oQ <= sD;

end Behavioral;


TESTBENCH

ENTITY RegTampTest_vhd IS
END RegTampTest_vhd;

ARCHITECTURE behavior OF RegTampTest_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RegTampon16Biti
PORT(
iD : IN std_logic_vector(15 downto 0);
iOC : IN std_logic;
iClk : IN std_logic;
oQ : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;

--Inputs
SIGNAL iOC : std_logic := '0';
SIGNAL iClk : std_logic := '0';
SIGNAL iD : std_logic_vector(15 downto 0) := x"0000";

--Outputs
SIGNAL oQ : std_logic_vector(15 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: RegTampon16Biti PORT MAP(
iD => iD,
iOC => iOC,
oQ => oQ,
iClk => iClk
);

tb : PROCESS
BEGIN

-- Wait 100 ns for global reset to finish
wait for 100 ns;

iD <= x"F4E2";
iOC <= '1';

wait for 100 ns;

assert (oQ = x"F4E2") report "problema regim normal" severity note;

iOC <= '0';

wait for 100 ns;

assert (oQ = "ZZZZZZZZZZZZZZZZ") report "problema regim high
impedance" severity note;

iD <= x"1111";
iOC <= '1';

wait for 100 ns;

assert (oQ = x"1111") report "problema regim normal" severity note;




wait; -- will wait forever
END PROCESS;

process
begin

wait for 50 ns;
iClk <= not(iClk);

end process;

END;

3. Folosind numai instructiuni VHDL concurente, se va modela un numarator sincron
modulo variabil. Lungimea ciclului de numrare se selecteaz cu semnalul LM
(lungime modulo). Dac LM=0 , numrtorul este modulo 7. Dac LM=1,
numrtorul este modulo 12. Initializarea este asincron.

entity numarator10 is
Port ( iClock : in STD_LOGIC;
iReset : in STD_LOGIC;
LM : in STD_LOGIC;
oaY : out STD_LOGIC_VECTOR (3 downto 0));
end numarator10;

architecture Behavioral of numarator10 is
signal temp0,temp1 : STD_LOGIC_VECTOR (3 downto 0):= "0000";
begin

temp0 <= "0000" when iReset = '1' else
"0000" when temp0 = "0111" else
temp0 + 1 when rising_edge(iClock);

temp1 <= "0000" when iReset = '1' else
"0000" when temp1 = "1100" else
temp1 + 1 when rising_edge(iClock);


oaY <= temp0 when LM = '0' else
temp1 when LM = '1';

end Behavioral;
TESTBENCH

ENTITY tbNum_vhd IS
END tbNum_vhd;

ARCHITECTURE behavior OF tbNum_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT numSinc
PORT(
iLM : IN std_logic;
iClk : IN std_logic;
iR : IN std_logic;
oY : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
SIGNAL iLM : std_logic := '0';
SIGNAL iClk : std_logic := '0';
SIGNAL iR : std_logic := '0';

--Outputs
SIGNAL oY : std_logic_vector(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: numSinc PORT MAP(
iLM => iLM,
iClk => iClk,
iR => iR,
oY => oY
);

tb : PROCESS
BEGIN

-- Wait 100 ns for global reset to finish
wait for 100 ns;

-- num mod 7

iR <= '1';

wait for 10 ns;

iR <= '0';

wait for 890 ns;

iR <= '1';

wait for 10 ns;

iR <= '0';
iLM <= '1';

-- num mod 12

wait for 1390 ns;


wait; -- will wait forever
END PROCESS;

clock : process
begin
wait for 50 ns;
iClk <= not(iClk);
end process;

END;



4. Folosind numai instructiuni VHDL concurente, se va modela un dispozitiv pentru
generarea seriala a complementului fata de doi al numrului binar de la intrare,
introdus ncepnd cu bitul cel mai puin semnificativ. Initializarea este asincron.
entity p3 is
Port ( iNr : in STD_LOGIC_VECTOR (7 downto 0);
oNr : out STD_LOGIC_VECTOR (7 downto 0);
oDep: out STD_LOGIC);
end p3;

architecture Behavioral of p3 is
signal oNrTemp : STD_LOGIC_VECTOR (7 downto 0);
begin

oNrTemp <= not iNr(7 downto 0) + 1;
oNr <= oNrTemp;

oDep <= '1' when iNr <= "00000000" else '0';

end Behavioral;

TESTBENCH


5. Folosind numai instructiuni VHDL concurente, se va modela un numarator sincron
reversibil modulo 12. Sensul de numrare se selecteaz cu semnalul SENS. Dac
LM=0 , numrtorul este direct. Dac LM=1, numrtorul este invers. Initializarea
este asincron.
entity numarator10 is
Port ( iClock : in STD_LOGIC;
iReset : in STD_LOGIC;
isens: in STD_LOGIC;
oaY : out STD_LOGIC_VECTOR (3 downto 0));
end numarator10;

architecture Behavioral of numarator10 is
signal saQ,saY : STD_LOGIC_VECTOR (3 downto 0);
begin

saY <= "0000" when saQ="1011" and isens='1' else
"1011" when saQ = "0000" and isens='0' else
saQ+1 when isens='1' else
saQ-1 when isens ='0';

saQ <= "0000" when iReset = '1' else
saY when rising_edge(iClock) ;

oaY <= saQ;

end Behavioral;

TESTBENCH


6. Folosind numai instructiuni VHDL concurente, se va modela un numarator sincron
reversibil modulo 12. Sensul de numrare se selecteaz cu semnalul SENS. Dac
SENS =0 , numrtorul este direct. Dac SENS =1, numrtorul este invers.
Numrtorul este prevzut cu tergere sincron i autoblocare (selectate cu
semnalul SA numai daca numaratorul numara direct).

entity numarator10 is
Port ( iClock : in STD_LOGIC;
iSA : in STD_LOGIC;
isens: in STD_LOGIC;
oaY : out STD_LOGIC_VECTOR (3 downto 0));
end numarator10;

architecture Behavioral of numarator10 is
signal saQ,saY : STD_LOGIC_VECTOR (3 downto 0);
begin

saY <= "0000" when saQ="1011" and isens='1' else
"1011" when saQ = "0000" and isens='0' else
saQ+1 when isens='1' else
saQ-1 when isens ='0';


saQ <= "0000" when iSA= '1' and isens = '1' else
saY when rising_edge(iClock) ;

oaY <= saQ;

end Behavioral;

TESTBENCH

7. Folosind numai instructiuni VHDL concurente, se va modela un recunoscator
dinamic (Mealy sau Moore) cu intrarea de date pe doi bii care activeaza ieirea ori
de cate ori este recunoscut secvena 0123210.
entity rec is_
Port ( iData : in STD_LOGIC_VECTOR(1 downto 0);
iClk : in STD_LOGIC;
iReset : in STD_LOGIC;
oRecunoscut : out STD_LOGIC);
end rec;
012321
architecture Behavioral of rec is
type Stare is (s0,s1,s2,s3,s4,s5);
signal sStarePrez, sStareUrm: Stare;
begin

sStareUrm <= s1 when sStarePrez = s0 and iData = "00"' else -- s0
s0 when sStarePrez = s0 else -- s0
s2 when sStarePrez = s1 and iData = "01" else -- s1
s1 when sStarePrez = s1 and iData = "00" else --s1
s0 when sStarePrez = s1 else -- s1
s3 when sStarePrez = s2 and iData = "10" else -- s2
s1 when sStarePrez = s2 and iData = "00" else
s0 when sStarePrez = s2 else -- s2
s4 when sStarePrez = s3 and iData = "11" else -- s3
s1 when sStarePrez = s3 and iData = "00" else
s0 when sStarePrez = s3 else -- s3
s5 when sStarePrez = s4 and iData = "10" else -- s4
s1 when sStarePrez = s4 and iData = "00" else
s0 when sStarePrez = s4 else
s1 when sStarePrez = s5 and iData = "00" else
s0 when sStarePrez = s5;

sStarePrez <= s0 when iReset = '1' else
sStareUrm when rising_edge(iClk);

oRecunoscut <= '1' when sStarePrez = s5 and iData = "01" else '0';

end Behavioral;

TESTBENCH


8. Folosind numai instructiuni VHDL concurente, se va modela un recunoscator
static (Mealy sau Moore) cu intrarea de date pe doi bii care activeaza ieirea ori de
cate ori este recunoscut secvena 0123.
entity rec0123 is
Port ( iData : in STD_LOGIC_VECTOR (1 downto 0);
iReset : in STD_LOGIC;
iClk : in STD_LOGIC;
oY : out STD_LOGIC);
end rec0123;

architecture Behavioral of rec0123 is

type tState is (s0, s1, s2, s3, s4);

signal sPresentState, sNextState : tState;

begin

--Moore

-- sNextState <= s0 when sPresentState = s0 and iData /= "00" else
-- s0 when sPresentState = s1 and iData = "10"
else
-- s0 when sPresentState = s1 and iData = "11"
else
-- s0 when sPresentState = s2 and iData = "01"
else
-- s0 when sPresentState = s2 and iData = "11"
else
-- s0 when sPresentState = s3 and iData = "01"
else
-- s0 when sPresentState = s3 and iData = "10"
else
-- s0 when sPresentState = s4 and iData /= "00"
else
-- s1 when
iData = "00" else
-- s2 when sPresentState = s1 and iData = "01"
else
-- s3 when sPresentState = s2 and iData = "10"
else
-- s4 when sPresentState = s3 and iData = "11" ;


-- sPresentState <= s0 when iReset = '1' else
-- sNextState when rising_edge(iClk);

-- oY <= '1' when sNextState = s4 else
-- '0';



--Mealy

sNextState <= s0 when sPresentState = s0 and iData /= "00" else
s0 when sPresentState = s1 and iData = "10"
else
s0 when sPresentState = s1 and iData = "11"
else
s0 when sPresentState = s2 and iData = "01"
else
s0 when sPresentState = s2 and iData = "11"
else
s0 when sPresentState = s3 and iData = "01"
else
s0 when sPresentState = s3 and iData = "10"
else
s1 when
iData = "00" else
s2 when sPresentState = s1 and iData = "01"
else
s3 when sPresentState = s2 and iData = "10";


sPresentState <= s0 when iReset = '1' else
sNextState when rising_edge(iClk);

oY <= '1' when sPresentState = s3 and iData = "11" else
'0';
end Behavioral;


TESTBENCH

ENTITY tbRecunoscator_vhd IS
END tbRecunoscator_vhd;

ARCHITECTURE behavior OF tbRecunoscator_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT recunoscatorDinamic
PORT(
iD : IN std_logic_vector(1 downto 0);
iClk : IN std_logic;
oY : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL iClk : std_logic := '0';
SIGNAL iD : std_logic_vector(1 downto 0) := (others=>'0');

--Outputs
SIGNAL oY : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: recunoscatorDinamic PORT MAP(
iD => iD,
iClk => iClk,
oY => oY
);

tb : PROCESS
BEGIN

-- Wait 100 ns for global reset to finish
wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "00";

wait for 100 ns;

iD <= "01";

wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "11";

wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "01";

wait for 100 ns;

iD <= "00";

wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "00";

wait for 100 ns;

iD <= "01";

wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "00";

wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "01";

wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "11";

wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "01";

wait for 100 ns;

iD <= "00";

wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "10";

wait for 100 ns;

iD <= "11";

wait for 100 ns;

iD <= "00";

wait for 100 ns;


wait; -- will wait forever
END PROCESS;

clock : process
begin
iclk <= not(iClk);
wait for 50 ns;
end process;

END;





9. Folosind numai instructiuni VHDL concurente, se va modela un divizor de
frecven modulo 120.

entity DivFrecv120 is
Port ( iClk : in STD_LOGIC;
oY : out STD_LOGIC;
iReset : in STD_LOGIC);
end DivFrecv120;

architecture Behavioral of DivFrecv120 is

signal sNum , sT: STD_LOGIC_VECTOR(6 downto 0);

begin

sNum <= "0000000" when iReset = '1' else
sT when rising_edge(iClk);

sT <= sNum + 1 when sNum < "1110111" else
"0000000";

oY <= '1' when sNum = "1110111" else
'0';


end Behavioral;
TESTBENCH

ENTITY tb_vhd IS
END tb_vhd;

ARCHITECTURE behavior OF tb_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DivFrecv120
PORT(
iClk : IN std_logic;
iReset : IN std_logic;
oY : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL iClk : std_logic := '0';
SIGNAL iReset : std_logic := '0';

--Outputs
SIGNAL oY : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: DivFrecv120 PORT MAP(
iClk => iClk,
oY => oY,
iReset => iReset
);

tb : PROCESS
BEGIN

-- Wait 100 ns for global reset to finish
wait for 100 ns;

iReset <= '1';

wait for 10 ns;

iReset <= '0';

wait for 280 ns;

iReset <= '1';

wait for 10 ns;

iReset <= '0';

wait; -- will wait forever
END PROCESS;

clock : process
begin

iClk <= not(iClk);
wait for 10 ns;

end process;

END;




10. Folosind numai instructiuni VHDL concurente, se va modela un numrtor
decadic modulo 24.
entity numarator is
Port ( iClk : in STD_LOGIC;
iReset : in STD_LOGIC;
oQ1 : out STD_LOGIC_VECTOR (3 downto 0);
oQ0 : out STD_LOGIC_VECTOR (3 downto 0));
end numarator;

architecture Behavioral of numarator is
signal aux1, aux2 : std_logic_vector(3 downto 0);
--signal ocY, icY : std_logic;
begin
aux1 <= "0000" when iReset='1' or aux1=10 or (aux1=4 and aux2=2)else
aux1+1 when rising_edge(iClk);

--ocY <='1' when aux1=9 else '0';

aux2 <= "0000" when iReset='1' or (aux2=2 and aux1=4) else
aux2+1 when rising_edge(iClk) and aux1 = 9;

oQ0 <= aux1;
oQ1 <= aux2;


end Behavioral;

TESTBENCH


11. Folosind numai instructiuni VHDL concurente, se va modela schema de comand
descris cu ajutorul unei diagrame ASM.

entity ASM is
Port ( iX : in STD_LOGIC;
iY : in STD_LOGIC;
iZ : in STD_LOGIC;
iReset : STD_LOGIC;
iClk : STD_LOGIC;
oC1N : out STD_LOGIC;
oC2 : out STD_LOGIC);
end ASM;

architecture Behavioral of ASM is

type tState is (sA, sB, sC);
signal sPresentState, sNextState : tState;

begin

sNextState <= sA when sPresentState = sA and iX = '1' else
sA when sPresentState = sB and
iZ = '0' else
sA when sPresentState = sC and
iZ = '1' else
sB when sPresentState = sA and
iX = '0' and iY = '1' else
sC when sPresentState = sA and
iX = '0' and iY = '0' else
sB when sPresentState = sC and
iZ = '0' else
sC when sPresentState = sB and
iZ = '1' else
sA;

sPresentState <= sA when iReset = '1' else
sNextState when
rising_edge(iClk);

oC1N <= '1' when sPresentState = sB or (sPresentState = sA
and iX = '0' and iY = '1') else --C1# = Ax#y + B
'0';

oC2 <= '1' when sPresentState = sC or (sPresentState = sA
and iX = '0' and iY = '0') else --C2 = Ax#y# + C
'0';

end Behavioral;



TESTBENCH

ENTITY tbASM_vhd IS
END tbASM_vhd;

ARCHITECTURE behavior OF tbASM_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ASM
PORT(
iX : IN std_logic;
iY : IN std_logic;
iZ : IN std_logic;
iReset : IN std_logic;
iClk : IN std_logic;
oC1N : OUT std_logic;
oC2 : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL iX : std_logic := '0';
SIGNAL iY : std_logic := '0';
SIGNAL iZ : std_logic := '0';
SIGNAL iReset : std_logic := '0';
SIGNAL iClk : std_logic := '0';

--Outputs
SIGNAL oC1N : std_logic;
SIGNAL oC2 : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: ASM PORT MAP(
iX => iX,
iY => iY,
iZ => iZ,
iReset => iReset,
iClk => iClk,
oC1N => oC1N,
oC2 => oC2
);

tb : PROCESS
BEGIN

-- Wait 100 ns for global reset to finish
wait for 100 ns;

iReset <= '1';

wait for 10 ns;

iReset <= '0';

wait for 90 ns;

iX <= '1';

iY <= '0';

iZ <= '0';

wait for 100 ns;

iX <= '0';

iY <= '1';

iZ <= '0';

wait for 100 ns;

iX <= '1';

iY <= '1';

iZ <= '0';

wait for 100 ns;

iX <= '0';

iY <= '0';

iZ <= '1';

wait for 100 ns;

iX <= '1';

iY <= '0';

iZ <= '1';

wait for 100 ns;

iX <= '0';

iY <= '1';

iZ <= '1';

wait for 100 ns;

iX <= '1';

iY <= '1';

iZ <= '1';


wait; -- will wait forever

END PROCESS;

clock : process
begin

iClk <= not(iClk);

wait for 50 ns;

end process;

END;






A
X#
Y#
B C
Z
F
F
F
C1# C2
C1# C2
Z
F
T
T
T
T

A
X#
B
C
Y#
F
F
F
C1#
Z
F
T
T
T
T
C1#,C2
Z
C1#
C2

12. Folosind numai instruciuni VHDL concurente se va modela un
registru multifunctional cu autoblocare, incarcare paralela, deplasare stanga/
dreapta