A new series parallel switched multilevel dc-link inverter topology

S. Ramkumar
a,
, V. Kamaraj
b
, S. Thamizharasan
a
, S. Jeevananthan
c
a
Surya College of Engineering and Technology, Villupuram, India
b
SSN College of Engineering, Chennai, India
c
Pondicherry Engineering College, Puducherry, India
a r t i c l e i n f o
Article history:
Received 8 June 2011
Received in revised form 18 October 2011
Accepted 29 October 2011
Available online 16 December 2011
Keywords:
Multilevel dc link inverter (MLDCI)
Switch count
Total harmonic distortion (THD)
Field programmable gate array (FPGA).
a b s t r a c t
The variable voltage and frequency requirements emphasize the need and elaborate the increasing trend
of using multilevel inverters (MLI) in modern drives and utility applications. The MLIs carves out a nearly
sinusoidal voltage from a stair case like waveform and the distortion level in the output voltage depends
on the number of steps. Increased component count and extension of basic modulation strategies to the
MLIs pose a bigger threat in the form layout size, cost and complexity of the gating circuits. These con-
icting requirements force to explore different and or new congurations to meet the state of art neces-
sities and it is this perspective a host of topologies keep emerging. Topologies based on multilevel dc-link
inverter (MLDCLI) structure pioneer the component reduction and add benets to suit economic and
power quality considerations besides living up to technological innovation. The paper orients to develop
a new variety of MLDCLI named series parallel switched multilevel dc-link inverter (SPMLDCLI) with a
primary objective to arrive at reduced component count for a particular voltage level. By appropriately
choosing a ratio for the voltage sources (V
0
:V
n
) and connecting them in series/parallel, a particular level
in the output voltage is generated and hence the name SPSMLDCLI. The performance of the topology is
investigated through MATLAB based simulation over a range of viable modulation indices and validated
using a prototype to propel its applicability in the present day context. The conventional sub harmonic
pulse width modulation strategy (SHPWM) with pulse pattern suitable for SPSMLDCLI is considered.
2011 Elsevier Ltd. All rights reserved.
1. Introduction
The use of multilevel inverter (MLI) appears to experience an
increasing trend in view of the extensive automation in industries
[15]. The medium to high voltage interface further enhances the
need and it is this perspective owing to which a host of topologies
keep emerging [6]. A good number of MLI topologies are in use over
the past four decades [710]. There are conicting requirements
forcing to explore different and or new congurations to meet the
state of the art necessities [11]. The technology trace pioneers the
dc-link oriented structures and directs changes to incorporate
added benets to suit economic and power quality considerations
besides living up to technological innovation. There are a host of
MLI topologies that continue to receive great attention and each
inherit their own merits based on count of switches, capacitors,
diodes and the number of output levels produced from a xed
number of sources [12,13].
The emergence of a new class of MLIs based on a multilevel
dc-link (MLDCL) and a bridge inverter to reduce the number of
switches, clamping diodes or capacitors appears to be a break-
through in multilevel power conversion applications [14]. The
MLDCLI can be formed by connecting a MLDCL which provides a
dc voltage with the shape of approximating the rectied shape of
a dictated sinusoidal wave, with or without pulse width modula-
tion, to the bridge inverter, which in turn alternates the polarity
to produce an ac voltage. These inverters signicantly reduce the
number of switches and gate drivers as the number of voltage level
increases. However, these structures do not entail a satisfactory
operation with unequal voltage sources. It thus perpetuates the
need for better structures with the ability to produce still higher
number of levels using unequal voltage sources and further com-
ponent reduction.
The cascaded MLI with different voltages [15] in the dc buses of
each H-bridge cell envisions the next in line called the hybrid mul-
tilevel power inverter. It is possible to synthesize more levels than
that with a symmetric topology [16] if the voltage level of each dc
bus is properly chosen with the same number of switches. Among
the asymmetric multilevel inverters, cascaded multilevel H-bridge
inverter with different dc voltage sources is particularly attractive
as it is free from capacitor voltage balancing but the power devices
are subjected to unequal voltage stress [17,18].
Multilevel topologies using bulk capacitors as a medium to syn-
thesize voltage levels lead to unbalanced voltage levels [19]. It au-
gurs the need for an adequate control or modulation strategy to
balance the voltage in the different capacitors of each topology. It
0142-0615/$ - see front matter 2011 Elsevier Ltd. All rights reserved.
doi:10.1016/j.ijepes.2011.10.028

Corresponding author.
E-mail address: set.dean@gmail.com (S. Ramkumar).
Electrical Power and Energy Systems 36 (2012) 9399
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Fig. 1. Generalized structure of SPSMLDCLI.
Fig. 2. SPSMLDCLI operating mode-level 1(50 V).
Fig. 3. SPSMLDCLI operating mode-level 2(100 V).
Fig. 4. SPSMLDCLI operating mode-level 3(150 V).
94 S. Ramkumar et al. / Electrical Power and Energy Systems 36 (2012) 9399
prevents the usage of existing control strategies of MLIs and an
alternate solution of innovative topologies that eliminate the
capacitor based voltage media. This paper presents a new variety
of MLDCLI which uses lower number of sources, power switches
and eliminates the necessity of capacitors. The proposed topology
coined as series parallel switched multilevel dc-link inverter
(SPSMLDCLI) synthesizes a nearly distortion less sinusoidal output
voltage owing to its inherent ability to increase the number of lev-
Fig. 5. SPSMLDCLI operating mode-level 4(200 V).
Fig. 6. SPSMLDCLI operating mode-level 5(250 V).
Fig. 7. SPSMLDCLI operating mode-level 6(300 V).
Fig. 8. SPSMLDCLI operating mode-level 7(350 V).
S. Ramkumar et al. / Electrical Power and Energy Systems 36 (2012) 9399 95
els. The performance of this SPMLDCLI is investigated through
MATLAB based simulation over a range of viable modulation indi-
ces and validated using a FPGA based prototype [16].
2. Proposed topology
The generalized structure of the proposed SPSMLDCLI topology
contains voltage sources in the ratio V
o
:V
n
= 1:3, switches and a
diode along with a H-bridge, that offers a minimumof fteen levels
is shown in Fig. 1. While the switches S
a
, S
b
, S
c
, S
a1
, S
b1,
S
c1
, S
an
, S
bn
and S
cn
form the dc-link circuit, the switches S
1
, S
2
, S
3
and S
4
constitute the H-bridge inverter. The part of the circuit enclosed
between the dotted lines acts as the parent cell and is the
obligatory structure in the dc-link part. The structure external to
the parent cell is named as a teen cell and every addition of a teen
cell gives way to raise six levels and there by avails the benet to
extend to the desired level.
The modes of operation of the basic fteen level SPSMLDCLI are
explained with V
0
:V
1
:V
2
= 1:3:3 to elicit the complete working of
the power module. The switches S
1,
S
2
and S
3
, S
4
in the H-bridge
are turned on alternatively, while both S
a1
and S
c
in the dc-link part
are allowed to conduct to arrive at the rst level of voltage as seen
in Fig. 2. In addition to the H-bridge, when the switch S
c1
in the dc-
link conducts, the topology lands at the second level as observed
fromFig. 3.The mode diagrams for the subsequent levels are shown
in Figs. 48. Accordingly the status of the switches are pictured for
the remaining levels and the sequence for synthesizing different
voltage levels in the fteen level SPSMLDCI is summarized in
Table 1. The entries in Table 2 compare the switch and source
requirements for the fteen level topology with the existing MLI
topologies to highlight the reduction in the count.
Table 2
Comparison between topologies for 15 level.
Multilevel
inverter
structure
Cascaded
H-bridge
Diode
clamped
Flying
capacitor
Multilevel dc-link inverter Proposed
Cascaded
half
bridge
Diode
clamped
Flying
capacitor
Main
switches
28 28 28 18 18 18 10
Bypass
diodes
1
Clamping
diodes
24 12
DC split
capacitors
6 6 6 6
Clamping
capacitors
12 6
DC sources 7 1 1 7 1 1 3
Total 35 59 47 25 37 31 14
Fig. 9. Inter-looping in dc-link structure.
Fig. 10. Output voltage using (a) Generic switches and (b) MOSFETs.
Table 1
Switching sequence for 15 level.
Voltage level Switches
S
a
S
b
S
c
S
a1
S
b1
S
c1
D
B
S
1
S
3
S
2
S
4
+7
p p p p
+6
p p p p
+5
p p p p
+4
p p p p p
+3
p p p p
+2
p p p p
+1
p p p p
0
p p p p p p
1
p p p p
2
p p p p
3
p p p p
4
p p p p p
5
p p p p
6
p p p p
7
p p p p
96 S. Ramkumar et al. / Electrical Power and Energy Systems 36 (2012) 9399
It is evident from the Table 2 that the number of power devices
required is only ten which is 76% less when compared with the ba-
sic MLI topologies and 44% with MLDCLIs. It is equally signicant to
note that the difference in the total component count stands at
forty-ve when it is compared with a similar conventional case.
The precise number of levels of output voltage that a SPSMLDCLI
can synthesize is expressed using a relation23n 1 1 where
n is the number of voltage sources excluding V
0
, if arranged in
the ratio V
0
:V
n
= 1:3.
The available power switches where a simple switch and an anti
parallel diode are patched to permit regeneration experience a spe-
cic phenomenon of inter-looping and consequently create two
circulating current paths as indicated with different colors in
Fig. 9. It may lead to a possible distortion in the output voltage
and deviate away from the ideal waveform as seen from Fig. 10a
and b. The problem can however be eliminated by replacing the
switches with IGBT switches as shown in Fig. 11.
Fig. 11. Eliminating inter-looping with IGBTs.
Fig. 12. Dc-link voltage waveform.
Fig. 13. Output voltage waveform and harmonic spectrum.
Fig. 14. Inductive load current.
S. Ramkumar et al. / Electrical Power and Energy Systems 36 (2012) 9399 97
3. Simulation
The basic fteen level SPSMLDCI is simulated using MATLAB
R2010a. The voltage sources in the topology are chosen accordingly
to offer an output of 220 V and a resistance of 110 O as the load.
The approach seeks the role of a PD-MC PWMtechnique with a car-
rier frequency of 4 kHz as the ring strategy. The MLDCL voltage
produced by the parent cell and the unfolded ac output voltage
waveform from the H-bridge along with harmonic spectrum are
shown in Figs. 12 and 13 respectively. The output current wave-
form for a RL load (R = 50 X and L = 20 mH) is displayed in Fig. 14.
The variation of THD as a function of the fundamental compo-
nent over a range of modulation indices for both the proposed
and CHBMLDCLI is depicted in Fig. 15 and observed that as the out-
put voltage magnitude increases the THD decreases. It serves to
bring out that the new structure eclipses a much lower harmonic
content of the output voltage for a projected target.
4. Hardware implementation
A prototype seen in Fig. 16 is constructed using similar power
switches as those used in simulation to operate under similar spec-
ications. The experimental arrangement is constituted of MOS-
FETs (IRF 840), diode (BYQ 28E), IGBTs (FIO 5O-12BD) and a
resistive load of 110 O. It seeks the role of Xilinx based system gen-
erator facility available as a toolbox in MATLAB R2010a to generate
the multi carrier PWM pulses for the power switches. The scheme
involves an appropriate mechanism through which the VHDL code
required to suit a Xilinx Spartan XC3SD1800A-FG676-4 Spartan 3A
DSP FPGA board is acquired and there from buffered to turn on the
power switches in the SPSMLDCLI [20]. The ow diagram of the
strategy is explained through Fig. 17.
The experimental prototype depicting the interface of power
module and control algorithm is photographed in Fig. 16. The gat-
ing signals captured through Tektronix TPS 2024 scope are shown
in Fig. 18. The dc- link and the load voltage waveforms along with
the harmonic spectrum corresponding to a modulation index of 0.9
and an output of 220 V are portrayed in Fig. 19. The fact that the
same fundamental output is obtained for the designed output level
both using simulation and hardware with comparable THD values
goes to validate the PWM technique in addition to highlighting the
practical feasibility of the proposed MLI conguration. The entries
in Table 3 serve to adequately validate the simulated and hardware
results through a close comparison of their harmonic components
of the output voltage over a range of specied targets.
Fig. 15. Fundamental component Vs THD.
Fig. 16. Prototype of SPSMLDCLI.
Fig. 18. Gating signals (a) Parent cell and (b) H-bridge.
Fig. 17. Flow chart for pulse generation using FPGA.
98 S. Ramkumar et al. / Electrical Power and Energy Systems 36 (2012) 9399
The output current waveform for the same values of RL load as
that used in simulation is seen Fig. 20 and it shows that the topol-
ogy also works well for a RL load.
5. Conclusion
A new SPSMLDCLI structure with a reduced number of power
switches has been suggested to steal home an innovation in this
domain. The philosophy has been to eclipse the increase in the
voltage levels through a new topology that imbibes a parent and
a tting number of teen cells along with a single full bridge to cater
to bidirectional power ow. It has been able to aggregate a much
better performance in the sense it facilitates more or less a sinusoi-
dal output voltage. The measure by which it excels has been
strongly authenticated through a series of results with a view to
illustrate its applicability in the present day context. The fact that
any level of target can be achieved using this conguration will go
a long way in exploring new dimensions in this domain.
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Table 3
Comparison of simulation and experimental results.
V
01 (V)
Simulation Hardware
THD (%) THD (%)
100 19.4 18.28
120 15.58 16.52
140 12.77 14.02
160 12.14 11.28
180 9.69 10.12
200 9.70 10.52
220 8.28 8.50
Fig. 19. (a) Dc-link voltage and load voltage waveforms and (b) Load voltage spectrum.
Fig. 20. Output current waveform for RL load.
S. Ramkumar et al. / Electrical Power and Energy Systems 36 (2012) 9399 99