Kongunadu College of Engineering and Technology

M.E-Applied Electronics
Advanced Digital System Design-Assignment-I

1.Design a serial adder using mealy model and Moore model. Also
draw the ASM chart for both the models.

2. Write down the design steps involved in designing Traditional
synchronous sequential circuits.

3. With an example explain the state assignment rules.

4. Determine the minimal state equivalent of the state table given


5. Design a sequential circuit to convert BCD to excess 3 codes

6. Design an asynchronous sequential circuit that has two inputs X2 and
X1 and one output Z. When X1 = 0, the output Z is 0. The first change in
X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z
remains at 1 until X1 returns to 0.

7. Explain the design steps involved in the realization of ASM.



8. Design a Fundamental mode asynchronous sequential network
meeting the following requirements :
(i) There are 2 inputs xl and x2 and single output z.
(ii) The inputs xl and x2 never change simultaneously
(iii) An output z = 1 is to occur only during the input state xlx2 = 01
and if input state xlx2 = 01 is preceded by input sequence x1x2 =
01,00,10,00,10,00.

9. Determine the minimal state equivalent of the state table given using
Implication chart.

10. Design a gated latch circuit with two inputs, G (gate) and D (data),
and one output Q. The gated latch is a memory element that accepts the
value of D when G = 1 and retains this value after G goes to 0. Once G
= 0, a change in D does not change the value of the output Q.