Lecture 5 part 1

Mch t hp:
Arithmetic Circuits
Ni dung
1. Mch cng (Carry Ripple (CR) Adder)
2. Mch cng nhn trc s nh - (Carry Look-
Ahead (CLA) Adder)
3. Mch cng/ mch tr
4. n v tnh ton lun l (Arithmetic Logic Unit)
1. Mch cng Carry Ripple (CR)
Cng 2 s 1 bit c 4 trng hp
Mch cng 1 bit c tng v s
nh nh th ny c gi l
mch cng bn phn (HA)
Mch cng bn phn (Half Adder)
S mch
x
y
Tng S nh
Mch cng nh phn song song
Cng nhng s c 2 hoc nhiu bit
Cng tng cp bit bnh thng
Nhng v tr cp bit i, c th c s nh u vo (carry-
in) t bit i-1
Tng
S
nh
S
hng
S
hng
(S cng
vo v tr
k tip)
Thit k mt b cng ton phn (Full Adder)
B cng ton phn (FA)

3 ng vo (2 ng vo cho 2 s 1-bit cn tnh tng,
v 1 ng vo cho s nh u vo (carry-in)

2 ng ra (1 ng ra cho tng v 1 cho s nh u
ra (carry-out)
Thit k mt b cng ton phn (Full Adder)
Bng s tht
Biu tng
S
hng
x
S
hng
y
Carr
y-in
C
IN
Carry
-out
C
OUT

Tng
S
y
x
Thit k mt b cng ton phn (Full Adder)
i i i i
S x y c
1 i i i i i i i
c x y x c y c

1 i OUT
c c

i IN
c c
Bng s tht
S
hng
x
S
hng
y
Carr
y-in
C
IN
Carry
-out
C
OUT

Tng
S
Thit k mt b cng ton phn (Full Adder)
S mch
Biu tng
Biu tng khc
i i i i
S x y c
1 i i i i i i i
c x y x c y c

1 i OUT
c c

i IN
c c
Thit k mt b cng ton phn (Full Adder)
i i i i
S x y c
1
( )
i i i i i i
c x y c x y

S dng li HA
S chi tit
S khi
S mch HA
x
y
Mch cng Carry Ripple (CR)
S biu din mch cng 4 bit song song s
dng full adder
Mch cng Carry Ripple
Mch FA bt u vi vic cng cc cp bit t LSB
n MSB
Nu carry xut hin v tr bit i, n c cng thm
vo php cng v tr bit th i+1

Vic kt hp nh vy thng c gi l mch
cng carry-ripple
v carry c ripple t FA ny sang cc FA k tip
Tc php cng b gii hn bi qu trnh truyn s
nh
Mch cng Carry Ripple
Mi FA c mt khong tr (delay), gi s l t
tr ph thuc vo s lng bit
Carry-out FA u tin C
1
c c sau t
Carry-out FA u tin C
2
c c sau 2t
=> C
n
c tnh ton sau nt
M hnh carry look ahead (CLA) thng c s dng ci thin tc
2. Mch cng nhn trc s nh
Carry Look-Ahead (CLA) Adder
Hiu nng
Tc ca mch b gii hn bi tr ln nht
dc theo ng ni trong mch

tr ln nht c gi l critical-path-
delay

ng ni gy ra tr gi l critical path
Carry Look-Ahead Adder (CLA)
Ci thin tc mch cng
Xc nh nhanh gi tr carry-out mi ln cng vi
carry-in ln cng trc s c gi tr 0 hay 1





Mc tiu: gim critical-path-delay
Hm xc nh carry-out ln cng th i
c
i+1
= x
i
y
i
+ x
i
c
i
+ y
i
c
i
= x
i
y
i
+ (x
i
+ y
i
)c
i

t g
i
= x
i
y
i
v p
i
= x
i
+ y
i
=> c
i+1
= g
i
+ p
i
c
i

g
i
= 1 khi c x
i
v y
i
u bng 1, khng quan tm c
i
g c gi l hm generate, v carry-out lun
c generate ra khi g=1
p
i
= 1 khi x
i
= 1 hoc y
i
= 1; carry-out = c
i

p c gi l hm propagate, v carry-in = 1
c propagate (truyn) ln cng th i
Carry Look-Ahead Adder (CLA)
Xc nh carry-out ca mch cng n bit
c
n
=g
n-1
+ p
n-1
c
n-1
M c
n-1
=g
n-2
+ p
n-2
c
n-2
c
n
=g
n-1
+ p
n-1
(g
n-2
+ p
n-2
c
n-2
)
c
n
=g
n-1
+ p
n-1
g
n-2
+ p
n-1
p
n-2
c
n-2

Tip tc khai trin n ln cng u tin
c
n
=g
n-1
+p
n-1
g
n-2
+p
n-1
p
n-2
g
n-3
++p
n-1
p
n-2
.p
1
g
0
+p
n-1
p
n-2
.p
1
p
0
c
0

Carry Look-Ahead Adder (CLA)
Carry Look-Ahead Adder (CLA)
S nh u vo c
0

c truyn qua
tt c cc ln cng
S nh sinh ra ln cng
th 1 v c truyn qua
cc ln cng cn li
S nh sinh ra ln cng
th n-2 v c truyn qua
cc ln cng cn li
S nh sinh ra ln cng
th n-1 v c truyn qua
cc ln cng cn li
S nh sinh ra
ln cng cui cng
V d: Trng hp cng 4 bit
C
1
= G
0
+ P
0
.C
0

C
2
= G
1
+ P
1
.G
0
+ P
1
.P
0
.C
0

C
3
= G
2
+ P
2
.G
1
+ P
2
.P
1
.G
0
+ P
2
.P
1
.P
0
.C
0

C
4
= G
3
+ P
3
.G
2
+ P
3
.P
2
.G
1
+ P
3
P
2
.P
1
.G
0
+ P
3
P
2
.P
1
.P
0
.C
0
Carry Look-Ahead Adder (CLA)
Mch cng CLA - critical path
Tm li, tr 2n+1 i vi
mch cng Carry Ripple n-bit
tr 3 cng i vi
tr 5 cng i vi
Mch cng CLA - critical path
C
1
= G
0
+ P
0
.C
0

C
2
= G
1
+ P
1
.G
0
+ P
1
.P
0
.C
0

tr 3 cng i vi
tr 3 cng i vi
tr 3 cng i vi
tr tng cng cho mch
cng CLA n-bit l tr 4 cng
- gi, pi: tr 1 cng
- Ci: tr 2 cng
- tr 1 cng cn li l do
tnh tng s
Gii hn ca CLA
Biu thc tnh carry trong mch cng CLA
c
n
=g
n-1
+p
n-1
g
n-2
+p
n-1
p
n-2
g
n-3
++p
n-1
p
n-2
.p
1
g
0
+p
n-1
p
n-2
.p
1
p
0
c
0

CLA l gii php tc cao (2 level AND-OR)

Fan-in issue c th hn ch tc ca CLA
Thit b c vn vi fan-in issue (vd: FPGA) thng
km mch ring hin thc mch cng nhanh
phc tp tng ln nhanh chng khi n ln
Hierrachical approach gim phc tp
3 Adder/ Subtractor

Mch cng/ tr
X,Y l 2 s khng du n-bit
Php cng: S = X + Y
Php tr: D = X - Y = X + (-Y) =
= X+ (B 2 ca Y)
= X+ (B 1 ca Y) + 1
= X+ Y+ 1

Mch tr
Mch cng Carry Ripple c th c dng xy
dng mch tr Carry Ripple bng cch o Y v t
s nh u tin l 1

Trn (Arithmetic Overflow)
Overflow l khi kt qu ca php ton vt
qu s bit biu din phn gi tr
n bit biu din c s t -2
n-1
n +2
n-1
-1
Overflow lun lun cho ra 1 kt qu sai





=> Mch xc nh c overflow hay khng
V d v arithmetic overflow
Vi s 4 bit, 3 bit gi tr v 1 bit du
Overflow khng xut hin khi cng 2 s tri du
O
O
Arithmetic overflow
Overflow c th pht hin c (t v d slide
trc)

Overflow = c
3
c
4
+ c
3
c
4
Overflow = c
3
c
4
Mch cng/ tr c th b sung mch kim tra overflow
vi 1 cng XOR
Vi n bit

Overflow = c
n-1
c
n
V d
Thit k mt mch cng/ tr vi 2 ng iu khin
ADD v SUB
ADD = 1: mch cng 2 s trong 2 thanh ghi A v B
SUB = 1: mch thc hin php tr s B-A

Ch :
Trong mt lc ch mt trong hai ng ADD, SUB bng 1
V d
4 Arithmetic Logic Unit (ALU)

ALU
ALUs c th thc thi nhiu ton t v hm logic
khc nhau
Cc ton t v hm c xc nh bi mt m ng vo
Inputs
S2 S1 S0 Function
0 0 0 F = 0000
0 0 1 F = B A 1 + Cin
0 1 0 F = A B 1 + Cin
0 1 1 F = A + B + Cin
1 0 0 F = A B
1 0 1 F = A + B
1 1 0 F = A * B
1 1 1 F = 1111
Any question?