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ISE 6.3i 1-800-255-7778
FJKCP
R
FJKCP
J-K Flip-Flop with Asynchronous Clear and Preset
FJKCP is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), and
asynchronous preset (PRE) inputs and data output (Q). When the asynchronous clear
(CLR) is High, all other inputs are ignored and Q is reset 0. The asynchronous preset
(PRE), when High, and CLR set to Low overrides all other inputs and sets the Q
output High. When CLR and PRE are Low, Q responds to the state of the J and K
inputs during the Low-to-High clock transition, as shown in the following truth table.
The flip-flop is asynchronously cleared, output Low, when power is applied. The
power-on condition can be simulated by applying a High-level pulse on the PRLD
global net.
FJKCP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Architectures Supported
FJKCP
Spartan-II, Spartan-IIE No
Spartan-3 No
Virtex, Virtex-E No
Virtex-II, Virtex-II Pro, Virtex-II Pro X No
XC9500, XC9500XV, XC9500XL Macro
CoolRunner XPLA3 Macro
CoolRunner-II Macro
Inputs Outputs
CLR PRE J K C Q
1 X X X X 0
0 1 X X X 1
0 0 0 0 X No Chg
0 0 0 1 0
0 0 1 0 1
0 0 1 1 Toggle
Q
J
C
FJKCP
K
PRE
CLR
X4390
Q
X8124
C
AND2B1
FDCP
D
C
Q
PRE
OR2
K
AND2B1
PRE
CLR
Q
J
CLR
FJKCP
R
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Usage
For HDL, this design element is inferred rather than instantiated.