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    Suggestions For Level II Interrupt Logic

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    ngayhevui
    Dean Schamburger raised a concern about the possibility of bursts of 15 level 2 (L2) rejects arriving at the rate of one per clock cycle overwhelming the processor. The document proposes connecting the empty flag of a first-in-first-out (FIFO) buffer for L2 decisions to a level sensitive interrupt pin on the processor. This would re-interrupt the processor as soon as one L2 decision is handled, avoiding processor confusion from multiple interrupts. A diagram shows the proposed L2 interrupt logic using the FIFO buffer and level sensitive interrupt.

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    Suggestions For Level II Interrupt Logic

    Uploaded by

    ngayhevui
    27 views1 page
    Dean Schamburger raised a concern about the possibility of bursts of 15 level 2 (L2) rejects arriving at the rate of one per clock cycle overwhelming the processor. The document proposes connecting the empty flag of a first-in-first-out (FIFO) buffer for L2 decisions to a level sensitive interrupt pin on the processor. This would re-interrupt the processor as soon as one L2 decision is handled, avoiding processor confusion from multiple interrupts. A diagram shows the proposed L2 interrupt logic using the FIFO buffer and level sensitive interrupt.

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    l2_irq

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    l2_irq

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    Dean Schamburger raised a concern about the possibility of bursts of 15 level 2 (L2) rejects arriving at the rate of one per clock cycle overwhelming the processor. The document proposes connecting the empty flag of a first-in-first-out (FIFO) buffer for L2 decisions to a level sensitive interrupt pin on the processor. This would re-interrupt the processor as soon as one L2 decision is handled, avoiding processor confusion from multiple interrupts. A diagram shows the proposed L2 interrupt logic using the FIFO buffer and level sensitive interrupt.

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    27 views1 page

    Suggestions For Level II Interrupt Logic

    Uploaded by

    ngayhevui
    Dean Schamburger raised a concern about the possibility of bursts of 15 level 2 (L2) rejects arriving at the rate of one per clock cycle overwhelming the processor. The document proposes connecting the empty flag of a first-in-first-out (FIFO) buffer for L2 decisions to a level sensitive interrupt pin on the processor. This would re-interrupt the processor as soon as one L2 decision is handled, avoiding processor confusion from multiple interrupts. A diagram shows the proposed L2 interrupt logic using the FIFO buffer and level sensitive interrupt.

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    of 1

    S.

    Hansen 7-30-98
    Suggestions for Level II Interrupt Logic
    Dean Schamburger brought up the point during our last Muon Electronics review that it
    was theoretically possible to have as many as 15 L2 rejects that arrived at the rate of one per
    crossing. If there was a DSP interrupt for every L2 decision, this string of rejects would confuse
    the processor, since the L2 interrupt service routine takes a couple of microseconds to run. A
    possible solution would be to change the L2 interrupt logic. There is a register in the 21csp01 that
    selects level or edge sensitivity for each external interrupt. If all L2 decisions were written to a
    FIFO and the empty flag of that FIFO was connected to a level sensitive interrupt pin, then there
    would be no problem with a burst of L2 rejects. The processor would be re-interrupted as soon as
    one L2 decision had been handled. Since L1 interrupts have higher priority, the L2 service routine
    would be preempted when an L1 accept occurred. A diagram of the L2 interrupt logic is shown
    below:
    WS
    XN0..XN7
    RF/7
    L2 REJ
    L2 ACC
    EF L2IRQ
    L2 TRIG
    DATA
    F
    I
    F
    O
    L2 Interrupt Logic
    9
    8

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