EEE C364/INSTR C364

Analog Electronics
ADC
Lecture 32
19-04-2012
Uses only two values of resistors
Overcomes the limitations of Binary
weighted DAC
OPAMP is connected in inverting mode
Each digital input is applied through R-2R
network and V
r
R-2R LADDER TYPE DAC
R-2R ladder D/A converter
Charge redistribution architecture
Redistribution switch
C
1
= C
2
= C
S
2
is used to recharge C
1
to V
r
if i
th
bit is 1
S
3
is used to recharge C
1
to 0 if i
th
bit is 0
C2 isinitially discharged using S
4
before the beginning
of the conversion
( )
3
3
2
2
1
1
2 2 2
8 4 2 2
2 4
2 4 2
2 /
2

+ + = + + =
+
|
.
|

\
|
+
=
+ =
+
=
=
b b b V
V V V
V
V V
V
V V V V
V
V
V
r
r r r
r
r r
out
r r r r
out
r
out
Charge redistribution architecture
Example: 101
V
out
= 0
( )
3 2 1
12 2 . 0 2 . 1
8
0
2 2
0
4
0
4 2
0 2 /
2

+ + = + + =
+
|
.
|

\
|
+
=
+ =
+
=
=
r
r r
r
r
out
r r
out
r
out
V
V V
V
V
V
V V
V
V
V
V
r
V
r
/2
V
out
= V
r
/2
oV
V
out
= (V
r
/4+Vr)/2 V
out
= V
r
/4
Pipelined DAC architecture
Block diagram of commercial D/A converters
Performance characteristics of D/A converters
1. Resolution --- V
r
/2
N
2. Accuracy
3. Offset error
4. Gain error
(a) Differential non-linearity (DNL) error
(b) Integral nonlinearity (INL) error
5. Settling time
6. Dynamic range
7. Power supply rejection ratio
8. Drift