Layout

ELE704/EE8502 Analog CMOS Integrated Circuits
MOS Device Layout Techniques
Fei Yuan, PhD. PEng.

Department of Electrical & Computer Engineering
Ryerson University
Toronto, Ontario, Canada
Copyright (c) Fei Yuan 2010
Copyright (c) F. Yuan 2010
(1)
Preface
This tutorial covers the fundamentals of CMOS device layout techniques, including process design
rules, MOS devices (resistors, capacitors, and transistors) and the layout of MOS devices. Materials
of this tutorial are drawn from various published texts, lecture notes, and research papers. Please
report any error to Prof. F. Yuan at @ee.ryerson.ca.
(2)
Table of Contents
Process Design Rules
Layout of Resistors
Layout of Capacitors
Layout of MOS Transistors
References
(3)
Process Design Rules

Minimum Width Rules
Minimum Space Rules
Minimum Extension Rules
Overlap Rules
(4)
Minimum Width Rules

The minimum width of polygon denes the limits of a fabrication
process.
A violation of the minimum width rules potentially results in an
open circuit in the oending layer.
An open circuit may be created during fabrication.
A narrow path may be created during fabrication - large currents
passing through a narrow path cause the path to act like a fuse.
Figure 1: Design rule - min. width
(5)
Minimum Space Rules
Figure 2: Design rule - min. space
To avoid an unwanted short circuit between two polygons during

fabrication, S1 > Smin , where Smin is set by process.
(6)
Minimum Extension Rules
Figure 3: Design rule - min. extension
Some geometries must extend beyond the edge of others by a

minimum value.
Typical example - gate poly must have a minimum extension beyond
the active area to ensure proper transistor action at the edge.
(7)
Overlap Rules
Apply to polygons on dierent layers.
Misalignment between polygons may result in either unwanted open
or short circuit connections.
Figure 4: Design rule - overlap
(8)
Layout of Resistors
Poly Resistors
Silicided poly resistors
Non-silicided poly resistors
Diusion Resistors
Layout of Resistors
Layout of Standard Resistors
Layout of Shielded Resistors
Layout of Matched Resistors
Layout of Large Resistors
(9)
Silicided Poly Resistors

Silicide
Silicidated poly
111
000
111
000
111
000
Metal1
111
000
111
000
111
000
Metal contacts
Silicide
111
000
111
000
111
000
111
000
111
000
SiO2
111
000
111
000
111
000
111
000
111
000
H
SiO2
Solicidated poly
psubstrate
Figure 5: Silicided poly resistor
Poly in standard digital CMOS processes is silicided to reduce sheet

resistance. Typical sheet resistance : from 1 2 per unit
area.(Typical 0.18 CMOS processes : R2 8/2 with error 30%).
R = R2 (L/W ) + 2Rc , where Rc =contact resistance.
Error : 100 200 % (Typical 0.18 CMOS processes : 30%). If
silicided poly resistors are used, care should be taken for the
parasitic resistance of metal wires and contacts (Typical 0.18
CMOS processes : 0.07/2 for Metal layers. 8/contact, and
2.5/Via).
(10)
Non-Silicided Poly Resistors

Silicide
Nonsilicidated poly
111
000
111
000
111
000
Metal1
111
000
111
000
111
000
Metal contacts
Silicide
111
000
111
000
111
000
111
000
111
000
111
000
SiO2
111
000
111
000
111
000
111
000
111
000
111
000
H
SiO2
Nonsilicidated poly
psubstrate
Figure 6: Non-silicided poly resistor
R = R2 (L/W ), where R2 =sheet resistance. Sheet resistance : from

50 to few hundred ohms per unit area . Error : 20 %. (Typical
0.18 CMOS processes: R2 3410/2 with error 15%).
Small parasitic capacitances to substrate.
Superior linearity.
High cost due to the extra mask needed to block silicide layer.
(11)
Diusion Resistors
n-well Resistors
Metal contacts
Silicide
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
SiO2
n+
111
000
111
000
111
000
111
000
111
000
111
000
n+
nwell
psubstrate
nwell
W
n+diffusion
L
Figure 7: Structure of n-well resistors
Sheet resistance : 1k per unit area (500/2 with error 30% for
typical 0.18 CMOS processes).
Large error : 40% (30 % for typical 0.18 CMOS processes).
Used only if absolute value is not critical.
Large parasitic capacitance between n-well and substrate.
Resistance is strongly voltage-dependent and highly nonlinear.
(12)
Diusion Resistors (contd)

Parasitic Capacitances
111
000
111
000
111
000
111
000
111
000
111
000
SiO2
n+
Depletion
regions
111
000
111
000
111
000
111
000
111
000
111
000
n+
psubstrate
nwell
junction cap.
Figure 8: Capacitance of n-well resistors
A large parasitic capacitance to the substrate - nonlinear

voltage-dependent junction capacitor
CJ =
CJo
1+
(1)
VR
where VR = reverse biasing voltage of the junction, =built-in

potential of the junction, CJo =junction capacitance at zero reverse
biasing voltage.
n-well resistors are quite noisy since (i) all disturbances/noise from
substrate can be coupled directly onto the resistors and (ii) when a
time-varying current ows through a n-well resistor, it interacts
with the substrate via the parasitic junction capacitance between
the n-well and the substrate.
(13)

Voltage Dependence
Crosssection area varies with

terminal voltages
V <V
A
111
000B
111
000
111
000
111
000
A
111
000
111
000
n+
Narrow depletion
regions
V =V
B
111
000 DD
111
000
111
000
111
000
B
111
000
111
000
11
00
11
00
11
00
11
00
n+
Wide depletion
region
psubstrate
Figure 9: Voltage-dependence of the resistance of n-well resistors
Depletion width varies with terminal voltages.
xn
x
p
2 VR +
q ND (1 + ND
NA
2 VR +
q NA (1+ NA
N
(2)
The cross-section area varies with terminal voltages - resistance is

terminal voltage-dependent.
(14)

Width Dependence
Depletion region
Wd
Depletion region
Wd
Weff
W1
Weff
A
W2
B
Wd
Wd
R
800
600
width (um)
Figure 10: Width-dependence of the resistance of n-well resistors
To reduce the voltage dependence of resistance, the width of the

resistors should not be made too small.
Normalized resistance error :
Ref f,1
1
=
R1
1 2 Wd
W1
Ref f,2
1
R
1 2 Wd
2
W2
f,1
Since W1 > W2, Ref1 >
R
(3)
Ref f,2
.
R2
(15)
Wide resistors are less aected by terminal voltages lower

nonlinearity.
Typical 0.18 1P6M+silicide 1.8V CMOS processes require
W > 2.0m.
(16)
Layout of Resistors
Standard Resistors
45
45
1. Resistance at the corners cannot extimated accurately

2. Current flow at the corner is not uniform
Metal1
Recommended resistor layout
Figure 11: Standard layout of resistors
Avoid 90 degree angle. 45 degree is recommended.
(17)
Layout of Resistors (contd)

Shielded Resistors
VSS
R
S
Shielding resistors
Figure 12: Layout of shielded resistors (S = shielding resistors)
Shielding resistors are connected to a constant voltage source to

prevent self-coupling of the resistor R/inter-coupling with others.
Widely used in analog/RF design.
Caution - a mutual capacitance between the resistor and its shield
exist.
(18)

Matched Resistors - Inter-Digitized Layout
R1
R2
Dummy
resistor
Dummy
resistor
R1
R2
Figure 13: Layout of matched resistors
Inter-digitized layout minimizes the eect of process variation in

x-direction.
Dummy resistors are added to ensure both resistors have the
exactly same environment - the same approach is also often used for
matching capacitors.
(19)

Matched Resistors with Temperature Consideration
R2 experiences
high temperature
Temperature gradient
R1
R2
Power
devices
Temperature effects on R1 and R2

are identical (ideally)
R1
R2
Figure 14: Layout of matched resistors with temperature consideration
(20)
Layout of Resistors
Standard Resistors (contd)
Figure 15: Standard layout of resistors
(21)

Large Resistors
p+ diffusion
111 1 1
000 0 0
1 1 111
0 0 000
1111111111111111111111
0000000000000000000000
111 1 1
000 0 0
1 1 111
0 0 000
111 1 1
000 0 0
1 1 111
0 0 000
p+
n+diffusion
metal1
p+
nwell
n+
111111111111111111111111
000000000000000000000000
psubstrate
Figure 16: Layout of large resistors
Use n-well resistors for resistors of a large resistance because n-well

resistors have a large sheet resistance).
n-well resistors have strong interaction with substrate aect
neighboring devices.
(22)
Large n-well resistors are usually enclosed by a substrate shielding

ring, also known as guard ring, to isolate the resistors from
neighboring devices.
(23)

Large Resistors (contd)
Figure 17: Layout of large resistors
(24)
Layout of Capacitors
Key Parameters
Linearity
Parasitic capacitance to substrate
Series resistance - resistance of capacitor plates
Capacitance per unit area
Types of IC Capacitors
Poly-diusion capacitors
MOS capacitors
Poly-poly capacitors - not available in standard CMOS processes
Metal-poly capacitors - capacitance is small, area consuming.
Metal-metal capacitors - capacitance is small, area consuming.
(25)
Poly-Diusion Capacitors
Interplate capacitance
111
000
111
000
111
000
111
000
111
000
111
000
111
000
Silicide
111
000
111
000
111
000
111
000
111
000
Poly
SiO2
n+
Depletion
psubstrate
Bottomplate capacitance
Figure 18: Poly-diusion capacitor
Most commonly used, particularly in digitally-oriented CMOS

processes.
Good linearity, C = Co (1 + a1 v + a2 v 2) with a1 = 0.0005/v,
a2 = 0.00005/v2, typically.
Good accuracy (5%).
Nonlinear bottom-plate capacitance.
Bottom-plate parasitic capacitance 20% of inter-plate capacitance.
(26)
MOS Capacitors
Vc
C
Stable capacitance in strong inversion
n+
n+
Inversion layer
psubsteate
0
Vc
Vc
Vt
+
Gate series resistance
n+
n+
C ch
Channel resistance Ron

Ron/2
Ron/2
R on /4
Lumped model of MOS capacitor (neglect series resistance)
Distributed model of MOS capacitor (neglect series resistance)
Figure 19: MOS capacitor
MOS transistors are biased in strong inversion to have a stable

capacitance.
Channel resistance: Ron =
1
1
gon n Cox ( W )(VGS VT )2

L
.
(27)
Channel capacitance :
Cch = Cox(W L)
(4)
.
Intrinsic time constant of MOS capacitors when the lumped model
is used
L2
Ron
n
=
Cch =
4
4n (VGS VT )
(5)
Intrinsic time constant of MOS capacitors when the distributed

model is used
1
L2
n
3 4n (VGS VT )
(6)
Reducing Ln increases Minimum channel length should be

used.
Non-negligible channel resistance (Ron ) lowers the quality factor (Q)
of the capacitor
Q=
1/C
Power stored
=
Power dissipated
Ron
(28)
Layout of MOS Capacitors

Minimize Gate Series Resistance & Channel
Resistance - Multi-Finger Structure
Gate series resistance
Poly gate
Lmin
Metal1
n+ diffusion
(a) Single finger structure
Large gate series resistance
Large source/substrate & drain/substrate capacitances
Metal1
Poly gate
11111111111111111111111
00000000000000000000000
1 1 1 1 1 1
0 0 0 0 0 0
11111111111111111111111
00000000000000000000000
1 1 1 1 1 1
0 0 0 0 0 0
11111111111111111111111
00000000000000000000000
1 1 1 1 1 1
0 0 0 0 0 0
11111111111111111111111
00000000000000000000000
1 1 1 1 1 1
0 0 0 0 0 0
11111111111111111111111
00000000000000000000000
11111111111111111111111
00000000000000000000000
11111111111111111111111
00000000000000000000000
C
Metal1
Lmin
(b) Multifinger structure
Figure 20: Layout of MOS capacitor
Multi-nger structure minimizes gate series resistance.

Multi-nger structure minimizes source/substrate &
drain/substrate parasitic capacitances.
(29)
Layout of Capacitors (contd)

Matched Capacitors - Minimize the Eect of Oxide
Thickness Gradient - Common Centroid Structure.
C1
11111111111111111
00000000000000000
11111111111111111
00000000000000000
11
00
11
00
11 11 11 11
00 00 00 00
1
0
1
0
1
0
1 11
0 00
1 11
0 00
1
0
1
0
1
0
1
0
1
0
1
0
11 1
00 0
1
0
11 1
00 0
1
0
11 11
00 00
1
0
11 11
00 00
1
0
1 11
0 00
1 11
0 00
1
0
1
0
11 11
00 00
11 11
00 00
1
0
1
0
1
0
11 11
00 00
11 11
00 00
1
0
1
0
1
0
1
0
1
0
11
00
11
00
11
00
11
00
1111111111111111111111
0000000000000000000000
1
0
1
0
1111111111111111111111
0000000000000000000000
1
0
C1
C2
C2
C1
C1
C2
C2
C1
C1
C1
C2
C2
C2
C2
C1
C2
C1
Figure 21: Layout of matched capacitor
Common centroid structure minimizes the eect of oxide thickness

variation in both x and y-directions.
Dummy capacitors are needed to ensure the same environment for
C1 and C2.
(30)

Large Capacitors
1111111111111111111111
0000000000000000000000
1
0
1
0
1111111111111111111111
0000000000000000000000
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 1
0 0
1 1
0 0
1 1
0 0
1
0
1 1
0 0
1
0
1
0
1 1
0 0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1111111111111111111111
0000000000000000000000
1
0
1
0
1111111111111111111111
0000000000000000000000
1
0
dummy cap.
C1
C2
Poly2
C2
C1
Poly1
dummy cap.
n+
nwell
nwell biasing
Figure 22: Layout of large matched capacitor
C1 and C2 are 2-poly capacitors.

n-well is employed as a charge collector to shield the interaction
between the bottom plate and substrate.
n-well is biased at multiple points and connected to a constant
voltage source.
(31)

Matched Capacitors (contd)
Figure 23: Layout of matched capacitor
(32)

Undercut Eect
x
top plate
bottom plate
4C
Perimeter reduction not the same
Same perimeter reduction
Figure 24: Undercut eect
Top plate is smaller than the bottom plate despite their identical
drawn dimensions.
Bottom plate area : A = ab
Top plate area : A A 2(a + b)x = A px, where p=drawn
perimeter.
Because x is xed for a given technology, to get the same area
reduction, the same perimeter reduction is required use
multiple unit caps connected in parallel.
(33)

Criteria for MOS Transistor Layout
Minimize gate series resistance.
Minimize source/drain resistances.
Minimize source/substrate & drain/substrate parasitic
capacitances.
(34)
Layout of MOS Transistors (contd)

Series resistance of drain
D
Poly
G
S
n+diffusion
Series resistance of source
D
G
S
Figure 25: Layout of MOS Transistors
Large gate series resistance (7.82.5/2 for typical 0.18 CMOS

processes).
Large distributed resistance of source/drain (6.82.5/2 for n+
and 7.22.5/2 for p+ in typical 0.18 CMOS processes.
Large source/substrate and drain/substrate parasitic capacitances.
Non-uniform gate/source/drain voltages. Non-uniform current ow
M1 carries the most current and Mn carries the least current).
(35)

Minimize Source/Drain Resistances Multiple
Contacts
Use as many contacts as possible

Metal1
D
G
Poly
Figure 26: Layout of MOS Transistors (multiple contacts at source/drain)
Better contact at source/drain high reliability & smaller

contact resistance (R = Rc /N , where N=number of contacts).
Smaller source/drain resistances (series resistance is negligible but
lateral resistance still exists).
Large source/substrate and drain/substrate parasitic capacitances.
Large gate series resistance.
Gate is too long.
Contacts are not allowed on the gate above the channel (high
temperature required to form contacts may destroy the thin gate
oxide).
(36)

Minimize Source/Substrate and Drain/Substrate
Parasitic Capacitances Multi-Finger Structure
Shared drain
Poly gate
M4
M3
M2
M1
n+ diffusion
D
Shared source
Figure 27: Layout of MOS Transistors (multi-nger structure
Better contact high reliability/smaller contact resistance.

Reduced source/drain resistances.
Reduced source/substrate and drain/substrate parasitic
capacitances (shared sources/drains).
Reduced gate series resistance (multiple gates connected in parallel).
Reduced silicon area.
(37)

Matched MOS Transistors
M1
M2
111111111111111111
000000000000000000
111111111111111111
000000000000000000
111111111111111111
000000000000000000
111111111111111111
000000000000000000
11
00
11
00
11
00
111111111111111111
000000000000000000
111111111
000000000
11
00
11
00
11
00
111111111 111111111111111111
000000000 000000000000000000
111111111
000000000
11
00
11
00
11
00
111111111
000000000
111111111
000000000
11
00
11
00
11
00
11
00
11
00
11
00
111111111
000000000
111111111
000000000
11
00
11
00
11
00
11
00
11
00
11
00
11
00
111111111
000000000
11
00
11
00
11
00
11
00
11
00
11
00
11
00
11
00
11
00
11
00
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S
11
00
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00
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00
11
00
11
00
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00
11
00
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11
00
D
S
D
S
D
11111
00000
11111
00000
11111
00000
11111
00000
11
00
11
00
11
00
11
00
D
S
D
S
11
00
11
00
11
00
11111
00000
11111
00000
11111
00000
11111
00000
11
00
11
00
11
00
11111
00000
11111
00000
11111
00000
11111
00000
11
00
11
00
11
00
11111
00000
11111
00000
11111
00000
11111
00000
11
00
11
00
11
00
11
00
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00
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00
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00
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11
00
111111111111111111111111111
000000000000000000000000000
111111111111111111111111111
000000000000000000000000000
11
00
11
00
11
00
111111111111111111111111111
000000000000000000000000000
111111111111111111111111111
000000000000000000000000000
111111111111111111111111111
000000000000000000000000000
111111111111111111111111111
000000000000000000000000000
G(M1)
D(M2)
M2
M1
M1
M2
M2
M1
M1
M2
M2
M1
111111111111111111
111111111111111111
000000000000000000
D(M1) 000000000000000000
G(M2)
n+ diffusion
Figure 28: Layout of matched MOS Transistors
Matched transistors are used extensively in both analog and digital

CMOS circuits.
Use inter-digitized layout style.
(38)

Matched MOS Transistors (contd)
Figure 29: Layout of matched MOS Transistors
(39)
References
A. Hastings, The Art of Analog Layout, 2nd Ed. Prentice-Hall,
2006.
B. Razavi, Design of Analog CMOS Integrated Circuits,
McGraw-Hill, 2001.
D. Clein, CMOS IC Layout - Concepts, Methodologies, and Tools,
Boston, 1999.
J. Franca and Y. Tsividis, editors, Design of Analog-Digital VLSI
Circuits For Telecommunications and Signal Processing, 2nd Ed.,
Prentice-Hall, 1994.
M. Ismail and T. Fiez editors, Analog VLSI - Signal and
Information Processing, McGraw-Hill, 1994.
(40)

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ELE704/EE8502 Analog CMOS Integrated Circuits

MOS Device Layout Techniques

Fei Yuan, PhD. PEng.

Copyright (c) F. Yuan 2010

Copyright (c) F. Yuan 2010

Copyright (c) F. Yuan 2010

Process Design Rules

Copyright (c) F. Yuan 2010

Minimum Width Rules

Figure 1: Design rule - min. width

Copyright (c) F. Yuan 2010

Minimum Space Rules

Figure 2: Design rule - min. space

To avoid an unwanted short circuit between two polygons during

Copyright (c) F. Yuan 2010

Minimum Extension Rules

Figure 3: Design rule - min. extension

Some geometries must extend beyond the edge of others by a

Copyright (c) F. Yuan 2010

Figure 4: Design rule - overlap

Copyright (c) F. Yuan 2010

Copyright (c) F. Yuan 2010

Silicided Poly Resistors

Figure 5: Silicided poly resistor

Poly in standard digital CMOS processes is silicided to reduce sheet

Non-Silicided Poly Resistors

Figure 6: Non-silicided poly resistor

R = R2 (L/W ), where R2 =sheet resistance. Sheet resistance : from

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Figure 7: Structure of n-well resistors

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Diusion Resistors (contd)

Figure 8: Capacitance of n-well resistors

A large parasitic capacitance to the substrate - nonlinear

where VR = reverse biasing voltage of the junction, =built-in

Diusion Resistors (contd)

Crosssection area varies with

Figure 9: Voltage-dependence of the resistance of n-well resistors

Depletion width varies with terminal voltages.

The cross-section area varies with terminal voltages - resistance is

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Diusion Resistors (contd)

Figure 10: Width-dependence of the resistance of n-well resistors

To reduce the voltage dependence of resistance, the width of the

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Wide resistors are less aected by terminal voltages lower

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1. Resistance at the corners cannot extimated accurately

Recommended resistor layout

Figure 11: Standard layout of resistors

Avoid 90 degree angle. 45 degree is recommended.

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Layout of Resistors (contd)

Shielding resistors are connected to a constant voltage source to

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Layout of Resistors (contd)

Figure 13: Layout of matched resistors

Inter-digitized layout minimizes the eect of process variation in

Copyright (c) F. Yuan 2010