Cdigo VHDL

Entity SUM is
Port ( A1 : in STD_LOGIC ;
B1 : in STD_LOGIC ;
Ao : in STD_LOGIC ;
Bo : in STD_LOGIC ;
R2 : out STD_LOGIC ;
R1 : out STD_LOGIC ;
Ro : out STD_LOGIC) ;
End SUM;

Architecture CALC of SUM is
Component SUMADOR
Port ( A : in STD_LOGIC;
B: in STD_LOGIC;
Cin: in STD_LOGIC;
Cout: out STD_LOGIC;
Suma: out STD_LOGIC);
End component;
Signal S: STD_LOGIC;
Begin
C1: SUMADOR port map (A1, B1,'0', S, R2);
C2: SUMADOR port map (Ao, Bo, S, Ro, R1);
End CALC;
Entity SUMADOR is
Port ( A: in STD_LOGIC;
B: in STD_LOGIC;
Cin: in STD_LOGIC;
Cout: out STD_LOGIC;
Suma: out STD_LOGIC);
End SUMADOR;

Architecture SUM of SUMADOR is

Begin

Cout <= ((Cin AND (A OR B)) OR (A AND B));
Suma<= (B XOR A XOR Cin);

End SUM;


Cdigos de los pines a la Basys2 Spartan-3E FPGA Board

Net "A1" loc="N3";
Net "B1" loc="E2";
Net "Ao" loc="F3";
Net "Bo" loc="G3";
Net "R2" loc="G1";
Net "R1" loc="P4";
Net "Ro" loc="N4";



















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