CircuitDesignandSimulationwithVHDL

2ndedition
VolneiA.Pedroni
MITPress,2010
Bookweb:www.vhdl.us

SamplesofExerciseSolutions
Version3


Coveredexercises:2.1,3.1,3.20,3.30,4.4,4.6,4.8,5.4,5.11,6.1,6.8,6.9,7.3,7.7,8.6,
9.6,10.1,10.11,10.12,11.6,11.15,12.2,12.13,13.5,14.10,15.3,16.3,16.6,17.3

CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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Exercise2.1:Multiplexer

a)Code

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LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY mux I S
PORT (
a, b: I N STD_LOGI C_VECTOR( 7 DOWNTO 0) ;
sel : I N STD_LOGI C_VECTOR( 1 DOWNTO 0) ) ;
x: OUT STD_LOGI C_VECTOR( 7 DOWNTO 0) ) ;
END mux; - - or END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE exampl e OF mux I S
BEGI N
PROCESS ( a, b, sel )
BEGI N
I F ( sel =" 00" ) THEN
x <= " 00000000" ;
ELSI F ( sel =" 01" ) THEN
x <= a;
ELSI F ( sel =" 10" ) THEN
x <= b;
ELSE
x <= " ZZZZZZZZ" ;
END I F;
END PROCESS;
END exampl e; - - or END ARCHI TECTURE;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

b)Comments:
Lines23:Library/packagedeclarations.BecausethetypeSTD_LOGICisemployed,thepackagestd_logic_1164mustbe
included.Theothertwoindispensablelibraries(stdandwork)aremadevisiblebydefault.
Lines510:ENTITY,herenamedmux.
Lines79:Specificationsofallinputandoutputports(alloftypeSTD_LOGIC_VECTORinthisexample).
Lines1227:ARCHITECTURE,herenamedexample.
Lines1426:APROCESSwasemployedtoconstructthecircuit.Itssensitivitylist(line13)containsthesignalsa,b,and
sel,sowheneveroneofthesesignalschangesitsvaluetheprocessisrun.
Lines1625:Intheprocess,theIFstatementwasusedtoimplementthemuxtliplexer,accordingtothetruthtableof
figure2.9.
Lines1,4,11,28:Usedjusttoimprovecodereadability(theselinesseparatethethreefundamentalcodesections).

Exercise3.1:Possibledatatypes#1

s1 <= ' 0' ; - - BI T, STD_( U) LOGI C, CHARACTER
s2 <= ' Z' ; - - STD_LOGI C, CHARACTER
s3 <= TRUE; - - BOOLEAN
s4 <= " 01000" ; - - BI T_VECTOR, STD_( U) LOGI C_VECTOR, ( UN) SI GNED, STRI NG

Exercise3.20:Typeconversionbyspecificfunctions

Figure3.10isveryhelpfultosolvethisexercise.Typecastingwasalsoincludedinsomecases(seefigure3.10ofthe
book).
a)INTEGERtoSLV:Functionconv_std_logic_vector(a,cs),fromthepackagestd_logic_arith.
b)BVtoSLV:Functionto_stdlogicvector(a,cs),fromthepackagestd_logic_1164.
c)SLVtoUNSIGNED:Functionunsigned(a),fromthepackagenumeric_stdorstd_logic_arith.
d)SLVtoINTEGER:Functionconv_integer(a,cs),fromthepackagestd_logic_signedorstd_logic_unsigned,orfunction
to_integer(a,cs),fromnumeric_std_unsigned.
e)SIGNEDtoSLV:Functionstd_logic_vector(a),fromthepackagenumeric_stdorstd_logic_arith,orfunction
conv_std_logic_vector(a,cs)fromstd_logic_arith.
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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Exercise3.30:Illegalassignments#3

a)s4( 0) ( 0) <= s7( 1, 1, 1) ; - - cause 1 ( BI T x STD_LOGI C)
b) s6( 1) <= s4( 1) ; - - cause 2 ( pi l e of BI T_VECTOR x si ngl e BI T_VECTOR)
c)s1 <= " 00000000" ; - - cause 3 ( i ndi vi dual val ues must be TRUE or FALSE)
d)s7( 0) ( 0) ( 0) <= ' Z' ; - - cause 4 ( zer o i s i nval i d i ndex) + cause 3 ( wr ong par ent hesi s)
e)s2( 7 DOWNTO 5) <= s1( 2 DOWNTO 0) ; - - cause 1 ( sl i ce wi t h BI T x sl i ce wi t h BOOLEAN)
f)s4( 1) <= ( OTHERS => ' Z' ) ; - - cause 3 ( ' Z' i s an i nval i d val ue f or BI T)
g)s6( 1, 1) <= s2; - - cause 4 ( cor r ect i ndex i s s6( 1) ( 1) )
h)s2 <= s3( 1) AND s4( 1) ; - - i nval i d oper at or ( f or I NTEGER) + cause 1 ( t ype2 x I NTEGER x BV)
i)s1( 0 TO 1) <= ( FALSE, FALSE) ; - - cause 4 ( i ndex of s1 must be downwar d)
j)s3( 1) <= ( 3, 35, - 8, 97) ; - - cause 2 ( si ngl e I NTEGER x pi l e of I NTEGER)

Exercise4.4:Logicaloperators

a) a( 7 DOWNTO 4) NAND " 0111" " 1100"

b) a( 7 DOWNTO 4) XOR NOT b "1100"
c) " 1111" NOR b " 0000" "0000"
d) b( 2 DOWNTO 0) XNOR "101" " 101"

Exercise4.6:Arithmeticoperators#2

a)x REM y - - = 65 ( 65/ 7) *7 = 2

b)x REM y - - = 65 ( 65/ - 7) *- 7 = 2
c)( x + 2*y) REM y - - = ( 65 + 2*- 7) = 51 51 ( 51/ 7) *7 = 2
d)( x + y) REM x - - = 72 ( 72/ - 7) *- 7 = 2
e)x MOD y - - = x REM y = 2
f)x MOD y - - = ( x REM y) + y = 2 7 = - 5
g)- x MOD y - - = x REM y = - 65 ( - 65/ - 7) *- 7 = - 2
h)ABS( - y) - - = 7

Exercise4.8:Shiftandconcatenationoperators

a) x SLL 3 - - " 010000"
b) x SLA - 2 - - " 111100"
c) x SRA 2 - - " 111100"
d) x ROL 1 - - " 100101"
e) x ROR - 3 - - " 010110"
a) x( 2 DOWNTO 0) & "000" ;
b) x( 5) & x( 5) & x( 5 DOWNTO 2) ;
c) x( 5) & x( 5) & x( 5 DOWNTO 2) ;
d) x( 4 DOWNTO 0) & x( 5) ;
e) x( 2 DOWNTO 0) & x( 5 DOWNTO 3) ;


Exercise5.4:Genericparitygenerator

Noteinthecodebelowtheuseoftherecommendationintroducedinsection7.7.


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ENTI TY par i t y_gener at or I S
GENERI C ( N: I NTEGER : = 8) ; - - number of bi t s
PORT (
x: I N BI T_VECTOR( N- 1 DOWNTO 0) ;
y: OUT BI T_VECTOR( N DOWNTO 0) ) ;
END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE st r uct ur al OF par i t y_gener at or I S
SI GNAL i nt er nal : BI T_VECTOR( N- 1 DOWNTO 0) ;
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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BEGI N
i nt er nal ( 0) <= x( 0) ;
gen: FOR i I N 1 TO N- 1 GENERATE
i nt er nal ( i ) <= i nt er naL( i - 1) XOR x( i ) ;
END GENERATE;
y <= i nt er nal ( N- 1) & x;
END st r uct ur al ;
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Exercise5.11:ArithmeticcircuitwithSTD_LOGIC

Noteinthesolutionbelowtheuseofthesignextensionrecommendationseeninsections3.18and5.7.

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LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
USE i eee. numer i c_st d. al l ;
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ENTI TY adder I S
GENERI C (
N: NATURAL : = 4) ; - - number of bi t s
PORT (
a, b: I N STD_LOGI C_VECTOR( N- 1 DOWNTO 0) ;
ci n: I N STD_LOGI C;
opcode: I N STD_LOGI C_VECTOR( 2 DOWNTO 0) ;
y: OUT STD_LOGI C_VECTOR( N- 1 DOWNTO 0) ;
cout : OUT STD_LOGI C) ;
END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE adder OF adder I S
- - def i ne i nt er nal unsi gned si gnal s:
SI GNAL a_unsi g, b_unsi g: UNSI GNED( N- 1 DOWNTO 0) ;
SI GNAL y_unsi g: UNSI GNED( N DOWNTO 0) ;
- - def i ne i nt er nal si gned si gnal s:
SI GNAL a_si g, b_si g: SI GNED( N- 1 DOWNTO 0) ;
SI GNAL y_si g: SI GNED( N DOWNTO 0) ;
BEGI N
- - conver t i nput s t o unsi gned:
a_unsi g <= unsi gned( a) ;
b_unsi g <= unsi gned( b) ;
- - conver t i nput s t o si gned:
a_si g <= si gned( a) ;
b_si g <= si gned( b) ;
- - i mpl ement ci r cui t and conver t t o st d_l ogi c:
WI TH opcode( 1 DOWNTO 0) SELECT
y_unsi g <= ( ' 0' & a_unsi g) + ( ' 0' & b_unsi g) WHEN " 00" ,
( ' 0' & a_unsi g) - ( ' 0' & b_unsi g) WHEN " 01" ,
( ' 0' & b_unsi g) - ( ' 0' & a_unsi g) WHEN " 10" ,
( ' 0' & a_unsi g) + ( ' 0' & b_unsi g) + ( ' 0' & ci n) WHEN OTHERS;
WI TH opcode( 1 DOWNTO 0) SELECT
y_si g <= ( a_si g( N- 1) & a_si g) + ( b_si g( N- 1) & b_si g) WHEN " 00" ,
( a_si g( N- 1) & a_si g) - ( b_si g( N- 1) & b_si g) WHEN " 01" ,
- ( a_si g( N- 1) & a_si g) + ( b_si g( N- 1) & b_si g) WHEN " 10" ,
( a_si g( N- 1) & a_si g) + ( b_si g( N- 1) & b_si g) + ( ' 0' & ci n) WHEN OTHERS;
WI TH opcode( 2) SELECT
y <= st d_l ogi c_vect or ( y_unsi g( N- 1 DOWNTO 0) ) WHEN ' 0' ,
st d_l ogi c_vect or ( y_si g( N- 1 DOWNTO 0) ) WHEN OTHERS;
WI TH opcode( 2) SELECT
cout <= st d_l ogi c( y_unsi g( N) ) WHEN ' 0' ,
st d_l ogi c( y_si g( N) ) WHEN OTHERS;
END ARCHI TECTURE;
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Exercise6.1:Latchandflipflop

a)Seefigurebelow.

CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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b)VHDLcodeandsimulation:

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LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY exampl e I S
PORT (
d, cl k: I N STD_LOGI C;
q1, q2: OUT STD_LOGI C) ;
END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE exampl e OF exampl e I S
BEGI N
PROCESS( cl k, d)
BEGI N
- - - Lat ch: - - - - - - - -
I F cl k=' 1' THEN
q1 <= d;
END I F;
- - - Fl i p- f l op: - - - -
I F cl k' EVENT AND cl k=' 1' THEN
q2 <= d;
END I F;
END PROCESS;
END ARCHI TECTURE;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Simulationresults:

Exercise6.8:Signalgenerator

Twoadditionalwaveforms(a,b)wereincludedinthefigure.Notethatthereisabigdifferencebetweengeneratinga,b
versusx,y,becauseeachsignalintheformerpairchangesitsstatealwaysatthesameclockedge,soitsresolutionis
oneclockperiod,whileinthelatterpaireachsignalcanchangeatbothclocktransitions,sowitharesolutionequalto
onehalfofaclockperiod(whichisthemaximumresolutionindigitalsystems).Inthecodebelow,firstaandbare
generated,thentriviallogicgatesareemployedtoobtainxandy.Notethatthisimplementationisfreefromglitches
becauseonlytwosignalsenterthegates,andsuchsignalscanneverchangeatthesametime(theyoperateatdifferent
clockedges).


clk
x
y
a
b
clk
d
q
clk
d
q
d q
d q
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ENTI TY si gnal _gener at or I S
PORT (
cl k: I N BI T;
x, y: OUT BI T) ;
END ENTI TY;
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ARCHI TECTURE ar ch OF si gnal _gener at or I S
BEGI N
PROCESS( cl k)
VARI ABLE a, b: BI T;
BEGI N
I F cl k' EVENT AND cl k=' 1' THEN
a : = NOT a;
ELSI F cl k' EVENT AND cl k=' 0' THEN
b : = NOT a;
END I F;
x <= a AND b;
y <= a NOR b;
END PROCESS;
END ARCHI TECTURE;
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Exercise6.9:Switchdebouncer

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USE i eee. st d_l ogi c_1164. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY debouncer I S
GENERI C(
f cl k: NATURAL : = 50; - - cl ock f r eq i n MHz
t wi ndow: NATURAL : = 10) ; - - t i me wi ndow i n ms
PORT (
sw: I N STD_LOGI C;
cl k: I N STD_LOGI C;
deb_sw: BUFFER STD_LOGI C) ;
END ENTI TY;
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ARCHI TECTURE di gi t al _debouncer OF debouncer I S
CONSTANT max: NATURAL : = 1000 * f cl k * t wi ndow;
BEGI N
PROCESS ( cl k)
VARI ABLE count : NATURAL RANGE 0 TO max;
BEGI N
I F ( cl k' EVENT AND cl k=' 1' ) THEN
I F ( deb_sw / = sw) THEN
count : = count + 1;
I F ( count =max) THEN
deb_sw <= sw;
count : = 0;
END I F;
ELSE
count : = 0;
END I F;
END I F;
END PROCESS;
END ARCHI TECTURE;
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Exercise7.3:Latchesandflipflops

(b) Flip-flop with clear (a) Latch with reset (c) Latch with clear
d q
clk
clr
d q
clk
rst
d q
clk
clr
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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Code1:ThisisaDtypelatchwithasynchronousreset(figure(a)above).Notethat,contrarytoflipflop
implementations,dneedstobeinthesensitivitylistbecausethecircuitistransparentduringawholesemiperiodof
theclock,notjustduringtheclocktransition.(Eventhoughthecompilermightunderstand,fromthecontext,thata
latchiswantedevenifdisnotinthesensitivitylist,thatisnotagoodpractice.)

Code2:NowwehaveaDtypeflipflopinsteadofaDtypelatch(notethe'EVENTattribute).Becauseresetisonly
activatedwhena(positive)clockedgeoccurs,itissynchronous;sinceinourcontextanasynchronousresetisanactual
reset,whileasynchronousresetisindeedaclearsignal,thepropercircuitisthatoffigure(b).

Code3:Thisisanexampleofbaddesign.Inprinciple,itseemsthatalatchwithcleariswanted,likethatinfigure(c).
However,becauseonlyclkisinthesensitivitylist,theprocesswillonlyberunwhenclkchanges,whichemulatesthe
behaviorofaflipflop.Insummary,theflipflopoffigure(b)mightbeinferred.

Exercise7.7:Registeredcircuits

a)Codeanalysis:
Code1isa8x1multiplexer(8inputs,1biteach),implementedbyline14,followedbyaonebitregister.Henceonly
oneDFFisneeded.Thecompiledcircuitisshowninfigure(a)below.
Code2istheopposite,thatis,itcontainsaregister(8bits,so8DFFsareneeded,inferredbylines1416)followedby
an8x1mux(line17).Thecompiledcircuitisinfigure(b).
Code3issimilartocode1.Theonlydifferenceisthatnointernalsignalwasusedtoimplementthemultiplexer(itwas
implementeddirectlyinline14).Hencethecircuitisthatoffigure(a),withoneDFF.

b)Compilation:Theinferredcircuitsareinthefigurebelow.

c)Codes1and3implementthesamecircuit.Thehardwaresinferredfromthesetwocodesareexactlythesame,so
fromtheimplementationpointofviewtherearenodifferencesbetweenthem.However,code3ismorecompact
(generallypreferred),whilesomemightfindcode1clearertounderstandthatamux,followedbyaregister,isthe
wantedcircuit.

Exercise8.6:SynchronouscounterwithCOMPONENT

a)Thestandardcellisillustratedonthelefthandsideofthefigureabove.AcorrespondingVHDLcodefollows,using
method1.

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- - - - The component : - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY count er _cel l I S
PORT (
cl k, a, b: I N BI T;
c, q: BUFFER BI T) ;
END ENTI TY;
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'1'
d q
q0
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q1
d q
q2
clk
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b
d q
q
c
c
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ARCHI TECTURE count er _cel l OF count er _cel l I S
SI GNAL d: BI T;
BEGI N
PROCESS ( cl k, a, b)
BEGI N
c <= a AND b;
d <= c XOR q;
I F cl k' EVENT AND cl k=' 1' THEN
q <= d;
END I F;
END PROCESS;
END ARCHI TECTURE;
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- - - - Mai n code: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY N_bi t _count er I S
GENERI C (
N: NATURAL : = 4) ; - - number of bi t s
PORT (
cl k: I N BI T;
q: OUT BI T_VECTOR( 0 TO N- 1) ) ;
END ENTI TY;
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ARCHI TECTURE st r uct ur al OF N_bi t _count er I S
SI GNAL a, b: BI T_VECTOR( 0 TO N) ;
- - component decl ar at i on: - -
COMPONENT count er _cel l I S
PORT (
cl k, a, b: I N BI T;
c, q: BUFFER BI T) ;
END COMPONENT;
BEGI N
a( 0) <=' 1' ;
b( 0) <=' 1' ;
gen: FOR i I N 0 TO N- 1 GENERATE
count er : count er _cel l PORT MAP ( cl k, a( i ) , b( i ) , a( i +1) , b( i +1) ) ;
END GENERATE;
q <= b( 1 TO N) ;
END ARCHI TECTURE;
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b)Havingseenthecodeformethod1,doingitformethod3isstraightforward(seeexample8.4).

Exercise9.6:Functionbcd_to_ssd

Seethefunctioninteger_to_ssdinsection2.5.TheASSERTstatementcanbebasedonthatinexercise9.1.

Exercise10.1:Generationofperiodicstimuli

Allthreesignalsaredepictedinthefigurebelow,followedbyaVHDLcodethatproducesallthree.
NotethattheWAITFORstatementwasusedinthissolution.ThereaderisinvitedtoredoitusingAFTER.Whichis
simplerinthiscase?

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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY st i mul i _gener at or I S
sig1
period=200ns
sig2
period=75ns
y
period=80ns
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE t est bench OF st i mul i _gener at or I S
SI GNAL si g1, si g2, y: STD_LOGI C;
BEGI N
PROCESS
BEGI N
- - si gnal si g1: - -
si g1 <= ' 1' ;
WAI T FOR 25ns;
si g1 <= ' 0' ;
WAI T FOR 50ns;
- - si gnal si g2: - -
si g2 <= ' 1' ;
WAI T FOR 25ns;
si g2 <= ' 0' ;
WAI T FOR 50ns;
si g2 <= ' 1' ;
WAI T FOR 25ns;
si g2 <= ' 0' ;
WAI T FOR 25ns;
si g2 <= ' 1' ;
WAI T FOR 50ns;
si g2 <= ' 0' ;
WAI T FOR 25ns;
- - si gnal y: - -
y <= ' 1' ;
WAI T FOR 20ns;
y <= ' 0' ;
WAI T FOR 10ns;
y <= ' 1' ;
WAI T FOR 10ns;
y <= ' 0' ;
WAI T FOR 40ns;
END PROCESS;
END ARCHI TECTURE;
----------------------------------------------

Exercise10.11:TypeItestbenchforanaddressdecoder

Thesimulationstimuli(enaandaddress)tobeusedinthisexercisearethoseofexample2.4(figure2.7),repeatedin
thefigurebelow.Theexpectedfunctionalresponse(wordline)derivedfromthemisalsoincludedinthefigure.

Acorrespondingdesignfile(address_decoder.vhd)ispresentednext.NoticethatonlySTD_LOGICdata(lines810)was
employed,whichistheindustrystandard.Observealsothatthiscodeistotallygeneric;toimplementanaddress
decoderofanysize,theonlychangeneededisinline7.

Thecircuitcanbedesignedinseveralways.Here,concurrentcode(withGENERATEandWHEN)wasemployed.
Anotheroptioncanbeseeninthesolutionsforthe1
st
editionofthebook.

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- - - - - Desi gn f i l e ( addr ess_decoder . vhd) : - - - - - - - - - - - - - - - - -
LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
USE i eee. st d_l ogi c_unsi gned. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY addr ess_decoder I S
GENERI C (
N: NATURAL : = 3) ; - - number of i nput bi t s
PORT (
ena: STD_LOGI C;
addr ess: I N STD_LOGI C_VECTOR( N- 1 DOWNTO 0) ;
wor dl i ne: OUT STD_LOGI C_VECTOR( 2**N- 1 DOWNTO 0) ) ;
address
ena
wordline
0 0 1 2 3 4 5 6 7 0
T
11111111 11111110 11111101 11111011 11110111 11101111 11011111 10111111 01111111 11111110
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE decoder OF addr ess_decoder I S
SI GNAL addr : NATURAL RANGE 0 TO 2**N- 1;
BEGI N
addr <= CONV_I NTEGER( addr ess) ;
gen: FOR i I N 0 TO 2**N- 1 GENERATE
wor dl i ne( i ) <=' 1' WHEN ena=' 0' ELSE
' 0' WHEN i =addr ELSE
' 1' ;
END GENERATE;
END ARCHI TECTURE;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

VHDLcodeforatypeItestbench(fileaddress_decoder_tb.vhd)isshownnext.Theinputwaveformsarethoseinthe
previousfigure,withT=80ns(line9).Thecodeconstructionissimilartothatseeninsection10.8(example10.4).The
statementinline34guaranteesthatafteracertaintime(800nsinthisexampleseeline10)thesimulationwillend.

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- - - - - Test bench f i l e ( addr ess_decoder _t b. vhd) : - - - - - - - - - - - - - - - - - - - - - - - - - - -
LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
USE i eee. st d_l ogi c_unsi gned. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY addr ess_decoder _t b I S
GENERI C (
N: NATURAL : = 3; - - # of bi t s at i nput
T: TI ME : = 80 ns; - - st i mul us per i od
Tf i nal : TI ME : = 800 ns) ; - - end of si mul at i on t i me
END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE t est bench OF addr ess_decoder _t b I S
- - Si gnal decl ar at i ons: - - - -
SI GNAL ena_t b: STD_LOGI C : = ' 0' ;
SI GNAL addr ess_t b: STD_LOGI C_VECTOR( N- 1 DOWNTO 0) : = ( OTHERS => ' 0' ) ;
SI GNAL wor dl i ne_t b: STD_LOGI C_VECTOR( 2**N- 1 DOWNTO 0) ; - - f r omci r cui t
- - DUT decl ar at i on: - - - - - - - -
COMPONENT addr ess_decoder I S
PORT (
ena: STD_LOGI C;
addr ess: I N STD_LOGI C_VECTOR( N- 1 DOWNTO 0) ;
wor dl i ne: OUT STD_LOGI C_VECTOR( 2**N- 1 DOWNTO 0) ) ;
END COMPONENT;
BEGI N
- - DUT i nst ant i at i on: - - - - - -
dut : addr ess_decoder PORT MAP ( ena_t b, addr ess_t b, wor dl i ne_t b) ;
- - Gener at e enabl e:
ena_t b <= ' 1' AFTER T;
- - Gener at e addr ess: - - - - - - -
PROCESS
BEGI N
WAI T FOR T;
WHI LE NOW<Tf i nal LOOP - - t hi s l oop coul d be uncondi t i onal
WAI T FOR T;
I F ( addr ess_t b < 2**N- 1) THEN
addr ess_t b <= addr ess_t b + 1;
ELSE
addr ess_t b <= ( OTHERS => ' 0' ) ;
END I F;
END LOOP;
END PROCESS;
END ARCHI TECTURE;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Simulationresults(fromModelSim)areshowninthenextfigure.Notethat,beingitatypeI(thereforefunctional)
simulation,therearenopropagationdelaysbetweenthetransitionsofaddress_tbandwordline_tb.Observealsothat
theresultproducedbythecircuit(wordline_tb)doesmatchtheexpectedresult(wordline)showninthepreviousfigure.

CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

11

Exercise10.12:TypeIVtestbenchforanaddressdecoder

Note:Beforeexaminingthissolution,pleasereadtheitemAdditionalDetailsonTypeIVSimulationintheExtra
Materiallinkofthebookwebsite.

Thesimulationstimuli(enaandaddress)tobeusedinthisexercisearethoseofexample2.4(figure2.7),repeatedin
thefigurebelow.Fromthem,theexpectedfunctionalresponse(idealwordline,wl
ideal
)isthatalsoincludedinthefigure,
alreadyseeninthesolutiontoexercise10.11.Thelastwaveform(worstcasewordline,wl
wc
)isthesignalexpectedto
beproducedbythecircuit,whichwillbeusedasareferencetodefinethecomparisonpointsandstabilitytest
intervals.

Thedesignfile(address_decoder.vhd)isthesameseeninthepreviousexercise.Acorrespondingtestbenchfile
(address_decoder_tb.vhd)fortypeIVsimulationispresentedbelow.Themaximumpropagationdelayforthedevice
usedinthisproject(aCycloneIIFPGA,fromAltera,synthesizedwithQuartusII;forXilinxdevices,ISEwouldbethe
naturalchoice)wasapproximately13ns,sot
pmax
=15nswasadopted(line10).Thestimulus(address)periodis80ns
(line9),andbothtimemarginsare1ns(lines1112).Thetotalsimulationtimeis800ns(line13).

Thesimulationprocedureisthatdescribedinchapter10andappendixD(mustincludetheSDFanddelayannotated
files).Seesection10.11andexample10.6foradditionaldetails.

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- - Test bench f i l e ( addr ess_decoder _t b. vhd) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - Not e 1: Because GENERI C par amet er s cannot be passed t o t he . vho f i l e, i f t he val ue of
- - N bel ow must be changed, t hen t he desi gn must be r esynt hesi zed t o get a new . vho f i l e.
LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
USE i eee. st d_l ogi c_ar i t h. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY addr ess_decoder _t b I S
GENERI C (
N: NATURAL : = 3; - - # of bi t s at i nput ( see Not e 1 above)
T: TI ME : = 80 ns; - - st i mul us per i od
t pmax: TI ME : = 15 ns; - - maxi mumpr opagat i on del ay
Tbef or e: TI ME : = 1 ns; - - t i me mar gi n bef or e t r ansi t i on
Taf t er : TI ME : = 1 ns; - - t i me mar gi n af t er t r ansi t i on
Tf i nal : TI ME : = 800 ns) ; - - end of si mul at i on
END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE t est bench OF addr ess_decoder _t b I S
- - Const ant and si gnal decl ar at i ons: - - - - - - - - - -
CONSTANT T1: TI ME : = Tpmax + Taf t er ; - - 16ns
CONSTANT T2: TI ME : = T - T1 - Tbef or e; - - 63ns
SI GNAL ena_t b: STD_LOGI C : = ' 0' ;
SI GNAL addr ess_t b: STD_LOGI C_VECTOR( N- 1 DOWNTO 0) : = ( OTHERS => ' 0' ) ;
SI GNAL wor dl i ne_i deal : STD_LOGI C_VECTOR( 2**N- 1 DOWNTO 0) : = ( OTHERS => ' 1' ) ; - - i deal
SI GNAL wor dl i ne_t b: STD_LOGI C_VECTOR( 2**N- 1 DOWNTO 0) ; - - act ual ci r cui t out put
- - DUT decl ar at i on: - - - - - - - - - - - - - - - - - - - - - - - - - - -
COMPONENT addr ess_decoder I S - - see Not e 1 above
address
ena
wlideal
wlwc
Tafter
tpmax
Tbefore
check stability compare
no-sampling region
0 0 1 2 3 4 5 6 7 0
T
11111111 11111110 11111101 11111011 11110111 11101111 11011111 10111111 01111111 11111110
11111111 11111110 11111101 11111011 11110111 11101111 11011111 10111111 01111111 11111110
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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PORT (
ena: STD_LOGI C;
addr ess: I N STD_LOGI C_VECTOR( N- 1 DOWNTO 0) ;
wor dl i ne: OUT STD_LOGI C_VECTOR( 2**N- 1 DOWNTO 0) ) ;
END COMPONENT;
BEGI N
- - DUT i nst ant i at i on ( see Not e 1 above) : - - - - - -
dut : addr ess_decoder PORT MAP ( ena_t b, addr ess_t b, wor dl i ne_t b) ;
- - Gener at e enabl e: - - - - - - - - - - - - - - - - - - - - - - - - - - -
ena_t b <= ' 1' AFTER T;
- - Gener at e addr ess + expect ed i deal out put : - -
PROCESS
VARI ABLE count : NATURAL RANGE 0 TO 2**N- 1 : = 0;
BEGI N
WAI T FOR T;
WHI LE NOW<Tf i nal LOOP - - t hi s l oop coul d be uncondi t i onal
addr ess_t b <= conv_st d_l ogi c_vect or ( count , N) ;
wor dl i ne_i deal <= ( count =>' 0' , OTHERS=>' 1' ) ;
WAI T FOR T;
I F ( count < 2**N- 1) THEN
count : = count + 1;
ELSE
count : = 0;
END I F;
END LOOP;
END PROCESS;
- - Compar i son + st abi l i t y t est : - - - - - - - - - - - - - - -
PROCESS
BEGI N
I F ( NOW<Tf i nal ) THEN
WAI T FOR T1;
ASSERT ( wor dl i ne_t b=wor dl i ne_i deal )
REPORT " Er r or : Si gnal val ues ar e not equal ! "
SEVERI TY FAI LURE;
WAI T FOR T2;
ASSERT wor dl i ne_t b' STABLE( T2)
REPORT " Er r or : Si gnal i s unst abl e! "
SEVERI TY FAI LURE;
WAI T FOR Tbef or e;
ELSE
ASSERT FALSE
REPORT " END OF SI MULATI ON: No er r or f ound! "
SEVERI TY FAI LURE;
END I F;
END PROCESS;
END ARCHI TECTURE;
-----------------------------------------------------------------

Simulationresultsaredepictedinthefigurebelow.Observethattheactualoutput(wordline_tb)doesexhibit
propagationdelays(oftheorderof13nsforthechosendevice)aftercorrespondingaddress(address_tb)transitions.

Thefollowing(veryimportant)challengesarelefttothereader:
1)Toplaywiththetestbenchfile.Forexample,whathappensifthevalueoft
pmax
isreducedtoavaluebelowtheactual
propagationdelay(say,8ns)?Andwhathappensifline60ischangedtoASSERT wor dl i ne_t b' STABLE( T2 + 5
ns) . . . ?
2)ToincludeintheASSERTstatementsthecodeneededforthesimulatortodisplaythetimevalueandthesignal
valuesincaseanerrorisfound(asinexample10.6).

CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

13
Exercise11.6:Signalgenerator#2

a)Thestatetransitiondiagramisincludedinthefigureabove.A0to39counterwaschosentocontrolthestate
transitions(itcountsfrom0to19inonestate,hence20clockperiods,then0to39intheotherstate,thus40clock
cycles),butrecallthatanycounterwith40stateswoulddo[Pedroni2008].Anotheroptionwouldbetousea60state
counter,whichwouldonlyberesetafterreaching59.AVHDLcodeforthestatemachineshowninthefigureis
presentedbelow.Becausetheoutputcoincideswiththestaterepresentation(thatis,output=pr_state),theoutput
comesdirectlyfromaflipflop,sothecircuitisautomaticallyglitchfree.(Suggestion:toeasetheinspectionofthe
simulationresultsuse2and4insteadof20and40forthegenericparametersPulsesLowandPulsesHigh,respectively.)


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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY si gnal _gener at or I S
GENERI C (
Pul sesLow: NATURAL : = 20; - - t i me i n st at e Out put Low
Pul sesHi gh: NATURAL : = 40) ; - - t i me i n st at e Out put Hi gh
PORT (
cl k, r st : I N BI T;
out put : OUT BI T) ;
END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE f smOF si gnal _gener at or I S
TYPE st at e I S ( Out put Low, Out put Hi gh) ;
SI GNAL pr _st at e, nx_st at e: st at e;
SI GNAL number _of _pul ses: NATURAL RANGE 0 TO Pul sesHi gh;
BEGI N
- - - - Lower sect i on of FSM: - - - - - - - - - - -
PROCESS ( r st , cl k)
VARI ABLE count : NATURAL RANGE 0 TO Pul sesHi gh;
BEGI N
I F ( r st =' 1' ) THEN
pr _st at e <= Out put Low;
ELSI F ( cl k' EVENT AND cl k=' 1' ) THEN
count : = count + 1;
I F ( count =number _of _pul ses) THEN
count : = 0;
pr _st at e <= nx_st at e;
END I F;
END I F;
END PROCESS;
- - - - Upper sect i on of FSM: - - - - - - - - - - -
PROCESS ( pr _st at e)
BEGI N
CASE pr _st at e I S
WHEN Out put Low =>
out put <= ' 0' ;
number _of _pul ses <= Pul sesLow;
nx_st at e <= Out put Hi gh;
WHEN Out put Hi gh =>
out put <= ' 1' ;
number _of _pul ses <= Pul sesHi gh;
nx_st at e <= Out put Low;
END CASE;
END PROCESS;
END ARCHI TECTURE;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Exercise11.15:FSMwithembeddedtimer#2

Firstweneedtoclarifythediagramabove.Therearetwooptionsforthetimedtransitions(BCandCA).TakingtheBC
transition,forexample,thespecificationscanbetheasfollows.
clk
output
20 T0
40 T0
T=60T0
cont=19
cont=39
cont<19 cont<39
OutputLow
(output=0)
OutputHigh
(output=1)
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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i)Themachinemuststaytime1secondsinBandthenevaluatex;ifx=2afterthattimeinterval,thenthemachinemust
proceedtostateC.
ii)Thevalueofxmustbex=2foratleasttime1seconds;therefore,ifxchangesitsvaluebeforetime1hasbeen
completed,thetimecountingmustrestart.
Bothoptionscanoccur,dependingontheapplication.Inthepresentsolution,wewillconsiderthatcase(ii)iswanted.
AcorrespondingVHDLcodefollows.Notethatbecausethepr_state<=nx_state;assignmentonlyoccurswhenall
conditionsaremet,thereisnoneedforspecifyingothernextstatesbesidestheactualnextstateineachstate
specifications(thatis,instateA,theonlypossiblenextstateisB;inB,itisC;andinC,itisA).

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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY f smI S
GENERI C (
t i me1: NATURAL : = 3; - - # of cl ock per i ods i n B
t i me2: NATURAL : = 4) ; - - # of cl ock per i ods i n C
PORT (
cl k, r st : I N STD_LOGI C;
x: I N NATURAL RANGE 0 TO 3;
y: OUT STD_LOGI C) ;
END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE f smOF f smI S
TYPE st at e I S ( A, B, C) ;
SI GNAL pr _st at e, nx_st at e: st at e;
ATTRI BUTE enum_encodi ng: STRI NG;
ATTRI BUTE enum_encodi ng OF st at e: TYPE I S " sequent i al " ;
SI GNAL T: NATURAL RANGE 0 TO t i me2;
SI GNAL i nput 1, i nput 2: NATURAL RANGE x' RANGE;
BEGI N
- - - - Lower sect i on of FSM: - - - - - - - - -
PROCESS ( r st , cl k)
VARI ABLE count : NATURAL RANGE 0 TO t i me2;
BEGI N
I F ( r st =' 1' ) THEN
pr _st at e <= A;
ELSI F ( cl k' EVENT AND cl k=' 1' ) THEN
I F ( x=i nput 1 OR x=i nput 2) THEN
count : = count + 1;
I F ( count =T) THEN
count : = 0;
pr _st at e <= nx_st at e;
END I F;
ELSE
count : = 0;
END I F;
END I F;
END PROCESS;
- - - - Upper sect i on of FSM: - - - - - - - - -
PROCESS ( pr _st at e, x)
BEGI N
CASE pr _st at e I S
WHEN A =>
y <= ' 1' ;
T <= 1;
i nput 1<=0; i nput 2<=1;
nx_st at e <= B;
WHEN B =>
y <= ' 0' ;
T <= t i me1;
i nput 1<=2; i nput 2<=2;
nx_st at e <= C;
WHEN C =>
y <= ' 1' ;
T <= t i me2;
i nput 1<=3; i nput 2<=3;
nx_st at e <= A;
END CASE;
END PROCESS;
END ARCHI TECTURE;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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Theviewproducedbythestatemachineviewer(withtheenum_encodingattributecommentedout)isshownbelow.

Simulationresults:

Exercise12.2:CounterwithLCDdisplay

AVHDLcodeforthisproblemispresentedbelow.Thecodefortheup/downcounter,with0.5secondsineachstate,is
shownexplicitly,whilethepartsalreadyseeninexamplesinthebookarejustindicated.Theclockfrequency(entered
asagenericparameter)wasassumedtobe50MHz.(Suggestion:Seefirstthedesigninsection12.2.)

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- - - - - Package wi t h f unct i on: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
PACKAGE my_f unct i ons I S
FUNCTI ON i nt eger _t o_l cd ( SI GNAL i nput : NATURAL) RETURN STD_LOGI C_VECTOR;
. . . ( i nser t f unct i on i nt eger _t o_l cd seen i n sec. 12. 2)
END my_f unct i ons;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - Mai n code: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
USE wor k. my_f unct i ons. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY count er _wi t h_LCD I S
GENERI C (
f cl k: POSI TI VE : = 50_000_000; - - cl ock f r equency ( 50MHz)
cl k_di vi der : POSI TI VE : = 50_000) ; - - f or LCD cl ock ( 500Hz)
PORT (
cl k, r st , up: I N STD_LOGI C;
RS, RW, LCD_ON, BKL_ON: OUT STD_LOGI C;
E: BUFFER STD_LOGI C;
DB: OUT STD_LOGI C_VECTOR( 7 DOWNTO 0) ) ;
END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE count er _wi t h_LCD OF count er _wi t h_LCD I S
TYPE st at e I S ( Funct i onSet 1, Funct i onSet 2, Funct i onSet 3, Funct i onSet 4,
Cl ear Di spl ay, Di spl ayCont r ol , Ent r yMode, Wr i t eDat a, Ret ur nHome) ;
SI GNAL pr _st at e, nx_st at e: st at e;
SI GNAL count er _out put : NATURAL RANGE 0 TO 15;
SI GNAL l cd_i nput : STD_LOGI C_VECTOR( 7 DOWNTO 0) ;
BEGI N
- - - - - Count er ( up/ down, 0. 5s per st at e) : - - - - -
PROCESS ( cl k, r st , up)
VARI ABLE count er 1: I NTEGER RANGE 0 TO f cl k/ 2;
VARI ABLE count er 2: I NTEGER RANGE 0 TO 15;
BEGI N
I F ( r st =' 1' ) THEN
count er 1 : = 0;
I F ( up=' 1' ) THEN count er 2 : = 0;
ELSE count er 2 : = 15;
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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END I F;
ELSI F ( cl k' EVENT AND cl k=' 1' ) THEN
I F ( up=' 1' ) THEN
I F ( count er 2 / = 15) THEN
count er 1 : = count er 1 + 1;
I F ( count er 1=f cl k/ 2) THEN
count er 1 : = 0;
count er 2 : = count er 2 + 1;
END I F;
END I F;
ELSE
I F ( count er 2 / = 0) THEN
count er 1 : = count er 1 + 1;
I F ( count er 1=f cl k/ 2) THEN
count er 1 : = 0;
count er 2 : = count er 2 - 1;
END I F;
END I F;
END I F;
END I F;
count er _out put <= count er 2;
END PROCESS;
- - - - - LCD dr i ver [ Pedr oni 2008] : - - - - - - - - - -
l cd_i nput <= i nt eger _t o_l cd( count er _out put ) ;
LCD_ON <= ' 1' ; BKL_ON <= ' 1' ;
PROCESS ( cl k)
. . . ( i nser t code f or LCD dr i ver seen i n sec. 12. 2)
END PROCESS;
END ARCHI TECTURE;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Exercise12.13:FrequencymeterwithGraycounter

Thesubjectofthisexerciseistheveryinterestingandimportantissueofclockdomaincrossing.Onlyabriefvisittothe
subjectispresentedhere,withthehelpofthefigurebelow.

Figure(a)showstwointerconnecteddomains.Theyoperatewithdistinct(asynchronouswithrespecttoeachother)
clocks,calledclk1andclk2.Theproblemthatmightoccuristheoccurrenceofapositiveedgeinclk2whiletheoutput
ofDFF1(q1)ischangingitsvalue;insuchacase,becausethesetup/holdtimesofDFF2arenotrespected,ametastable
state(astatebetween0and1,whichnormallytakesarelativelylongtimetosettle)canoccurattheoutputofDFF2
(dataoutput)

Thesimplestsynchronizerforclockdomaincrossingisdepictedinfigure(b);itconsistssimplyinaddingaregistertothe
originalcircuit,sothesignal(data)isnotreceivedwithmetastablestatesdownstream.Anotheralternativeisdepicted
in(c),whichisadequateforthecasewhendataistheoutputofacounter.Becauseinagraycounter[Pedroni2008]
onlyonebitchangesatatime,ifclk2activatestheregisterwhileitischangingitsvalue(thatis,whenthischange
clock domain 1 clock domain 2
d1 q1
cross
over
data
d3 q3 d2 q2
clk1
data
clk2
clock domain 1 clock domain 2
d1 q1
cross
over
data
d2 q2
clk1
clk2
clock domain 1 clock domain 2
gray
counter
cross
over
data
d q
register
clock domain 1
gray
counter
cross
over
clock domain 2
data
d3 q3 d2 q2 q1
(a) (b)
(c) (d)
clk2
clk1
clk2
clk1
data
q1
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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occursduringthesetup+holdtimesoftheregister),atmostonebitwillbestoredwithincorrectvalue,sotheoutput
cannotbemorethanoneunitofftheactualvalue.This,however,doesnotpreventtheregisterfromproducinga
metastablestate,whichcanbecleanedusingthesamearrangementoffigure(b),thusresultingthecombined
implementationoffigure(d).

Intermsofhardwareusage,thesolutionwithasimplesynchronizer(figure(b))requiresjustanextraregister(thatis,N
flipflops,whereNisthenumberofbitsindata),whilethesolutionwithjustagraycounter(figure(c))doesnotrequire
additionalflipflops,butdoesrequireadditionalcombinationallogic(whichalsogrowswithN).Obviously,themore
completesolution(figure(d))requiresthesumofboth.

Astraightforwardimplementationforagraycounteristoimplementaregularsequentialcounterthenconvertits
outputtograycodeusingtheequationsbelow,wherebistheoutputfromthebinarycounterandgisthe
correspondinggrayrepresentation:
g(N1)=b(N1)
g(i)=b(i)b(i+1)fori=0,1,...,N2

Acorrespondingcircuitisshowninthefigurebelow(forN=4).

Iftheapproachaboveisusedtoimplementthegraycounteroffigure(c),itrequiresN1twoinputXORgatesin
additiontothehardwarerequiredbytheregularcounter,whiletheregisterbasedsynchronizeroffigure(b)requiresN
flipflopsinadditiontotheregularimplementationoffigure(a).Thecombined(recommended)implementation(figure
(d))thenrequirestheinclusionofN1XORgatesandNflipflops.

Exercise13.5:ROMimplementedwithaHEXfile#1

Theonlychangesneededinthecodeofsection13.4,whichemployedCONSTANTtoimplementtheROM,areinthe
architecturedeclarations,replacingtheoriginaltextwiththatbelow:

ARCHI TECTURE r omOF r om_wi t h_hex_f i l e I S

SI GNAL r eg_addr ess: I NTEGER RANGE 0 TO 15;
TYPE memor y I S ARRAY ( 0 TO 15) OF STD_LOGI C_VECTOR( 7 DOWNTO 0) ;
SI GNAL myr om: memor y;
ATTRI BUTE r am_i ni t _f i l e: STRI NG;
ATTRI BUTE r am_i ni t _f i l e OF myr om: SI GNAL I S " r om_cont ent s. hex" ;
BEGI N

Remembertocreateaplaintextfilewiththecontentsbelow(seetheconstructionofMIFfilesinsection13.3),saved
withthenamerom_contents.hexintheworkdirectory:

: 10 0000 00 00 00 FF 1A 05 50 B0 00 00 00 00 00 00 00 00 11 C1
: 00 0000 01 FF

Exercise14.10:I
2
CinterfaceforanRTC

Note:Beforeexaminingthissolution,pleasereadthetopicAdditionalDetailsontheI
2
CInterfaceintheExtra
Materialpartofthebookwebsite.

PCF8563,PCF8573,PCF8583,andPCF8593arepartoftheNXPfamilyofRTC(realtimeclock)devices.Foravailability
reasons,theRTCemployedinthissolutionwasPFC8593,whichisanRTCwithclock/calendarplustimer/alarmoptions.
clk
binary
counter
b3

b2

b1

b0
g3

g2

g1

g0
gray
output
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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Theclock/calendarfeatureswereexploredinthisdesign,whicharesetusingthefirsteightmemorybytes,shownin
figure1.

Figure1.FirsteightbytesofthePCF8593register.

IntheVHDLcode,theeightregistersabove(addressesfrom0to7)werefilledwiththefollowingvalues:
Control:00000000
Subseconds:00000000(0.00seconds)
Seconds:00000000(00seconds)
Minutes:00110000(30minutes)
Hours:00010100(14hours,24houroptionchosen)
Year/date:00000001(day01)
Weekday/month:00010001(month11=November)
Timer:00000000

Thesetupfortheexperimentsisshowninfigure2.

Figure2.Setupfortheexperiments.

VHDLcodeforthisexerciseispresentednext.Notethatdatawaswrittentoall8RTCregistersoffigure1,butonly
informationregardingseconds,minutes,andhourswasretrieved,whichillustratestheuseofdifferentstarting
addressesforwritingandreading.Notealsothattheinitialtime(14:30:00HH/MM/SS)wasenteredusingGENERIC,but
severalotherpossibilitiesexist.Finally,observethattheclockingschemeissimilartothatinsection14.4ofthebook,
butthatinAdditionalDetailsontheI
2
CInterfaceintheExtraMaterialpartofthebookwebsitewouldalsodo.

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- - - - Package wi t h a f unct i on: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
PACKAGE my_f unct i ons I S
FUNCTI ON bi n_t o_ssd ( CONSTANT i nput : STD_LOGI C_VECTOR) RETURN STD_LOGI C_VECTOR;
END my_f unct i ons;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
clk
rst
rd
wr
5V
10
k
5V
10
k
hours minutes seconds
FPGA
SCL
SDA
GND
MASTER
ssd_10hour(6:0)
ssd_hour(6:0)
ssd_10min(6:0)
ssd_min(6:0)
ssd_10sec(6:0)
ssd_sec(6:0)
PCF
8593
SLAVE
chip_rst
ack_error GND
chip_rst
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SCL
SDA
5V
32.768 kHz
crystal
PCF
8593
GND
interrupt
Registername Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Control 0 RTCsetup
Subseconds 1 1/10sec 1/100sec
Seconds 2 10sec sec
Minutes 3 10min min
Hours 4 AM/
PM
12/
24
10hour hour
Year/Date 5 year 10date date
Weekday/Month 6 weekday 10mo month
Timer 7 Timersetup
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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PACKAGE BODY my_f unct i ons I S
FUNCTI ON bi n_t o_ssd ( CONSTANT i nput : STD_LOGI C_VECTOR) RETURN STD_LOGI C_VECTOR I S
VARI ABLE out put : STD_LOGI C_VECTOR( 6 DOWNTO 0) ;
BEGI N
CASE i nput I S
WHEN " 0000" => out put : =" 0000001" ; - - " 0" on SSD
WHEN " 0001" => out put : =" 1001111" ; - - " 1" on SSD
WHEN " 0010" => out put : =" 0010010" ; - - " 2" on SSD
WHEN " 0011" => out put : =" 0000110" ; - - " 3" on SSD
WHEN " 0100" => out put : =" 1001100" ; - - " 4" on SSD
WHEN " 0101" => out put : =" 0100100" ; - - " 5" on SSD
WHEN " 0110" => out put : =" 0100000" ; - - " 6" on SSD
WHEN " 0111" => out put : =" 0001111" ; - - " 7" on SSD
WHEN " 1000" => out put : =" 0000000" ; - - " 8" on SSD
WHEN " 1001" => out put : =" 0000100" ; - - " 9" on SSD
WHEN " 1010" => out put : =" 0001000" ; - - " A" on SSD
WHEN " 1011" => out put : =" 1100000" ; - - " b" on SSD
WHEN " 1100" => out put : =" 0110001" ; - - " C" on SSD
WHEN " 1101" => out put : =" 1000010" ; - - " d" on SSD
WHEN " 1110" => out put : =" 0110000" ; - - " E" on SSD
WHEN OTHERS => out put : =" 0111000" ; - - " F" on SSD
END CASE;
RETURN out put ;
END bi n_t o_ssd;
END PACKAGE BODY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


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- - - - Mai n code: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
USE wor k. my_f unct i ons. al l ; - - package wi t h " i nt eger _t o_ssd" f unct i on.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY r t c_i 2c I S
GENERI C (
- - Syst empar ament er s:
f cl k: POSI TI VE : = 50_000; - - Fr eq. of syst emcl ock ( i n kHz)
dat a_r at e: POSI TI VE : = 100; - - Desi r ed I 2C bus speed ( i n kbps)
sl ave_addr _f or _wr i t e: STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 10100010" ;
sl ave_addr _f or _r ead: STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 10100011" ;
i ni t i al _addr ess_wr : STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 00000000" ;
i ni t i al _addr ess_r d: STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 00000010" ;
- - Val ues t o st or e i n t he RTC memor y ( cl ock/ cal endar set t i ngs) :
set _cont r ol : STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 00000000" ;
set _subsec: STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 00000000" ; - - 0. 00 sec
set _sec: STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 00000000" ; - - 00 sec
set _mi n: STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 00110000" ; - - 30 mi n
set _hour : STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 00010100" ; - - 14 h
set _dat e: STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 00000001" ; - - 01 day
set _mont h: STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 00010001" ; - - 11 November
set _t i mer : STD_LOGI C_VECTOR( 7 DOWNTO 0) : = " 00000000" ) ;
PORT (
- - Cl ock and cont r ol si gnal s:
cl k, r st , wr , r d: I N STD_LOGI C;
- - I 2C si gnal s:
SCL: OUT STD_LOGI C;
SDA: I NOUT STD_LOGI C;
- - Syst emout put s ( t o SSD di spl ays) :
chi p_r st : OUT STD_LOGI C;
ssd_sec: OUT STD_LOGI C_VECTOR( 6 DOWNTO 0) ; - - uni t s of seconds
ssd_10sec: OUT STD_LOGI C_VECTOR( 6 DOWNTO 0) ; - - t ens of seconds
ssd_mi n: OUT STD_LOGI C_VECTOR( 6 DOWNTO 0) ; - - uni t s of mi nut es
ssd_10mi n: OUT STD_LOGI C_VECTOR( 6 DOWNTO 0) ; - - t ens of mi nut es
ssd_hour : OUT STD_LOGI C_VECTOR( 6 DOWNTO 0) ; - - uni t s of hour s
ssd_10hour : OUT STD_LOGI C_VECTOR( 6 DOWNTO 0) ; - - t ens of hour s
ack_er r or : OUT STD_LOGI C) ; - - t o an LED
END ENTI TY;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE f smOF r t c_i 2c I S
- - Gener al si gnal s:
CONSTANT di vi der : I NTEGER : = ( f cl k/ 8) / dat a_r at e;
SI GNAL t i mer : NATURAL RANGE 0 TO 8;
SI GNAL aux_cl k, bus_cl k, dat a_cl k: STD_LOGI C;
SI GNAL wr _f l ag, r d_f l ag: STD_LOGI C;
SI GNAL sec: STD_LOGI C_VECTOR( 7 DOWNTO 0) ;
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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SI GNAL mi n: STD_LOGI C_VECTOR( 7 DOWNTO 0) ;
SI GNAL hour : STD_LOGI C_VECTOR( 7 DOWNTO 0) ;
SHARED VARI ABLE i : NATURAL RANGE 0 TO 7 : = 0;
- - St at e- machi ne si gnal s:
TYPE st at e I S (
- - Common wr i t e+r ead st at es:
i dl e, st ar t _wr , sl ave_addr _wr , ack1, st op,
- - Wr i t e- onl y st at es:
i ni t i al _addr _wr , ack2, wr _cont r ol , ack3, wr _subsec, ack4, wr _sec, ack5, wr _mi n, ack6,
wr _hour , ack7, wr _dat e, ack8, wr _mont h, ack9, wr _t i mer , ack10,
- - Read- onl y st at es:
i ni t i al _addr _r d, ack11, st ar t _r d, sl ave_addr _r d, ack12, r d_sec, ack13, r d_mi n, ack14,
r d_hour , no_ack) ;
SI GNAL pr _st at e, nx_st at e: st at e;
BEGI N
chi p_r st <= NOT r st ; - - t o r eset t he chi p ( pi n 3)
- - - - - - - Di spl ay si gnal s: - - - - - - - - - - - - - - - - - - - -
ssd_sec <= bi n_t o_ssd( sec( 3 DOWNTO 0) ) ;
ssd_10sec <= bi n_t o_ssd( sec( 7 DOWNTO 4) ) ;
ssd_mi n <= bi n_t o_ssd( mi n( 3 DOWNTO 0) ) ;
ssd_10mi n <= bi n_t o_ssd( mi n( 7 DOWNTO 4) ) ;
ssd_hour <= bi n_t o_ssd( hour ( 3 DOWNTO 0) ) ;
ssd_10hour <= bi n_t o_ssd( " 00" & hour ( 5 DOWNTO 4) ) ;
- - - - - - - Auxi l i ar y cl ock ( 400kHz) : - - - - - - - - - - -
PROCESS ( cl k)
VARI ABLE count 1: I NTEGER RANGE 0 TO di vi der ;
BEGI N
I F ( cl k' EVENT AND cl k=' 1' ) THEN
count 1 : = count 1 + 1;
I F ( count 1=di vi der ) THEN
aux_cl k <= NOT aux_cl k;
count 1 : = 0;
END I F;
END I F;
END PROCESS;
- - - - - - - Bus & dat a cl ocks ( 100kHz) : - - - - - - - - -
PROCESS ( aux_cl k)
VARI ABLE count 2: NATURAL RANGE 0 TO 3;
BEGI N
I F ( aux_cl k' EVENT AND aux_cl k=' 1' ) THEN
count 2 : = count 2 + 1;
I F ( count 2=0) THEN
bus_cl k <= ' 0' ;
ELSI F ( count 2=1) THEN
dat a_cl k <= ' 1' ;
ELSI F ( count 2=2) THEN
bus_cl k <= ' 1' ;
ELSE
dat a_cl k <= ' 0' ;
END I F;
END I F;
END PROCESS;
- - - - - - - Lower sect i on of FSM: - - - - - - - - - - - - - - -
PROCESS ( r st , dat a_cl k)
VARI ABLE er r or _f l ag: STD_LOGI C;
BEGI N
I F ( r st =' 1' ) THEN
pr _st at e <= i dl e;
wr _f l ag <= ' 0' ;
r d_f l ag <= ' 0' ;
er r or _f l ag : = ' 0' ;
i : = 0;
- - Ent er dat a f or I 2C bus:
ELSI F ( dat a_cl k' EVENT AND dat a_cl k=' 1' ) THEN
I F ( i =t i mer - 1) THEN
pr _st at e <= nx_st at e;
i : = 0;
ELSE
i : = i + 1;
END I F;
ELSI F ( dat a_cl k' EVENT AND dat a_cl k=' 0' ) THEN
- - St or e dat a r ead f r omRTC memor y:
I F ( pr _st at e=r d_sec) THEN
sec( 7- i ) <= SDA;
ELSI F ( pr _st at e=r d_mi n) THEN
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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mi n( 7- i ) <= SDA;
ELSI F ( pr _st at e=r d_hour ) THEN
hour ( 7- i ) <= SDA;
END I F;
- - St or e wr i t e/ r ead/ er r or f l ags:
I F ( pr _st at e=i dl e) THEN
wr _f l ag <= wr ;
r d_f l ag <= r d;
ELSI F ( pr _st at e=st op) THEN
wr _f l ag <= ' 0' ;
r d_f l ag <= ' 0' ;
ELSI F ( pr _st at e=ack1 OR pr _st at e=ack2 OR pr _st at e=ack3 OR pr _st at e=ack4 OR
pr _st at e=ack5 OR pr _st at e=ack6OR pr _st at e=ack7 OR pr _st at e=ack8 OR pr _st at e=ack9
OR pr _st at e=ack10) THEN
er r or _f l ag : = er r or _f l ag OR SDA;
END I F;
END I F;
ack_er r or <= er r or _f l ag;
END PROCESS;
- - - - - - - Upper sect i on of FSM: - - - - - - - - - - - - - - -
PROCESS ( pr _st at e, bus_cl k, dat a_cl k, wr _f l ag, r d_f l ag)
BEGI N
CASE pr _st at e I S
- - common wr i t e- r ead st at es:
WHEN i dl e =>
SCL <= ' 1' ;
SDA <= ' 1' ;
t i mer <= 1;
I F ( wr _f l ag=' 1' OR r d_f l ag=' 1' ) THEN
nx_st at e <= st ar t _wr ;
ELSE
nx_st at e <= i dl e;
END I F;
WHEN st ar t _wr =>
SCL <= ' 1' ;
SDA <= dat a_cl k; - - or ' 0'
t i mer <= 1;
nx_st at e <= sl ave_addr _wr ;
WHEN sl ave_addr _wr =>
SCL <= bus_cl k;
SDA <= sl ave_addr _f or _wr i t e( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack1;
WHEN ack1 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
I F ( wr _f l ag=' 1' ) THEN
nx_st at e <= i ni t i al _addr _wr ;
ELSE
nx_st at e <= i ni t i al _addr _r d;
END I F;
- - dat a- wr i t e st at es:
WHEN i ni t i al _addr _wr =>
SCL <= bus_cl k;
SDA <= i ni t i al _addr ess_wr ( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack2;
WHEN ack2 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= wr _cont r ol ;
WHEN wr _cont r ol =>
SCL <= bus_cl k;
SDA <= set _cont r ol ( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack3;
WHEN ack3 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= wr _subsec;
WHEN wr _subsec =>
SCL <= bus_cl k;
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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SDA <= set _subsec( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack4;
WHEN ack4 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= wr _sec;
WHEN wr _sec =>
SCL <= bus_cl k;
SDA <= set _sec( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack5;
WHEN ack5 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= wr _mi n;
WHEN wr _mi n =>
SCL <= bus_cl k;
SDA <= set _mi n( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack6;
WHEN ack6 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= wr _hour ;
WHEN wr _hour =>
SCL <= bus_cl k;
SDA <= set _hour ( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack7;
WHEN ack7 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= wr _dat e;
WHEN wr _dat e =>
SCL <= bus_cl k;
SDA <= set _dat e( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack8;
WHEN ack8 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= wr _mont h;
WHEN wr _mont h =>
SCL <= bus_cl k;
SDA <= set _mont h( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack9;
WHEN ack9 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= wr _t i mer ;
WHEN wr _t i mer =>
SCL <= bus_cl k;
SDA <= set _t i mer ( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack10;
WHEN ack10 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= st op;
- - dat a- r ead st at es:
WHEN i ni t i al _addr _r d =>
SCL <= bus_cl k;
SDA <= i ni t i al _addr ess_r d( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack11;
WHEN ack11 =>
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SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= st ar t _r d;
WHEN st ar t _r d =>
SCL <= ' 1' ; - - or bus_cl k;
SDA <= dat a_cl k;
t i mer <= 1;
nx_st at e <= sl ave_addr _r d;
WHEN sl ave_addr _r d =>
SCL <= bus_cl k;
SDA <= sl ave_addr _f or _r ead( 7- i ) ;
t i mer <= 8;
nx_st at e <= ack12;
WHEN ack12 =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 1;
nx_st at e <= r d_sec;
WHEN r d_sec =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 8;
nx_st at e <= ack13;
WHEN ack13 =>
SCL <= bus_cl k;
SDA <= ' 0' ;
t i mer <= 1;
nx_st at e <= r d_mi n;
WHEN r d_mi n =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 8;
nx_st at e <= ack14;
WHEN ack14 =>
SCL <= bus_cl k;
SDA <= ' 0' ;
t i mer <= 1;
nx_st at e <= r d_hour ;
WHEN r d_hour =>
SCL <= bus_cl k;
SDA <= ' Z' ;
t i mer <= 8;
nx_st at e <= no_ack;
WHEN no_ack =>
SCL <= bus_cl k;
SDA <= ' 1' ;
t i mer <= 1;
nx_st at e <= st op;
- - Common wr i t e- r ead st at e:
WHEN st op =>
SCL <= bus_cl k;
SDA <= NOT dat a_cl k; - - or ' 0'
t i mer <= 1;
nx_st at e <= i dl e;
END CASE;
END PROCESS;
END ARCHI TECTURE;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Exercise15.3:Imagegenerationwithhardware#2(suninthesky)

Asmentionedabove,amajoradvantageofbreakingthevideointerfacesintostandardandnonstandardparts,asdone
inchapters1517,isthatmostofthedesignstaysalwaysthesame.Tosolvethepresentexercise,weonlyneedto
replacethecodeforPart2(imagegenerator)insection15.9withanewcode,forthenewimage,becausetherest
(controlsignals)remainthesame.Acodethatsolvesthisexerciseisshownbelow(justreplacelines78115ofthecode
insection15.9withthiscode).

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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - Par t 2: I MAGE GENERATOR
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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PROCESS ( pi xel _cl k, Hsync, dena)
VARI ABLE x: NATURAL RANGE 0 TO Hd;
VARI ABLE y: NATURAL RANGE 0 TO Vd;
BEGI N
- - - - Count col umns: - - - - - - - -
I F ( pi xel _cl k' EVENT AND pi xel _cl k=' 1' ) THEN
I F ( Hact i ve=' 1' ) THEN x : = x + 1;
ELSE x : = 0;
END I F;
END I F;
- - - - Count l i nes: - - - - - - - - - -
I F ( Hsync' EVENT AND Hsync=' 1' ) THEN
I F ( Vact i ve=' 1' ) THEN y : = y + 1;
ELSE y : = 0;
END I F;
END I F;
- - Gener at e t he i mage: - - - - -
I F ( dena=' 1' ) THEN
I F ( ( ( x- 320) **2+( y- 240) **2) <14400) THEN
R <= ( OTHERS => ' 1' ) ;
G <= ( OTHERS => ' 1' ) ;
B <= ( OTHERS => ' 0' ) ;
ELSE
R <= ( OTHERS => r ed_swi t ch) ;
G <= ( OTHERS => gr een_swi t ch) ;
B <= ( OTHERS => bl ue_swi t ch) ;
END I F;
ELSE
R <= ( OTHERS => ' 0' ) ;
G <= ( OTHERS => ' 0' ) ;
B <= ( OTHERS => ' 0' ) ;
END I F;
END PROCESS;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Exercise16.3:Imagegenerationwithhardware#2(suninthesky)

Asmentionedabove,thesamecodeusedinsection16.7canbeemployedherebecauseitwasalreadyseparatedinto
standardandnonstandardparts.Takethecodeofsection16.7andreplaceitsPart1(imagegenerator)withacodefor
thenewimage,whichcanbeeasilywrittenbasedonthesolutiontoexercise17.3,shownahead.Recallthatthecircles
centermustbeatthecenterofthescreen,soitscoordinatesmustbeadjustedaccordingwiththeresolutionchosenfor
thedisplay.DonotforgettocreateafileforthePLL(seesections14.2and16.7).

Exercise17.3:Imagegenerationwithhardware#2(suninthesky)

Asseenintheexamplesofchapters1517,amajoradvantageofseparatingthevideointerfaceinstandardandnon
standardpartsisthatmostofthemstayalwaysthesame.Thusthecodeofsection17.4canbeusedhere,replacing
onlyPart1(imagegenerator)withthecodebelow.Obviously,becausetheimagegeneratorisinstantiatedinthemain
code,someadjustmentsmightbeneededinthedeclarationandinstantiationoftheimagegeneratorthere.Recallthat
thescreensizeis600800pixelsandthatthesunsradiusmustbe150pixels(seethefigurebelow).Donotforgetto
createafileforthePLL(seesections14.2and17.4).

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3
- - - - - I mage gener at or : - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
switches
yellow
250 300 250

300

150

150
Sun in the sky(600800)
CircuitDesignandSimulationwithVHDL,2ndedition,VolneiA.Pedroni,MITPress,2010SolutionstoSelectedExercises

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ENTI TY i mage_gener at or I S
PORT (
r ed_swi t ch, gr een_swi t ch, bl ue_swi t ch: I N STD_LOGI C;
cl k50, Hsync, Vsync, Hact i ve, Vact i ve, dena: I N STD_LOGI C;
R, G, B: OUT STD_LOGI C_VECTOR( 5 DOWNTO 0) ) ;
END i mage_gener at or ;
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ARCHI TECTURE i mage_gener at or OF i mage_gener at or I S
BEGI N
PROCESS ( cl k50, Hsync, dena)
VARI ABLE x: I NTEGER RANGE 0 TO 800;
VARI ABLE y: I NTEGER RANGE 0 TO 600;
BEGI N
- - Count col umns: - - - - - - - - - - - - - -
I F ( cl k50' EVENT AND cl k50=' 1' ) THEN
I F ( Hact i ve=' 1' ) THEN x : = x + 1;
ELSE x : = 0;
END I F;
END I F;
- - Count l i nes: - - - - - - - - - - - - - - - -
I F ( Hsync' EVENT AND Hsync=' 1' ) THEN
I F ( Vact i ve=' 1' ) THEN y : = y + 1;
ELSE y : = 0;
END I F;
END I F;
- - Gener at e t he i mage: - - - - - - - - -
I F ( dena=' 1' ) THEN
I F ( ( ( x- 400) **2+( y- 300) **2) <22500) THEN
R <= ( OTHERS => ' 1' ) ;
G <= ( OTHERS => ' 1' ) ;
B <= ( OTHERS => ' 0' ) ;
ELSE
R <= ( OTHERS => r ed_swi t ch) ;
G <= ( OTHERS => gr een_swi t ch) ;
B <= ( OTHERS => bl ue_swi t ch) ;
END I F;
ELSE
R <= ( OTHERS => ' 0' ) ;
G <= ( OTHERS => ' 0' ) ;
B <= ( OTHERS => ' 0' ) ;
END I F;
END PROCESS;
END i mage_gener at or ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -