IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO.

1, JANUARY 2012 29
Performance Improvement of One-Transistor
DRAM by Band Engineering
Ashish Pal, Aneesh Nainani, Suyog Gupta, and Krishna C. Saraswat, Fellow, IEEE
AbstractWe propose a novel one-transistor (1T) quantum well
(QW) DRAM with raised GaP source/drain. This novel device
structure shows much better retention time and sense margin than
the existing silicon 1T DRAM (with and without QW). Detailed
simulation study indicates that the proposed structure is scalable
up to 15-nm gate length. The proposed device utilizes nearly
lattice-matched heterostructures which have already been realized
in the literature.
Index TermsGallium phosphide, heterostructure design,
quantum well (QW), one-transistor (IT) DRAM.
I. INTRODUCTION
W
ITH continued scaling in the past, the trend of increase
in packing density of memory bits of the conventional
one-transistor (1T) one-capacitor (1T1C) DRAM was similar
to that of the logic transistors [1]. However, as scaling con-
tinued, new problems specic to DRAM cell started to appear
like leakage and resistance of the access transistor and scaling
of the capacitor dimensions while storing sufcient charge
to maintain the good signal-to-noise ratio [2]. Due to these
fundamental challenges, the 1T1C DRAM scaling has slowed
down, and new alternatives are being researched aggressively.
1T DRAM [3][6] is a promising candidate for replacing the
1T1C DRAM in the near future. The 1T-DRAM cell size
is 4F
2
, as desired by ITRS [7]. In comparison, achieving a
feature size of 4F
2
with conventional 1T1C DRAM requires
the use of vertical channel transistor, buried bit line, and folded
word line architecture [8]. Furthermore, eliminating the trench
capacitor makes the process ow of 1T DRAM more com-
patible with CMOS logic for embedded memory in both SOI
and FinFET process ows (Fig. 1). However, Si 1T DRAM
has many problems. The retention time (t
r
) is only on the
order of 30 s10 ms [9][11], and it becomes worse with
smaller gate lengths. With scaling of dimensions, the volume
for the charge to be stored reduces [12]. To increase the stored
charge density, 1T DRAM with SiGe quantum well (QW) (1T-
Manuscript received August 25, 2011; revised October 4, 2011; accepted
October 7, 2011. Date of publication November 11, 2011; date of current ver-
sion December 23, 2011. This work was supported by the Stanford University
Non-Volatile Memory Technology Research Initiative (NMTRI), FCRP Center
on Materials, Structures, and Devices, and by a Stanford fellowship. The review
of this letter was arranged by Editor L. Selmi.
A. Pal, S. Gupta, and K. C. Saraswat are with the Center for Integrated
Systems, Department of Electrical Engineering, Stanford University, Stanford,
CA 94305 USA (e-mail: apal@stanford.edu; suyog@stanford.edu; saraswat@
stanford.edu).
A. Nainani is with Applied Materials, Inc., Sunnyvale, CA 94085 USA
(e-mail: aneesh_nainani@amat.com).
Color versions of one or more of the gures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/LED.2011.2171912
Fig. 1. RSD 1T-DRAM device structure. The proposed device has GaP
as source and drain materials. The RSD structure has comparatively more
area than a planar device to store charges, therefore improving the device
performance and scalability. The type-I heterostructure between the GaP S/D
and silicon channel helps in conning the charge in the silicon channel. For
1T-QW devices, the Ge % in the SiGe QW layer is 25%.
QW) has been proposed [13], [14], which improves the cell
performance by increasing the read current (I
read
). However,
even with QW, the t
r
of the cell does not meet the ITRS criteria
of 64 ms at 85

C. Si 1T and 1T-QW DRAMs fail to achieve
the required read margin and t
r
due mainly to two reasons:
1) During programming, the hole barrier at the source junction
is not sufcient to conne the highly energetic holes generated
by impact ionization, and so, they can easily escape and be col-
lected at the source electrode, hence reducing the sense margin
of state 1, and 2) during the hold state, the high diode leakage
current through the source/drain (S/D) diode tends to remove all
the holes stored in the body, hence reducing the t
r
. To overcome
these problems, we propose a novel fully depleted device with
GaP raised S/D (RSD), which can be either implemented in a
planar SOI or FinFET process ow (Fig. 1). First, for the same
gate length, the RSD structure has higher volume to store the
charge inside the body. Second, GaP has a much higher bandgap
of 2.26 eV than Si [15]. This results in a type-I heterostruc-
ture along the sourcechanneldrain direction with valence
and conduction band offsets of 1.04 and 0.1 V, respectively
[15]. The valence (conduction) band offset between the GaP
source and Si channel helps in conning holes (electrons) in an
n-channel (p-channel) transistor, improving the I
read
and t
r
.
Our design is also combined with the use of SiGe QW in
the channel to further improve the device characteristics [13],
[14]. In the next sections, we present results of detailed device
simulations comparing the performance of the newproposed 1T
and 1T-QW devices with GaP-RSD structure (n- and p-channel)
with the standard silicon 1T and 1T-QW devices.
0741-3106/$26.00 2011 IEEE
30 IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 1, JANUARY 2012
Fig. 2. Stored carrier density prole in (a) 1T and (b) 1T-QW devices along
direction (2) in Fig. 1 (holes for n-channel and electron for p-channel) in the
body after impact ionization shows that the charge density in GaP-SD devices
is signicantly higher than that in the silicon devices. This is attributed to the
higher barrier seen by the carriers at the sourcechannel junction in GaP-SD
devices.
II. ADVANTAGE OF USING A GaP RSD STRUCTURE
The 2-DPoisson equation, along with hydrodynamic models,
is solved to calculate the charge densities, sensing current, and
t
r
. The impact ionization models and modied local-density
approximation models to predict the carrier connement ef-
fects are included [16]. The device parameters are optimized
such that the 0 state I
read
is 1 A/m. The band lineup
in the sourcechanneldrain direction is shown in Fig. 1.
For n-channel device with GaP-SD, the barrier height for the
holes at the valence band is given by
E
barrier,V
= E
V
+K
B
T ln

N
body
N
i,Si

+K
B
T ln

N
source
N
i,GaP

E
i
(1)
where E
i
is dened as
E
i
=
E
G,GaP
E
G,Si
2
E
C
. (2)
For silicon 1T DRAM, this barrier height is simply
E
barrier,V
=K
B
T ln

N
body
N
i,Si

+K
B
T ln

N
source
N
i,Si

. (3)
Similar equations can be written for p-channel GaP-SD case.
Because of offsets present between GaP and silicon and also
since N
i,GaP
N
i,Si
, the barrier for the holes in n-channel (for
electrons in p-channel) in GaP-RSD structure is much higher
than that in the silicon case. This helps in conning most of
the generated carriers inside the body than the structure with
Si S/D. Consequently, the hole (electron) densities in GaP-
SD device after programming the cell are almost an order of
magnitude higher than those in the Si device with the SiGe
QW (Fig. 2). A back-gate voltage of 1 V (1 V) for the
n-channel (p-channel) devices is used to attract and store the
holes (electrons) near the back-gate interface. For the Si devices
with QWs (1T-QW), most of the stored carriers are in the
QW (Fig. 2). Due to higher stored charge concentration with
GaP-RSD devices, the body potential, and hence shift in the
Fig. 3. Comparison of I
read
s with a hold voltage of 1.0 V at 27

C and
85

C shows that the performances of both GaP-SD 1T and 1T-QW devices
can meet the ITRS requirements.
threshold voltage and I
read
, is much higher than that of the Si
1T or 1T-QW device. For reading of the cell, a voltage of 0.5 V
is applied to drain with zero gate voltage. During retention, a
positive (negative) hold voltage (V
Hold
) of 1.0 V is also applied
to both source and drain of the n-channel (p-channel) transistor
to increase the sourcebody and drainbody barrier heights to
retain the state of the cell. We note that both the GaP-SD 1T
and 1T-QW devices can meet the ITRS requirement of 64 ms
of t
r
at 85

C, as shown in Fig. 3. Since the GaP-RSD devices
(1T and 1T-QW) show higher retention time than the ITRS
requirements, the back-gate voltage can be reduced and traded
with retention time. Due to higher electron mobility and higher
stored charge retention attributed to higher valence band offset,
the n-channel GaP devices show higher I
read
than the p-channel
devices. At room temperature for 1T devices, a higher number
of carriers are stored near the surface, which tends to increase
the surface potential to a higher value than the corresponding
1T-QW device, resulting in higher shift in V
TH
and I
read
. How-
ever, at higher temperature, the 1T-QW devices show higher
I
read
and better retention characteristics due to higher barrier
seen by the carriers stored in the SiGe QW.
One of the concerns with applying a high source and drain
voltage during the hold state (V
Hold
= 1.0 V) is that the 0
state t
r
can be severely affected by band-to-band tunneling
(BTBT). The BTBT current depends exponentially on the tun-
neling distance which is the shortest path seen by the carriers
to tunnel across the p-n junction from an occupied state to
an empty state. Due to BTBT current, holes (electrons) in the
n-channel (p-channel) device in 0 hold state will tunnel into
the body, thus increasing the body potential and, hence, the
I
read
. This will convert the 0 state into 1, thus limiting the
0 state t
r
. Fig. 4(a) shows the plot of the tunneling distance
of different devices at the drainbody interface for different
V
Hold
s (1.0, 1.5, and 2.0 V). The higher valence band offset
at the GaPSi interface results in higher BTBT distance for
the p-channel case than Si or n-channel 1T or 1T-QW devices.
Fig. 4(b) shows the plot of the band diagram for the p-channel
GaP-SD. The tunneling distance is 19 nm even at a high V
Hold
of 2 V. So, t
r
of 0 state will be much better in p-channel
GaP-SD device. This implies that, for the same 0 state t
r
,
higher drain/source hold voltage can be applied for p-channel
GaP-SD case, resulting in better 1 state t
r
.
Finally, we study the scalability of the device dimensions
for different body thicknesses (1030 nm) and channel lengths
PAL et al.: PERFORMANCE IMPROVEMENT OF ONE-TRANSISTOR DRAM BY BAND ENGINEERING 31
Fig. 4. (a) Comparison of tunneling distance at the drainbody interface
during the hold state. (b) Band diagram of p-channel GaP-SD 1T-QW device
shows a much higher tunneling distance than the silicon and GaP-SD devices,
indicating better retention of 0 state.
Fig. 5. I
read
of p-channel GaP-SD devices with scaled gate length and body
thickness shows that, even for 15-nm gate length, both 1T and 1T-QW DRAMs
have enough retention of stored charges to separate state 1 from state 0
(I
read
> 6 A/m).
(45 and 15 nm). Fig. 5 summarizes the result. When the body
thickness is reduced in this range, the stored carriers are con-
ned in a smaller volume. So, the concentration of the stored
charge and, hence, the body potential increases, which reects
a higher I
read
. However, the I
read
reduces as the gate length
is scaled. As the channel length is scaled, the same number of
carriers is stored in a smaller volume mainly under the gate due
to the sourcebody and drainbody depletion regions, leading
to a higher recombination rate. However, even at 15-nm gate
length with 10-nm body thickness, both p-channel GaP-SD 1T
and 1T-QW devices show sufcient I
read
to have a good sense
margin. Also, it must be noted that GaP has very small lattice
mismatch (0.37%) with silicon. High-quality epitaxial lms
of GaP on silicon have already been grown [17], making 1T
DRAM with GaP-RSD an attractive candidate for experimental
investigation.
III. CONCLUSION
In this letter, we have proposed a novel 1T-DRAM structure
with GaP RSD. Being almost lattice matched with silicon, the
epitaxial growth of GaP on silicon has already been realized.
The band offsets at source and drain between GaP and silicon
help to improve the sense margin and the retention time con-
siderably. The performance can even be more enhanced using
silicon germanium QW. Finally, by scalability study of channel
length and body thickness, we showed that, even at 15-nm
node, the p-channel GaP device has enough sense margin and
retention time for proper DRAM functionality.
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