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    Charge Steering: A Low-Power Design Paradigm

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    Ashfaq Ahmed
    The document proposes a charge steering design paradigm for low-power integrated circuits. It introduces charge steering logic as an alternative to traditional current steering, and describes its application in clock and data recovery (CDR) and demultiplexer designs, as well as analog-to-digital converters (ADCs). The document reports on implementations of a 25Gb/s 5.8mW CMOS equalizer, a 25-Gb/s 5-mW CDR/deserializer, and a 10-bit 800-MHz 19-mW CMOS ADC using this charge steering approach.

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    Charge Steering: A Low-Power Design Paradigm

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    Ashfaq Ahmed
    39 views6 pages
    The document proposes a charge steering design paradigm for low-power integrated circuits. It introduces charge steering logic as an alternative to traditional current steering, and describes its application in clock and data recovery (CDR) and demultiplexer designs, as well as analog-to-digital converters (ADCs). The document reports on implementations of a 25Gb/s 5.8mW CMOS equalizer, a 25-Gb/s 5-mW CDR/deserializer, and a 10-bit 800-MHz 19-mW CMOS ADC using this charge steering approach.

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    design survey

    Original Title

    30 April, 2014

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    The document proposes a charge steering design paradigm for low-power integrated circuits. It introduces charge steering logic as an alternative to traditional current steering, and describes its application in clock and data recovery (CDR) and demultiplexer designs, as well as analog-to-digital converters (ADCs). The document reports on implementations of a 25Gb/s 5.8mW CMOS equalizer, a 25-Gb/s 5-mW CDR/deserializer, and a 10-bit 800-MHz 19-mW CMOS ADC using this charge steering approach.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pptx, pdf, or txt
    39 views6 pages

    Charge Steering: A Low-Power Design Paradigm

    Uploaded by

    Ashfaq Ahmed
    The document proposes a charge steering design paradigm for low-power integrated circuits. It introduces charge steering logic as an alternative to traditional current steering, and describes its application in clock and data recovery (CDR) and demultiplexer designs, as well as analog-to-digital converters (ADCs). The document reports on implementations of a 25Gb/s 5.8mW CMOS equalizer, a 25-Gb/s 5-mW CDR/deserializer, and a 10-bit 800-MHz 19-mW CMOS ADC using this charge steering approach.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
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    of 6

    Charge Steering: A Low-Power Design Paradigm

    [1] Razavi, B., "Charge steering: A low-power design


    paradigm," Custom Integrated Circuits Conference (CICC),
    2013 IEEE , vol., no., pp.1,8, 22-25 Sept. 2013
    doi: 10.1109/CICC.2013.6658443

    INTRODUCTION
    BASIC IDEA
    CHARGE-STEERING LOGIC
    CDR AND DEMUX DESIGN
    CHARGE STEERING ADCs
    CONCLUSION
    Introduction/Basic Idea
    Transformation from current steering to charge steering [1]
    CHARGE-STEERING LOGIC
    CDR AND DEMUX DESIGN
    CHARGE-STEERING ADCs

    Implementation

    A 25Gb/s 5.8mW CMOS Equalizer [ISSCC 2014]
    A 25-Gb/s 5-mW CMOS CDR/Deserializer [JSSC 2013]
    A 10-bit 800-MHz 19-mW CMOS ADC [JSSC 2014]



    Summary
    Take Away Message
    Motivation
    Proposed Solution
    Authors Evaluation
    My Analysis
    Future Directions
    Open Questions

    Future Work
    Apply technique on other type of data converters, Equalizer
    Circuit(FFE,CTLE, DFE)

    A 25Gb/s 5.8mW CMOS equalizer
    A 10-Bit 800-MHz 19-mW CMOS ADC

    References
    [1] Razavi, B., "Charge steering: A low-power design paradigm," Custom Integrated Circuits
    Conference (CICC), 2013 IEEE , vol., no., pp.1,8, 22-25 Sept. 2013
    doi: 10.1109/CICC.2013.6658443
    [2] Jun Won Jung; Razavi, B., "A 25-Gb/s 5-mW CMOS CDR/Deserializer," Solid-State Circuits, IEEE
    Journal of , vol.48, no.3, pp.684,697, March 2013
    doi: 10.1109/JSSC.2013.2237692
    [3] Chiang, S.-H.W.; Hyuk Sun; Razavi, B., "A 10-Bit 800-MHz 19-mW CMOS ADC," Solid-State
    Circuits, IEEE Journal of , vol.49, no.4, pp.935,949, April 2014
    doi: 10.1109/JSSC.2014.2300199
    [4] Jun Won Jung; Razavi, B., "2.4 A 25Gb/s 5.8mW CMOS equalizer," Solid-State Circuits
    Conference Digest of Technical Papers (ISSCC), 2014 IEEE International , vol., no., pp.44,45, 9-13
    Feb. 2014doi: 10.1109/ISSCC.2014.6757330

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