Exercises for chapter 2 VLSI Design

1. Sketch a transistor level schematic for a CMOS 4-input NOR gate.

2. Sketch a transistor level schematic for a single-stage CMOS logic gate for each of the
following function:
a. = +

b. = ( +)

c. = + ( +)

3. Sketch transistor level schematics for the following logic functions. You may assume you
have both true and complementary versions of the input variable
a. A 2:4 decoder defined by:
0 = 0

1
1 = 0 1
2 = 0

1
3 = 0 1
b. A 3:2 priority encoder defined by:
0 = 0

(1 +2
1 = 0

1
4. Sketch a stick diagram for 4-input NOR gate
5. Consider the design of a CMOS compound OAI21
a. Sketch a transistor level schematic
b. Sketch a stick diagram
6. Repeat the exercise 5 with CMOS compound OAI22
7. A 3-input majority gate returns a true output if at least two of the inputs are true. A
minority gate is its complement. Design a 3-input CMOS minority gate using single-stage
of logic
a. Sketch a transistor-level schematic
b. Sketch a stick diagram
c. Design the minority gate using CMOS NANDs, NORs and inverters gate. How
many transistors are required?