((FET)

FET)

 FET
JFET

Gate

p+

p+

ID

Source

JFET

IG

IS

VGG

VDD

Drain

p+
Gate

p+

VDD

VGG

MOS
-FET
MOS-FET

n++

ly
Po

(SiO2)

-Si

Source
(S)

n++

n++

Gate

GS>V
=V
=0 tn
G

DS=0
D

n++
p

n++

Bulk

n++
W
p

S Source

Vtn =
Vtn > 0

L
Poly-Si
Gate

Drain
(D)
D
G

S
4

nMOS ()
GS>Vtn
G
0DS
< =0
DS <<
D

S
n++

n++

iD

nMOS ()
iD
GS = Vtn +4V
GS = Vtn +3V
GS = Vtn +2V
GS = Vtn +1V
GS Vtn iD0
100

200

DS (mV)

nMOS ()
GS>V
=0 tn
G

GS
=0 tn > DS >>0
DS V

D
n++

n++

: DS GS Vtn

nMOS (
V)
(V)
GS>Vtn
G

= GS
DS >>>
t Vtn
GSV

D
n++

n++

p
Pinch-Off
: DS > GS Vtn

iD--
DS nMOS

tn

iD
()

<

GS

DS > GS Vtn

GS > Vtn

. DS

DS

DSsat= GS Vtn

nMOS
ly
Po

n++

-Si

n++

Kn =

n W
2 t ox L

Kn =

n
2
GS Vtn < 0

0
iD =

K n 2(GS Vtn )DS 2DS

K n (GS Vtn )

0 < DS < GS Vtn

0 < GS Vtn < DS

10

iD--
DS nMOS
iD

tn

DSsat= GS Vtn

GS

GS = Vtn +4V

<

DS > GS Vtn

()

iD

GS = Vtn +3V
GS = Vtn +2V

iG=0

GS = Vtn +1V

GS

iD = K n

DS

2
DSsat

GS Vtn

DS

iS=iD

11

iD--
GS nMOS
iD

: DS GS Vtn GS Vtn
iD

Kn (GS Vtn )

GS

i D = K n (GS Vtn )

DS

iS =iD

GS

Vtn

-
DC
nMOS

12

 pMOS

VDD > 0

p+

S
lyPo

(SiO2)

Source
(S)

p+

p+

Source
S

VDD

Gate

= 0tp
=V
GS<V
G

Drain
(D)

p+

Bulk

p+
W

DS= 0
D

p+
Vtp =
Vtp < 0

L
Poly-Si
Gate

S
G

VDD K

D
13

pMOS ()
GS<Vtp
G
VDD

DS=DS0 < 0
<<
D

S
p+

iD

p+

n
VDD

14

pMOS ()
GS<Vtp
G
VDD

GS
=0 tp < DS <<0
DS V

D
p+

p+

n
VDD
: 0 > DS > GS Vtp

15

pMOS (
II)
(II)
GS<Vtp
G
VDD

= GS
DS <<<
t Vt
GSV

D
p+

p+

n
VDD

Pinch-Off

: DS < GS Vtp < 0

16

 pMOS
ly
Po

p+

-Si

Kp =

p+

Kp =

2
GS Vtp > 0

K p 2(GS Vtp )DS 2DS

iD =

p W
2 t ox L
p

K p (GS Vtp )

0 > DS > GS Vtp

0 > GS Vtp > DS

17

iD--
GS pMOS
|iD|

: DS GS Vtp GS Vtp
iD

Kp GS Vtp

)2

GS

i D = K p GS Vtp

)2

DS

iS =iD

|GS|

Vtp

-
DC
pMOS

18

iD--
DS pMOS

DS
GS Vtp

i D = K n 2DSsat

GS = Vtp 1V

()

GS = Vtp 2V

tp

GS = Vtp 3V

>
D

GS = Vtp 4V

GS

DS < GS Vtp

DSsat= GS Vtp

iD

19

Voltage

VD

VD

Voltage

VDD

VS
VS-|Vtp|

Vtp

VG

VG

Vtn
VS+Vtn

Gnd

VS

nMOS

pMOS

20

10

 ()
:

iD

DS

GS

DS()

DS()

nMOS

Early

DS

VA=1/

DS DS DS() [DS=DS()+DS]
L L. iD
, iD . :

i D = K (GS Vt ) (1 + DS )
2

21

()
:

.

(.
x).
K ( V )
iD
G
D
2

GS

tn

GS

DS
ro

ro :
1

i
ro = D
= K ( GS Vt )2

DS

GS = .

] (I )
1

VA

iS =iD

I D

22

11

 MOS

Si3N4
spacers

Poly-Si
SiO2
SiO2

180nm

23

MOS -

pMOS
pMOS

nMOS
nMOS

S
G

G
S

D
G

D
B

24

12

CMOS

ly
Po

n++

p+

-Si

ly
Po

p+
n-

n++

-Si

p+
n++
p

25

1 ()
:
:
Vtn=1V Kn=0.5mA/V2.

VDD=5V
D

RD
VD=0.1V

:
G=0

RD
VD=0.1V;

26

13

 1 (
I)
(I)
VDD=5V
D

VDS=0.1V, :

VDS = 0.1V < 4V = VGS Vtn

RD
VD=0.1V

G=0

() . ID
:

2
I D = K n 2(VGS Vtn )VDS VDS
= 0.395mA

Ohm:

RD =

VDD VD
= 12.4K
ID

27

2 ()
VDD=10V
RG1=10M

RD=6K

G=0

RG2=10M

:
:
Vtn=1V Kn=0.5mA/V2.
:

D
RS=6K

28

14

 2 (
I)
(I)
VDD=10V
RG1=10M

RD=6K

G=0

DS

VG=5V > Vtn=1V

.
.

DS

RG2=10M

IG MOS
. RG1 RG2

VG=5V.

RS=6K

29

2 (
I)
(I)
- :

VDD=10V
RG1=10M

RD=6K

G=0
G
RG2=10M

VGS = VG VS = VG I D R S
ID :

I D = K n (VGS Vtn ) 2

RS=6K

I D = K n (VG Vtn I D R S ) 2
ID = 0.89mA ID = 0.5mA

30

15

 2 (
V)
(V)

.

VDD=10V
RG1=10M

RD=6K

G=0

D = 0.5mA.
VS = 3V VGS = VG VS = 2V>Vtn

RG2=10M

ID=0.89mA : VS = ID.RS=5.34V.
VS > VG

ID=0.

RS=6K

VD = VDD I D R D = 7V

VDS=(73)V=4V > 1V=(2 1)V=VGS Vtn 9

!

31

2 ((V)
V)
VDD

VDD

VDD=10V
RD=6K

G
G=0

RG2=10M

RD

RG1

RG1=10M

G=0

Kn (VGS Vtn )

RG2

VGS

D
VDS

D
RS=6K

S =D
RS

32

16

 3 ()
:

VDD=+5V

D=0.5mA
VD=+3V. RD

;

RG1

G=0
RG2

VD=+3V

:
:
Vtp= 1V Kp=0.5mA/V2.

RD

33

3 (
I)
(I)
ID :

VDD=+5V

I D = K p (VGS Vtp ) 2

RG1

VGS= 2V.

S
G

G=0
RG2

VD=+3V

D
RD

VS=5V VG=3V.
IG MOS
, RG1
RG2

RG1=2 RG2=3 VG=3V.

34

17

 3 (
I)
(I)
RD :

VDD=+5V

RD =

RG1

VD
= 6K
ID

N. Ohm

VDSVGS Vtp. VD VG Vtp.
G=0
RG2

VD=+3V

:
VDmax = VG Vtp = 3+1 = 4V

RD

R D max =

VD max
= 8K
ID

35

MOS
iD DS = GS Vtn
VDD

DS = GS

GS 4

DS = GS

iG=0

GS 3

iD

GS2
GS1

Vtn

GS1

DS
GS

GS2
MOS :
GS3
GS Vt < DS GS
2
! i D = K n (VDD Vtn )
GS4

36

18