Chng 5 phn 2

NHP MN MCH S
Mch t hp:
Cc loi mch khc
Ni dung
5. Mch gii m (Decoder)/ Mch m ho
(Encoder)
6. Mch dn knh (Multiplexer)/ Mch chia
knh (Demultiplexer)
7. Mch to Parity/ Mch kim tra
8. Mch so snh (Comparator)
5. Decoder/ Encoder

Mch gii m (Decoder)
Nhiu ng vo/ nhiu ng ra
Ng vo (n) thng thng t hn ng ra (m)
Chuyn m ng vo thnh m ng ra
nh x 1-1:
Mi m ng vo ch to ra mt m ng ra
Cc m ng vo:
M nh phn
Your Code!
Cc m ng ra:
1-trong-m
Gray Code
BCD Code
enable
inputs
Mch gii m nh phn (Binary
Decoders)
Mch gii m n-ra-2
n
: n ng vo v 2
n
ng ra
M u vo: n bit nh phn
M u ra: 1-trong-2
n

V d: n=2, mch gii m 2-ra-4
Ch x (k hiu ng vo dont care)
Gii m nh phn 2-ra-4
74x139: Biu tng lun l Bng s
tht
Tnh hiu Enable tch cc mc thp v ng ra tch
cc mc thp





Mch gii m hon chnh 74x139
74x138: Gii m nh phn 3-to-8
Bng s tht
74x138
Biu tng
lun l
Mch lun l
Ghp mch gii m
Mch gii m
4ra16
ng dng ca mch gii m
Mt ng dng ph bin l gii m a ch cho cc
chip nh
V d: gii m BCD ra
n 7 on
n 7 on (7-segment display)
n 7 on l cch ph bin hin th s thp phn
hoc s thp lc phn
S dng LED cho mi on

n 7 on (7-segment display)
Bng cch iu khin dng in qua mi
LED, mt s on s sng v mt s tt,
t to nn s mong mun
Gii m BCD ra n 7 on
Chuyn s BCD sang thng tin thch hp hin th trn n 7
on
Mch m ho
Nhiu ng vo/ nhiu ng ra

Chc nng ngc li vi
mch gii m

Outputs ( m ) t hn inputs ( n
)

Chuyn m ng vo thnh m
ng ra


input
code
output
code
ENCODER
Encoders vs. Decoders
Decoder Encoder
2^n-ra-n
Input code: 1-trong-2^n
Output code: M nh phn
n-ra-2^n
Input code: M nh phn
Output code:1-trong-2^n
decoders/encoders nh phn
Mch m ho nh phn (Binary
Encoder)
2^n-ra-n encoder: 2^n ng vo v n ng ra
Input code: 1-trong-2^n
Output code: M nh phn

V d: n=3, mch gii m 8-ra-3

Ng vo Ng ra
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
I1
I2
I3 Y1
Y2 I4
I5
I6
I0
Y0
I7
Binary encoder
Hin thc mch gii m 8-ra-3
Rt gn:
Y0 = I1 + I3 + I5 + I7
Y1 = I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 + I7

I1
I2
I3
I4
I5
I6
I0
I7
Y1
Y0
Y2

Ng vo Ng ra
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Hin thc mch gii m 8-ra-3

Gii hn:
I0 khng nh hng n ng ra
Ch mt ng nhp c kch hot ti
mt thi im


ng dng:
Gii quyt nhng yu cu t nhiu
thit b, nhng khng phi l nhng
yu cu ng thi.

Thit lp mc u tin gii quyt
vn ca nhiu yu cu
I1
I2
I3
I4
I5
I6
I0
I7
Y1
Y0
Y2
Cn c u tin trong hu ht cc ng
dng
Mch m ho c u tin (Priority
Encoder)
Gn u tin cho cc ng vo

Khi c nhiu hn 1 ng vo c hiu lc, ng ra to ra m ca
ng vo c u tin cao nht.

Priority Encoder:
H7=I7 ( u tin cao nht)
H6=I6.I7
H5=I5.I6.I7
H4=I4.I5.I6.I7
H3=I3.I4.I5.I6.I7
H2=I2.I3.I4.I5.I6.I7
H1=I1. I2.I3.I4.I5.I6.I7
H0=I0.I1. I2.I3.I4.I5.I6.I7
IDLE= I0.I1. I2.I3.I4.I5.I6.I7

Encoder
A0=Y0 = H1 + H3 + H5 + H7
A1=Y1 = H2 + H3 + H6 + H7
A2=Y2 = H4 + H5 + H6 + H7
I6
I5
I4 Y1
Y0 I3
I2
I1
I7
Y2
I0
Binary encoder
I6
I5
I4
I3
I2
I1
I7
I0
Priority Circuit
H6
H5
H4
H3
H2
H1
H7
H0
IDLE
I6
I5
I4
I3
I2
I1
I7
I0
A1
A0
A2
IDLE
Priority encoder
8-input priority encoder
I7 c u tin cao nht, I0 thp nht
A2-A0 cha s th t ca ng vo c
u tin cao nht c hiu lc
IDLE c hiu lc nu khng c ng
vo no c hiu lc
74x148 8-input priority encoder
I/O tch cc mc thp
Ng vo Enable
Got Something": Group Select
Ng ra Enable
74x148 Bng s tht

74x148
27
S lun l
Cascading
priority encoders

Mch m ho c
u tin 32-ng vo
6. Multiplexer (MUX)/
Demultiplexer (DeMUX)

Multiplexer
A MUX truyn mt trong nhng ng vo ca
n ra ng ra da trn tn hiu Select
Ng vo SELECT s xc
nh ng vo no c
truyn ra Z
2-ra-1 Multiplexer
Sel Out
0 I
0
1 I
1
Out =I
0
* Sel + I
1
*Sel
4-ra-1 Mux
4-ra-1 Mux xut ra mt trong bn ng vo da
trn gi tr ca 2 tn hiu select
Xy dng MUX 4-ra-1
T MUX 2-ra-1
MSI: 74x151 8-input 1-bit multiplexer
Bng s tht
Biu tng
S lun l
Demultiplexer
Demultiplexer (DEMUX) ly ng vo duy nht v
phn phi n ra vi ng ra.
M ng vo SELECT s xc nh ng ra no m ng vo
DATA s truyn qua
DATA c truyn ra mt
v ch mt ng ra c xc
nh bi m ca ng vo
SELECT
DEMUX

1-ra-8 demultiplexer
Ch : I l ng vo
DATA
Tng hp cc hm logic t MUX
Cch hin thc LUT s dng MUX chn mt gi
tr (hng s) t look-up table

V d hm XOR
Tng hp cc hm logic t MUX
Gii php slide trc khng hiu qu
Tng hp cc hm logic t MUX
V d: Hin thc mch vi bng s tht sau bng mt
MUX v cc cng khc
A B X
0 0 1
0 1 1
1 0 0
1 1 1
Tng hp cc hm logic t MUX
XOR 3 ng vo c th hin thc bng 2 MUX 2 ra 1
Tng hp cc hm logic t MUX
V d: Hin thc mch vi bng s tht sau bng mt
MUX v cc cng khc
A B C X
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Biu thc Shannon
Bt k hm boolean f(w
1
,w
2
, , w
n
) c th c vit
di dng:

f(w
1
,w
2
, , w
n
)=*f(0,w
2
, ..., w
n
) + w
1
*f(1, w
2
, w
n
)

Biu thc Shannon
Example 1:
f(w
1
,w
2
, w
3
)= w
1
w
2
+ w
1
w
3
+ w
2
w
3


Expanding this in terms of w
1
:
f(w
1
,w
2
, w
3
)= w
1
(w
2
+ w
3
)

+
1
(w
2
w
3
)
f when w
1
=1 f when w
1
=0
Wrong??
Biu thc Shannon

Biu thc Shannon
V d 2:

Chn x lm bin m rng
Biu thc Shannon
V d 3:


Chn z lm bin m rng

V d
Dng MUX 4 ra 1 v cc cng lun l cn thit
hin thc hm sau:
F (a, b, c, d) = SOP (1, 3, 5, 6, 8, 11, 15)

Yu cu: c v d l cc ng vo iu khin ca MUX 4
ra 1
7. Parity Generator/ Checker

Cng Exclusive OR v Exclusive NOR
XOR
X
Y
F
' ' Y X Y X Y X
' ' )' ( Y X Y X Y X
XOR: NAND 3 cp
XNOR:
XOR: AND-OR
Bng s tht
XOR and XNOR Symbols
Cc biu tng tng ng ca cng XOR




Cc biu tng tng ng ca cng XNOR
ng dng ca XOR: Mch Parity
Mch Parity chn: tng s bit 1 trong chui bit (k c bit parity) l s chn.
Parity bit = 1, nu s s 1 trong chui bit (khng k parity) l s l
Parity bit = 0, nu s s 1 trong chui bit (khng k parity) l s chn
Mch Parity l: tng s bit 1 trong chui bit (k c bit parity) l s l.
V d: Mch Parity 4-bit

Input Even Parity Odd Parity
0000 0 1
0001 1 0
1101 1 0
1111 0 1
1100 0 1
EVEN
ODD
ODD
EVEN
ng dng ca XOR: Mch Parity
Tree structure
Daisy-Chain Structure
EVEN
EVEN
ng dng ca XOR: Mch Parity
Source: http://en.wikipedia.org/wiki/Parity_bit
Mch kim tra parity MSI: 74x280
NOTE: the 74x280 chip defines the even/odd parity
bit opposite to the definition in the previous slides
Mch kim tra parity
ng dng ca XOR: Mch Parity
Source: http://en.wikipedia.org/wiki/Parity_bit
ng dng cng XOR: Parity
Source: http://en.wikipedia.org/wiki/Parity_bit
8. Comparator
Mch so snh
Mch so snh so snh 2 s
Xut ra 1 nu chng bng nhau
Xut ra 0 nu chng khc nhau
Da trn cng XOR, tr v 0 nu ng vo ging nhau
v 1 nu chng khc nhau
Da trn cng NXOR, tr v 1 nu ng vo ging
nhau v 0 nu chng khc nhau
Mch so snh 1 bit

a b gt eq lt
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
Mch so snh 4 bit
a0
b3
a3
b2
a2
b1
a1
b0
eq
Mch so snh 4 bit
a0
b3
a3
b2
a2
b1
a1
b0
gt
Mch so snh 4 bit
lt
Mch so snh 4 bit
74x85 l mch so snh tiu chun vi nhng c tnh sau:

if (A>B) lt=0, eq=0, gt=1
if (A<B) lt=1, eq=0, gt=0
if (A=B) lt=l, eq=e, gt=g

Ch : 3 ng vo l, e v g c s dng khi ghp
4
4
B
A
g
e
l
gt
eq
lt
Mch so snh 16 bit
Ghp 4 IC 74x85 xy dng mt mch so snh 16
bit

a[ 15:0 ]
b[ 15:0 ]
[15:12]
4
4
B
A
g
e
l
gt
eq
lt
4
4
B
A
g
e
l
gt
eq
lt
[15:12]
[11:8] [11:8] [7:4]
4
4
B
A
g
e
l
gt
eq
lt
4
4
B
A
g
e
l
gt
eq
lt
0
1
0
[7:4]
[3:0] [3:0]
gt eq lt
Final results of
comparison
Mch so snh 16 bit
Mch s u tin so snh 4 bit cao nht 2 ng vo

Trong bc u ny:
a nh hn b nu 4 MSB nh hn
a ln hn b nu 4 MSB ln hn
Nu 4 MSB ca 2 s bng nhau, kt qu ca php so snh
s l kt qu so snh bit thp hn
V d
Thit k mch tm s ln nht s nh nht trong n s
4 bit s dng mch so snh v MUXs
Any question?