Layout Design Rules

Amir M. Sodagar
Spring 2003

K.N.Toosi University of
Amir M. Sodagar Technology ١
Layout of An MOS Transistor
‰ MOS Transistor

‰ A partially-finished
transistor

‰ The corresponding
layout of the Active,
Poly, and Contact
masks (for a minimum-
size transistor)

For a min. size tr.:

AS=AD=5λW, PS=PD=10λ+W [1]

Amir M. Sodagar K.N.Toosi University of Technology ٢

Why design rules?
‰ Minimum width
‰ An excessively narrow poly rectangle:

Layout After fabrication

It may simply break or at least suffer from a large local resistance

Amir M. Sodagar K.N.Toosi University of Technology ٣

Why design rules?
‰ Spacing

Mask misalignment that results in catastrophic short circuits

and an example of a non-catastrophic misalignment
Amir M. Sodagar K.N.Toosi University of Technology ٤
Why design rules?
‰ Spacing
¾ Two excessively close poly lines

Layout After fabrication

A short may occur between the two lines after fabrication.

Amir M. Sodagar K.N.Toosi University of Technology ٥

Design Rules
‰ Minimum spacing
between active and
poly

‰ Enclosure rule for poly

and metal surrounding
a contact

Amir M. Sodagar K.N.Toosi University of Technology ٦

Design Rules
‰ Extension of poly beyond the gate area

Amir M. Sodagar K.N.Toosi University of Technology ٧

Design Rules
‰ Layout of a differential pair with PMOS current-
source loads

Amir M. Sodagar K.N.Toosi University of Technology ٨

Design Rules
‰ Design Rules for a Double-Metal, Double-
Polysilicon, N-Well, Bulk CMOS Process.

Minimum Dimension Resolution (λ)

‰ 1. N-Well
¾ 1A. width .................................….....................………………….......6
¾ 1B. spacing (same potential)......….......................………………......8
¾ 1C. spacing (different potential) ................…..……………….........22

‰ 2. Active Area (AA)

¾ 2A. width ........................................................……………….............4

Amir M. Sodagar K.N.Toosi University of Technology ٩

Design Rules
Spacing to Well
¾ 2B. AA-n contained in n-Well ..................…………………..................1
¾ 2C. AA-n external to n-Well.................................…………………....10
¾ 2D. AA-p contained in n-Well ...........................…………………….....3
¾ 2E. AA-p external to n-Well...................................…………………....7
Spacing to other AA (inside or outside well)
¾ 2F. AA to AA (p or n) .........................................…………………...…3

‰ 3. Polysilicon Gate (Capacitor bottom plate)

¾ 3A. width........................................................……………….......….....2
¾ 3B. spacing...................................................……………….........…....3
¾ 3C. spacing of polysilicon to AA (over field)....…………………..........1
¾ 3D. extension of gate beyond AA (transistor width direction) ……….2
¾ 3E. spacing of gate to edge of AA (transistor length direction) ……..4

Amir M. Sodagar K.N.Toosi University of Technology ١٠

Design Rules
‰ 4. Polysilicon Capacitor top plate
¾ 4A. width...................................................................……………......2
¾ 4B. spacing...................................................................…………......2
¾ 4C. spacing to inside of polysilicon gate (bottom plate)………….....2
‰ 5. Contacts
¾ 5A. size ........................................................................……….....2x2
¾ 5B. spacing..................................................................………..........4
¾ 5C. spacing to polysilicon gate ....................................………….....2
¾ 5D. spacing polysilicon contact to AA.......................………….........2
¾ 5E. metal overlap of contact .....................................………….........1
¾ 5F. AA overlap of contact .........................................……....…….....2
¾ 5G. polysilicon overlap of contact ..................................…………...2
¾ 5H. capacitor top plate overlap of contact........................……….…2
‰ 6. Metal-1
¾ 6A. width.........................................................................………......3
¾ 6B. spacing.....................................................................………......3

Amir M. Sodagar K.N.Toosi University of Technology ١١

Design Rules
‰ 7. Via
¾ 7A. size .......................................................................……….......3x3
¾ 7B. spacing................................................................………............4
¾ 7C. enclosure by Metal-1...........................................………............2
¾ 7D. enclosure by Metal-2..........................................……….............2
‰ 8. Metal-2
¾ 8A. width...................................................................…………..........4
¾ 8B. spacing...............................................................……….............3
Bonding Pad
¾ 8C. spacing to AA.......................................................……….........24
¾ 8D. spacing to metal circuitry ......................................……….......24
¾ 8E. spacing to polysilicon gate ....................................…….…......24
‰ 9. Passivation Opening (Pad)
¾ 9A. bonding-pad opening......................………....100 mm x 100 mm
¾ 9B. bonding-pad opening enclosed by Metal-2 ...........…….…........8
¾ 9C. bonding-pad opening to pad opening space ..........………......40

Amir M. Sodagar K.N.Toosi University of Technology ١٢

Design Rules

Amir M. Sodagar K.N.Toosi University of Technology ١٣

Design Rules

Amir M. Sodagar K.N.Toosi University of Technology ١٤

Design Rules

Amir M. Sodagar K.N.Toosi University of Technology ١٥

Design Rules

Amir M. Sodagar K.N.Toosi University of Technology ١٦

Layout Design
‰ A series connection of two MOS transistors

A single junction (J3) is shared

between Q1 & Q2.
ÎThe area and specially the
perimeter of this junction gets
much smaller.
Amir M. Sodagar K.N.Toosi University of Technology ١٧
Layout Design
‰ A CMOS Digital Inverter

Amir M. Sodagar K.N.Toosi University of Technology ١٨

Layout Design
‰ Realization of a large transistor

Amir M. Sodagar K.N.Toosi University of Technology ١٩

Layout Design
‰ A common-centroid layout

Amir M. Sodagar K.N.Toosi University of Technology ٢٠

Layout of Passive Devices
‰ A simplified layout of a capacitor array

Amir M. Sodagar K.N.Toosi University of Technology ٢١

Layout of Passive Devices
‰ Resistor Layout

A typical layout for an A more accurate, but larger,

integrated resistor layout for a resistor
Amir M. Sodagar K.N.Toosi University of Technology ٢٢
Undesired Effects
‰ Parasitic capacitance of the interconnects
¾ Parallel plate and fringe capacitance of an
interconnect

Amir M. Sodagar K.N.Toosi University of Technology ٢٣

Undesired Effects
‰ Latch-up Problem
NMOS PMOS
Cross section of a CMOS
inverter with superimposed
schematic of the parasitic
transistors responsible for
the latch-up mechanism

The equivalent The voltages

circuit of the after latch-up
parasitic bipolar has occurred
transistors

Amir M. Sodagar K.N.Toosi University of Technology ٢٤

 Multi-Metal-Layer Processes
‰ Cross-over Metal

Metal Metal
Metal 2

Oxide
Metal 1
n+ or p+ Diffusion

Metal Metal

Metal 2

n+ or p+
Diffusion
Metal Metal 1

In Single-Metal In Double-Metal
Processes Processes
Amir M. Sodagar K.N.Toosi University of Technology ٢٥
Multi-Metal-Layer Processes

Amir M. Sodagar K.N.Toosi University of Technology ٢٦

Multi-Metal-Layer Processes
‰ Via

Metal 2

Metal 1
Oxide

Amir M. Sodagar K.N.Toosi University of Technology ٢٧

Layout vs. Die Photo
‰ University of Michigan BiCMOS Process

Amir M. Sodagar K.N.Toosi University of Technology ٢٨

Layout vs. Die Photo
‰ A 2mmx2mm Chip, AMI 1.6μm N-Well CMOS through MOSIS

Amir M. Sodagar K.N.Toosi University of Technology ٢٩

Terminology

Amir M. Sodagar K.N.Toosi University of Technology ٣٠

Die Photo

Amir M. Sodagar K.N.Toosi University of Technology ٣١

Die Photo

Amir M. Sodagar K.N.Toosi University of Technology ٣٢

Die Photo

Amir M. Sodagar K.N.Toosi University of Technology ٣٣

 Test & Monitoring After Fab

K.N.Toosi University of
Amir M. Sodagar Technology ٣٤
A Wafer

Amir M. Sodagar K.N.Toosi University of Technology ٣٥

Wafer Slice
‰ Dice on a wafer slice

Amir M. Sodagar K.N.Toosi University of Technology ٣٦

Holding a Die By a Tweezer

Amir M. Sodagar K.N.Toosi University of Technology ٣٧

Un-bonded Chip
‰ A 2mmx2mm Chip

Amir M. Sodagar K.N.Toosi University of Technology ٣٨

Probe Station
‰ Binocular microscope with platform for
micromanipulators
‰ Micromanipulators with sharp tips for
electrical and mechanical probing of
substrate
‰ Long focal depth microscope is needed
‰ Various designs possible, useful features:
¾ Move sample stage relative to probes
¾ Move microscope relative to sample and probes
¾ Zoom, video camera
EE527 - Microfabrication Techniques, University of Washington, 2000

Amir M. Sodagar K.N.Toosi University of Technology ٣٩

Probe Station

Amir M. Sodagar K.N.Toosi University of Technology ٤٠

Micromanipulator

Amir M. Sodagar K.N.Toosi University of Technology ٤١

Probe Tips

Amir M. Sodagar K.N.Toosi University of Technology ٤٢

Micro-photograph of a 2mmx2mm Die

Amir M. Sodagar K.N.Toosi University of Technology ٤٣

Bonding Pads

Amir M. Sodagar K.N.Toosi University of Technology ٤٤

Test Points

Amir M. Sodagar K.N.Toosi University of Technology ٤٥

Fusible Links

Amir M. Sodagar K.N.Toosi University of Technology ٤٦