FPGA Logic Cells Comparison

In this article we compare logic cells architectures that are used in modern FPGAs: Xilinx (both
Virtex-5 and earlier! Altera and Actel"
Introduction
FPGA (Field Programmable Gate Array) is an integrated circuit containing a matrix of user-
programmable logic cells, being able to implement complex digital circuitry.
These gates are designed to implement user-defined combinational and seuential functions. FPGA
families from different !endors use different logic cells architecture.
"elo# you can find a short o!er!ie# of different FPGA logic cells architectures, as #ell as an
attempt to elaborate a uni!ersal method of their comparison.
Xilinx Slices (Virtex-4 and earlier)
The elementary programmable logic bloc$ in %ilinx FPGAs is called slice"
This architecture (#ith minor modifications) is used in all Virtex FPGA families before Virtex-5 and
all #partan FPGA families so far (at least, up to #partan-$A).
The &irtex-' FPGA slice includes(
T#o 4-input LUTs ()oo$-*p Tables) that can implement any '-input boolean function,
used as combinational function generators (one )*T is mar$ed +F,, the other one is mar$ed
+G,).
T#o dedicated user-controlled multiplexers for combinational logic (-*%F. and
-*%F%). -*%F. can be used to combine outputs of the slice/s )*Ts and so to implement
.-input combinational circuit. -*%F% is used to combine outputs of the other -*%F. and
-*%F% (from the other slices).
0edicated arithmetic logic (t#o 1-bit adders, carry chain and t#o dedicated A20 gates for
fast and efficient multiplication).
T#o 1-bit registers that can be configured either as flip-flops or as latches. The input to
these registers is selected by 3-*% and %-*% multiplexers. 2ote that these multiplexers
aren/t user-controlled( the path is selected during FPGA programming.
The simplified diagram of a &irtex-' slice is presented belo#.
This '-input )*T-based architecture became can be considered classic.
To implement a a '-input )*T one need 14 bits of memory. Then, #e can measure an amount of
combinational logic that can be fitted in the slice by calculating the total number of )*T bits.
Xilinx Virtex-4 slice
5ombinational logic density (in )*T bits) 67
8egister bits 7
Xilinx Virtex-5 Slices
The &irtex-. slices include(
Four LUTs ()oo$-*p Tables) that can be configured as 4-input )*Ts #ith 1-bit output or .-
input )*Ts #ith 7-bit output.
%hree dedicated user-controlled multiplexers for combinational logic (F9A-*%, F9"-*%
and F:-*%). F9A-*% and F9"-*% combine outputs of the slice/s )*Ts to implement
9-input combinational circuits. F:-*% is used to combine outputs of the F9A-*% and
F9"-*%.
0edicated arithmetic logic (t#o 1-bit adders and a carry chain).
Four 1-bit registers that can be configured either as flip-flops or as latches. The input to
these registers is selected by A-*% ; 0-*% multiplexers. 2ote that these multiplexers
aren/t user-controlled( the path is selected during FPGA programming.
The main differences from the pre!ious architecture(
Fig" &: A simpli'ied diagram o' a Xilinx Virtex-( FPGA slice
4-input
LUT
(G)
4-input
LUT
(F)
MUXFX
MUXF5
Arithmetic
and carry
logic
D
L!
D
L!
"
"
#
#
$%
$%
&MUX
XMUX
5onfigurable 4-to-1 or .-to-7 )*Ts instead of '-to-1 )*Ts.
' )*Ts and ' register bits per slice.
0edicated arithmetic logic circuitry doesn/t include dedicated A20 gate.
For example, it is possible in &irtex-. to implement a full '-to-1 multiplexer #ith <ust one )*T.
Xilinx Virtex-5 slice
5ombinational logic density (in )*T bits) 7.4
8egister bits '
Altera ALMs
Altera FPGAs (#tratix and )*clone families) uses slightly different logic bloc$s called +Adapti!e
)ogic -odules, (A)-s).
A)- resources include(
T#o 4-input LUTs and four 3-input LUTs for combinational logic implementation.
Fig" +: A simpli'ied diagram o' a Virtex-5 FPGA slice
LUT
LUT
LUT
LUT
Arithmetic and
carry logic
D
L!
#
$%
D
L!
#
$%
D
L!
#
$%
D
L!
#
$%
"
"
"
"
F'(MUX
F'AMUX
F)MUX
AMUX
(MUX
MUX
DMUX
0edicated arithmetic and carry logic.
To programmable registers.
=t should be noted that an A)- has only : inputs, #hich is less than a total number of )*T inputs.
This means that some input signals are connected to more than one )*T. There are se!eral input
signal multiplexers in the A)- that forms a $ind of interconnect matrix programmable by the user
(at the time of configuration). 2ote that not e!ery connection is possible. 8efer to the #tratix-IV
,e-ice .andboo/ for more details.
!ltera !L"
5ombinational logic density (in )*T bits) 4'
8egister bits 7
Actel VersaTile
Actel produces FPGAs mainly for aerospace and military applications. 5ompared #ith top %ilinx
and Altera de!ices, Actel FPGAs pro!ide less logic resources.
The basic building bloc$ for Actel flash-based FPGAs (such as ProA#I)-$) is called Versa%ile.
>ach &ersaTile cell can implement any of the follo#ing(
Any 6-input combinational logic function, ?8
0 flip-flop or latch.
Fig" $: A simpli'ied diagram o' the Altera A01
4-input
LUT
*-
input
LUT
*-
input
LUT
4-input
LUT
*-
input
LUT
*-
input
LUT
+nterconnect
matri,
Arithmetic and
carry logic
FF
FF
?ne &ersaTile can implement only one of these, not both. Therefore, for the purpose of our
comparison, #e #ill di!ide )*T and register bits by 7.
!ctel VersaTile
5ombinational logic density (in )*T bits) '
8egister bits @..
Conclusion
The architectures are !ery different, so it/s difficult to compare them ob<ecti!ely. =t should be
understood that the results of such comparison ha!e limited application.
=t is usually the number of )*Ts (and not the number of registers) that is a bottlenec$ for FPGA
designs. From this perspecti!e, it could be stated that one &irtex-. slice can in theor* substitute :
&irtex-' slices or ' A)-/s. "ut in real-#orld designs it is impossible to utiliAe all the resources.
>xperiments #ith real-#orld designs sho# the follo#ing approximate relationship bet#een
different FPGA logic bloc$s(
Logic bloc# Virtex-4 slices e$ui%alent
%ilinx &irtex-' slice (reference) 1
%ilinx &irtex-. slice 7
Altera A)- 1.6
Actel &ersaTile @.7.
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