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Me Question Paper
Me Question Paper
Applied Electornics
First Semester
Reg. No. :
2.
3.
4.
5.
6.
7.
8.
1.
10.
9.
PART B (5 16 = 80 Marks)
With an example explain the state assignment rules.
(ii)
Determine the minimal state equivalent of the state table given. (10)
Present
Next State/ Output
State
Input
Input
x=o
x=1
q
q /1
q /0
0
q /0
q /0
q2
q1/0
q5/0
q3
q1/0
q5/0
q4
q2/0
q6/1
q5
q2/0
q6/1
q6
q3/0
q7/1
q7
q3/0
(6)
(i)
(a)
q7/1
11.
Or
12.
Design a serial adder using mealy model and Moore model. Also draw the
ASM chart for both the models.
(16)
(a)
(b)
Or
(b)
(i)
(ii)
Present
State
Next State
Output
Z
Input Input
X=0 X=1
J7602
(a)
(i)
Derive the test vector to detect the stuck-at-0 fault at line 3 of the
following logic circuit using path sensitization method.
(8)
4
(ii)
13.
(8)
Or
(a)
(10)
(ii)
14.
(i)
(6)
(b)
Design a 4-bit serial - in, serial - out shift register and implement it using
suitable sequential PAL.
(16)
Or
(b)
(a)
(i)
(ii)
15.
Explain in detail the CLB and I/O block of a Xilinx 4000 series FPGA. (16)
(6)
Or
(b)
J7602