Sheet

1 of 17

Amplifier Design Tutorial

Introduction

This tutorial will set out the design stages required to design a theoretical microwave amplifier
with the following specification shown in Table 1:

Table 1 Required Specification

Parameter Units
Frequency 1.45 1.55 GHz
Gain 12.5 0.2 dB
Noise Figure 2.0 dB
Output VSWR 1:1.5 (>13dB)
Gain ripple < 1.5 dB

The first stage in the design process is to pick a suitable device. For X-Band and above GaAs
MESFETS are used while at lower frequencies Bipolar devices are used if noise is not so
critical. Try to pick a device design for the range of frequencies you require. Dont for example
use an X-band device for an LNA at UHF you are bound to run into stability problems. Also
pick a device that will give you plenty of gain margin to allow for noise mismatching etc.

For this design an Agilent AT41435 Bipolar transistor has been used. This device has >14dB
of gain at 2GHz with an associated noise figure of <1.7dB.

To double-check the gain available we can use a simple rule-of-thumb estimate by
evaluating

|S21|/|S12|.

At 1.5GHz this will be 4.63/0.063 =73.5 or 10*LOG(73.5) =18.6dB

We should easily meet the specification for overall gain and allow for significant output
mismatch to allow for gain equalisation and minimum noise. This estimation needs to be
checked against the stability factor K of the device as this effects the gain and gives an
indication to whether the device is likely to oscillate or not.

The device at 1.5GHz is unconditionally stable with a K of >1.

The ADS simulation shown in Figure 1 has been setup to calculate K factor and plot
minimum noise figure.



Sheet
2 of 17


StabFact
StabFact1
StabFact1=stab_fact(S)
StabFact
Term
Term2
Z=50 Ohm
Num=2
sp_hp_AT-41435_1_19921201
SNP1
Noise Frequency="{0.10 - 4.00} GHz"
Frequency="{0.10 - 6.00} GHz"
Bias="Bjt: Vce=8V Ic=10mA"
S_Param
SP1
CalcNoise=yes
Step=
Stop=2.0 GHz
Start=1.0 GHz
S-PARAMETERS
Term
Term1
Z=50 Ohm
Num=1

Figure 1 ADS simulation to calculate K and minimum noise figure. The resistor-
capacitor combination connected between the gate and source are to ensure that the
device is unconditionally stable at 1.5GHz.

m1
freq=1.526GHz
nf(2)=1.589
1.0 1.2 1.4 1.6 1.8 2.0
1.2
1.4
1.6
1.8
2.0
freq, GHz
nf(2)
m1
freq
1.000GHz
1.053GHz
1.105GHz
1.158GHz
1.211GHz
1.263GHz
1.316GHz
1.368GHz
1.421GHz
1.474GHz
1.526GHz
1.579GHz
1.632GHz
1.684GHz
1.737GHz
1.789GHz
1.842GHz
1.895GHz
1.947GHz
StabFact1
0.944
0.950
0.958
0.968
0.980
0.995
1.012
1.032
1.056
1.083
1.097
1.097
1.098
1.100
1.104
1.110
1.116
1.124
1.134

Figure 2 Results from the simulation shown in Figure 1, showing a K factor >= 1 at
1.4GHz and a minimum noise figure of 1.65dB at our highest frequency of 1.6GHz.


Sheet
3 of 17

General Amplifier Design Procedure

Now that we have picked our device, stabilised it and checked its maximum available gain we
can begin the process of designing the LNA. This process consists of the following steps:-

(1) Evaluate the Rolletts stability factor to identify the possibility of instabilities depending on
source and load matching.

(2) Determine Bias conditions and circuit.

(3) If a specified gain is required at a single frequency then the gain circles can be plotted on
a Smith chart and the associated source match can be read off and the corresponding load
match calculated. Careful consideration must be taken to the position of the source match in
relation to the stability circles.

(4) If a specified noise figure and gain at a frequency is required then the noise circles need to
be added to the gain circles from (ii). The source match required will be the intersection of the
required gain & noise circles. Again careful consideration must be given to the position of the
source match in relation to the stability circles.

(5) Once the required source impedance has been chosen the corresponding output match
required for best return loss can be calculated.

Gain & Noise Parameters

Using the S-parameters of the device it is possible to calculate the overall transducer gain
which consists of three parts, the gain factor of the input (source) matching network, the
active device and the output (load) matching network:-

2
22
L
2
o
2
11
s
L o s 10
2
22
2
L
2
o
2
2
s
S 1
1
G
21 G
S 1
1
G
- : following the to simplified be can
equations above the device) stable a (and 0 = S12 where case unilateral the For
) G . G . G ( 10LOG = gain Transducer Overall
. 1
1
G
21 G
. 1
1
G

=
=

=


=
=


=
S
S
S
L
s
s in
s



Sheet
4 of 17


For rough estimate of the maximum gain available we can assume that S12 =0 therefore at
1.5GHz (Assuming a bias of 8V @ 10mA) the estimated gain is:-

1.14dB = 1.29 =
0.48 - 1
1
=
S 1
1
G
13.31dB = 21.43 = 4.63 = S = G
0.68dB = 1.17 =
0.38 - 1
1
=
S 1
1
G
2 2
22
L
2 2
21 o
2 2
11
s

=


Total available gain =0.68 +13.31 +1.14 =15.13dB

Constant Gain circles

G . D 1
G . S . S + G . S . S 2K - 1
p circle gain of Radius
G . D 1
* G.C
= r circle gain of Location
S
dB) in not ie (absolute desired Gain
= G = Gain
* S S C
S D
2
2
2
21 12 21 12
o
2
2
o
2
21
11 22 2
2 2
22 2
+
=
+
=
=


Note the 0dB gain circle will always pass through the centre of the Smith chart.



Sheet
5 of 17

Constant Noise circles

Formula for calculation of noise circles:-

( )

1 + N
- 1 + N N
= is circle figure noise the of radius the and
1 N
= circle figure noise of Centre
noise optimum achieve to t coefficien Reflection =
transistor of resistance noise Equivalent = R
) 10 = factor (noise figure noise Optimum F
) 10 = factor (noise figure noise required = F Where
1
Zo
4R
F - F
= N
2
N
10
dB NF
min
10
NFdB
2
N
min
min
opt
opt
opt
opt

=
+

The values of F
min
, R
N
and
opt
are given in the manufacturers data sheet.

However remember that that the parallel feedback resistor will now have modified the device
noise parameters.

Calculating these circles by hand is luckily not required these days, as this can be
performed using the CAD simulator but before we progress to gain & noise we need to
check on the stability of the device.
Refer to the stability tutorial for a discussion of stability circles etc.


Sheet
6 of 17

Specifically we need to find the no-go matching zones that may cause the circuit to oscillate if
we place these matches to the device. Again this is best performed using the CAD the ADS
simulation shown in Figure 3 has the basic FET device with stability circle simulation boxes.

S_StabCircle
S_StabCircle1
S_StabCircle1=s_stab_circle(S,51)
SStabCircle
S_Param
SP1
CalcNoise=yes
Step=
Stop=2.0 GHz
Start=1.0 GHz
S-PARAMETERS
Term
Term2
Z=50 Ohm
Num=2
sp_hp_AT-41435_1_19921201
SNP1
Noise Frequency="{0.10 - 4.00} GHz"
Frequency="{0.10 - 6.00} GHz"
Bias="Bjt: Vce=8V Ic=10mA"
Term
Term1
Z=50 Ohm
Num=1



Figure 3 ADS setup to simulate the Agilent AT41435 using a S-parameter simulator and
output the input stability circles.

The results from the ADS simulation (Figure 3) shows that the device is conditionally stable
as the stability circles clip the edge of the smith chart so that there is a possibility of instability,
if a match is placed on the device source with an impedance within the area of the smith chart
covered by the stability circle (as shown by the shaded area).


S_StabCircle1=1.009 / 179.579
freq=1.315789GHz
impedance = Z0 * (-0.004 + j0.004)
indep(S_StabCircle1) (0.000 to 51.000)
S_
St
ab
Cir
cle
1
m1

Figure 4 Result of the circuit simulation showing the input stability circles. The stability
circles are outside the smith chart so that for any match applied to the device, the
device will be unconditionally stable.



Sheet
7 of 17

We can now plot the gain circles and noise circles. The idea is to choose a matching point on
the 10dB source and load constant gain circles and ensure the input matching point is either
on the 2dB noise circle or within it.

To perform the simulation we need to add the gain mismatch and noise mismatch simulator
boxes, note too that the noise feature has been switched on in the S-parameter simulator box.
The simulation is shown in Figure 5.


S_Param
SP1
CalcNoise=yes
Stop=3.5 GHz
Start=0.5 GHz
S-PARAMETERS
sp_hp_AT-41435_1_19921201
SNP1
Noise Frequency="{0.10 - 4.00} GHz"
Frequency="{0.10 - 6.00} GHz"
Bias="Bjt: Vce=8V Ic=10mA"
SmZ1
smz1
smz_in=sm_z1(S,PortZ1)
smz_out=sm_z2(S,PortZ2)
Eqn
Meas
SmGamma2
smg2
match_output=sm_gamma2(S)
Eqn
Meas
SmGamma1
smg1
match_input=sm_gamma1(S)
Eqn
Meas
Term
Term2
Z=50 Ohm
Num=2
Term
Term1
Z=50 Ohm
Num=1

Figure 5 ADS simulation showing the modified S-parameter simulation box set to
include noise. The other measurement boxes are:

SmGamma1 which, returns the simultaneous-match input-reflection coefficient.
SmGamma2 which, returns the simultaneous-match output-reflection coefficient.
Sm_z1 which, returns the simultaneous-match input impedance.


Sheet
8 of 17

Eqn num_NFci rcl es=4
Eqn NFstep_si ze=.1
Eqn Noi se_ci rcl es=ns_ci rcl e(NFmi n[m2]+NFstep_si ze*[0::num_NFci rcl es],NFmi n[m2],Sopt[m2],Rn[m2]/50,51)
Eqn GAstep_si ze=1
Eqn GAci rcl es=ga_ci rcl e(S[m2],max_gai n(S[m2])-GAstep_si ze*[0::num_GAci rcl es])
Eqn GAci rcl eMax=ga_ci rcl e(S[m2],max_gai n(S[m2]))
Eqn num_GAci rcl es=6
Eqn Noi se_ci rcl eMi n=ns_ci rcl e(NFmi n[m2],NFmi n[m2],Sopt[m2],Rn[m2]/50,51)
Set step sizes and
number of circles, here.
m1
i ndep(m1)=4
GAci rcl es=0.337 / 48.137
gai n=12.759112
i mpedance = Z0 * (1.335 + j 0.75
m3
i ndep(m3)=3
Noi se_ci rcl es=0.399 / 42.894
ns fi gure=1.900000
i mpedance = Z0 * (1.463 + j 0.94
indep(GAcircleMax) (0.000 to 51.000)
a
x
G
A
c
i
r
c
l
e
M
cir_pts (0.000 to 51.000)
G
A
c
i
r
c
l
e
s
m1
indep(Noise_circleMin) (0.000 to 51.000)
N
o
i
s
e
_
c
i
r
c
l
e
M
i
n
N
o
i
s
e
_
c
i
r
c
l
e
s
m3
m2
i ndep(m2)=1500000000.000
vs([0::sweep_si ze(freq)-1],freq)=33.000
4
0
0
.
M
6
0
0
.
M
8
0
0
.
M
1
.
0
0
G
1
.
2
0
G
1
.
4
0
G
1
.
6
0
G
1
.
8
0
G
2
.
0
0
G
2
.
2
0
G
2
.
4
0
G
2
.
6
0
G
2
.
8
0
G
3
.
0
0
G
3
.
2
0
G
3
.
4
0
G
3
.
6
0
G
0
20
40
60
80
100
freq, Hz
[
0
:
:
s
w
e
e
p
_
s
i
z
e
(
f
r
e
q
)
-
1
]
m2
RF Frequency Selector

Figure 6 Data display setup to plot gain and noise circles. The slider m2 on the
frequency selector can be moved to display the noise and gain circles at other
frequencies.

















Sheet
9 of 17


m1
indep(m1)=4
GAcircles=0.337 / 48.137
gain=12.759112
impedance = Z0 * (1.335 + j0.755)
m3
indep(m3)=45
Noise_circles=0.252 / -30.384
ns figure=1.900000
impedance = Z0 * (1.490 - j0.406)
indep(GAcircleMax) (0.000 to 51.000)
GAcircleMax
cir_pts (0.000 to 51.000)
GAcircles
m1
indep(Noise_circleMin) (0.000 to 51.000)
Noise_circleMin
Noise_circles
m3

Figure 7 The diagram shows a smith chart with constant gain and noise circles plotted.
The brown circles show the constant noise circles with the blue dot showing the
optimum noise point.
The red circle shows the constant maximum available gain and the green circles are
the constant gain circles. Marker 1 has been placed on the 12.5dB constant gain circle
with the 2.0dB constant noise circle is indicated by marker 3. If we place a load at
marker 1 ie an impedance of 1.335+j0.75 to the input of the Bipolar transistor then we
should have an amplifier with 12.5dB of gain and a noise figure of <2.0dB.

Figure 7 Shows the constant gain and noise circles plotted at 1.5GHz. Marker 1 has been
placed on the 12.5dB gain circle and marker 3 has been placed on the 1.9dB noise circle.
Referring back to the stability circle plots of Figure 4 we can see that our required matching
point is clear of any unstable regions.

Clearly then the noise figure at our designated matching point should be lower than 1.9dB as
it is within the 1.9dB constant noise circle.

We can now generate our input matching circuit.


Sheet
10 of 17


The input matching circuit can be drawn onto a smith chart or it can be synthesised using the
CAD. Using a program called WinSmith the input matching circuit has been generated using
ideal micro-strip lines defined by electrical length (these electrical lengths then need to be
converted to physical lengths depending on the characteristics and dimensions of the micro-
strip substrate used.

Figure 8 Shows the WinSmith design of the input matching circuit design to provide a load of
1.335+j0.755 ohms (ie 66.8+j37.8 ohms normalised to 50 ohms) to the base of the AT41435.


Figure 8 WinSmith plot of the proposed input matching circuit designed to present a
load of 66.8+j37.8 ohms to the input of the AT41435. The line length from the FET gate
to the stub is 102 degrees long and the stub has an electrical length of 36 degrees.

We can now simulate the circuit with the input matching circuit added to see if we get close to
the required gain and noise figure. To do this the ideal transmission lines have been
converted into real micro-strip transmission lines (Er=9.9,H=25thou) using LineCalc. The
ADS schematic is shown in Figure 9.



Sheet
11 of 17

MSUB
MSub1
Rough=0 mm
TanD=0
T=0 mm
Hu=1.0e+033 mm
Cond=1.0E+50
Mur=1
Er=9.6
H=25 mil
MSub
MLEF
TL2
L=7.96 mm
W=0.56 mm
Subst="MSub1"
MLIN
TL1
L=22.5 mm
W=0.56 mm
Subst="MSub1" Term
Term1
Z=50 Ohm
Num=1
sp_hp_AT-41435_1_19921201
SNP1
Noise Frequency="{0.10 - 4.00} GHz"
Frequency="{0.10 - 6.00} GHz"
Bias="Bjt: Vce=8V Ic=10mA"
S_Param
SP1
CalcNoise=yes
Step=
Stop=1.55 GHz
Start=1.45 GHz
S-PARAMETERS
Term
Term2
Z=50 Ohm
Num=2

Figure 9 ADS schematic of LNA with real matching circuit added to the input.
m2
freq=1.500GHz
dB(S(2,1))=11.887
1.44 1.46 1.48 1.50 1.52 1.54 1.56
11.4
11.6
11.8
12.0
12.2
12.4
12.6
freq, GHz
d
B
(
S
(
2
,
1
)
)
m2
m1
freq=1.550GHz
nf(2)=1.975
1.44 1.46 1.48 1.50 1.52 1.54 1.56
1.6
1.7
1.8
1.9
2.0
freq, GHz
n
f
(
2
)
m1
m3
freq=1.501GHz
dB(S(2,2))=-8.061
1.44 1.46 1.48 1.50 1.52 1.54 1.56
-8.3
-8.2
-8.1
-8.0
-7.9
-7.8
freq, GHz
d
B
(
S
(
2
,
2
)
)
m3

Figure 10 Resulting simulation from the ADS schematic shown in Figure 9. As we can
see the gain and noise figures dont quite meet the requirements across our band of
interest. However we have not added the load matching circuit, which we can now
calculate as the device is unconditionally stable.



Sheet
12 of 17

The current design has no matching on the output and as we require a good output return
loss we should match to S22* - Note S22 will now have been modified by adding the input
matching circuit and will have to design the matching circuit to be the conjugate of S22
modified (This is because S22 is looking into the device and the conjugate will looking
towards the matching circuit.

In order to improve the gain and noise response we need to provide the R
L
=R
OUT
* given by:

*
opt 11
opt 21 12
22 OUT L
. S 1
. .S S
S * R R

+ = =
freq
1.000GHz
1.100GHz
1.200GHz
1.300GHz
1.400GHz
1.500GHz
1.600GHz
1.700GHz
1.800GHz
1.900GHz
2.000GHz
S(1,1)
0.400 / -152.000
0.396 / -158.400
0.392 / -164.800
0.388 / -171.200
0.384 / -177.600
0.380 / 176.000
0.382 / 174.000
0.384 / 172.000
0.386 / 170.000
0.388 / 168.000
0.390 / 166.000
S(2,1)
6.730 / 85.000
6.310 / 82.200
5.890 / 79.400
5.470 / 76.600
5.050 / 73.800
4.630 / 71.000
4.412 / 68.800
4.194 / 66.600
3.976 / 64.400
3.758 / 62.200
3.540 / 60.000
S(1,2)
0.049 / 56.000
0.052 / 56.600
0.055 / 57.200
0.057 / 57.800
0.060 / 58.400
0.063 / 59.000
0.066 / 58.800
0.070 / 58.600
0.073 / 58.400
0.077 / 58.200
0.080 / 58.000
S(2,2)
0.510 / -30.000
0.504 / -30.400
0.498 / -30.800
0.492 / -31.200
0.486 / -31.600
0.480 / -32.000
0.476 / -33.000
0.472 / -34.000
0.468 / -35.000
0.464 / -36.000
0.460 / -37.000


Calculation is long winded but has been included here for completeness:



Sheet
13 of 17

( )
( )
( ) ( )
( ) ( )
( ) ( )
*
*
OUT L
1 - 2 2
*
OUT L
*
OUT L
opt
*
opt 11
opt 21 12
22 OUT L
173.3 089 . 0 32 - 0.48
67 . 4 095 . 1
178 0.098
32 - 0.48 * R R
67 . 4
092 . 1
089 . 0
tan 095 . 1 089 . 0 092 . 1 r
polar to back convert j0.089 1.092 j0.089 - 0.092 - j0 1 be will term bottom the So
j0.089 0.092 - 44) j0.128sin( 4) 0.128cos(4 -
jb a - ie quadrant 3rd the in be will which cartesian to 224 0.128 convert to need We
224 128 . 0 1
178 0.098
32 - 0.48 * R R
48 0.337 * 176 381 . 0 1
48 0.337 * 71 4.63 * 59 0.063
32 - 0.48 * R R
48 0.337 s
. S 1
. .S S
S * R R
+ =

+ = =
=

= = + = =
+ = +
=

+ = =

+ = =
= =

+ = =

( ) 37 0.402 244 . 0 32 . 0 244 . 0 32 . 0 Rout Therefore
244 . 0 32 . 0 ) 01 . 0 088 . 0 ( ) 254 . 0 407 . 0 ( R have we So
j0.01 0.088 -
6.7) j0.089sin( .7) 0.089cos(6 173.3) - 180 j0.089sin( 173.3) - 80 0.089cos(1 jsin cos r
jb a ie sector 2nd the be will cartesian to 3.3 7 1 0.089 Convert
j0.254 - 0.407 2) j0.48sin(3 - ) 0.48cos(32 jsin cos r
jb - a ie sector 4th the be will cartesian to 32 - 0.48 Convert
*
L
= + = =
= + + =
+
= + = + = +
+
= = +
+
j j
j j j




The required output match is similar to the input match set for gain & noise performance. The
electrical lengths were found to be line length =100 deg with a stub of 39 degrees. The ADS
simulation of the complete amplifier is shown in Figure 11, with the resulting plots of the
simulation shown in Figure 12.



Sheet
14 of 17

MLEF
TL4
L=8.6 mm
W=0.56 mm
Subst="MSub1"
MLIN
TL3
L=22 mm
W=0.56 mm
Subst="MSub1"
MLIN
TL1
L=21.2 mm
W=0.56 mm
Subst="MSub1"
MLEF
TL2
L=7.6 mm
W=0.56 mm
Subst="MSub1"
sp_hp_AT-41435_1_19921201
SNP1
Noise Frequency="{0.10 - 4.00} GHz"
Frequency="{0.10 - 6.00} GHz"
Bias="Bjt: Vce=8V Ic=10mA"
Term
Term1
Z=50 Ohm
Num=1
S_Param
SP1
CalcNoise=yes
Step=
Stop=1.55 GHz
Start=1.45 GHz
S-PARAMETERS
Term
Term2
Z=50 Ohm
Num=2
MSUB
MSub1
Rough=0 mm
TanD=0
T=0 mm
Hu=1.0e+033 mm
Cond=1.0E+50
Mur=1
Er=9.6
H=25 mil
MSub

Figure 11 ADS simulation of complete amplifier with real micro-strip input and output
matching circuits.


Sheet
15 of 17

m2
freq=1.500GHz
dB(S(2,1))=12.716
1.44 1.46 1.48 1.50 1.52 1.54 1.56
12.2
12.4
12.6
12.8
13.0
13.2
13.4
freq, GHz
d
B
(
S
(
2
,
1
)
)
m2
m1
freq=1.550GHz
nf(2)=1.924
1.44 1.46 1.48 1.50 1.52 1.54 1.56
1.65
1.70
1.75
1.80
1.85
1.90
1.95
freq, GHz
n
f
(
2
)
m1
m3
freq=1.501GHz
dB(S(2,2))=-34.519
1.44 1.46 1.48 1.50 1.52 1.54 1.56
-45
-40
-35
-30
-25
-20
freq, GHz
d
B
(
S
(
2
,
2
)
)
m3

Figure 12 Simulation of the complete amplifier as shown in the schematic of Figure 11.
Here we can see that we have a gain of 12.7dB and gain ripple of 1.02dB and
associated noise figure of 1.77dB at 1.5GHz (worst-case noise figure is at band-edge at
1.92dB.
The output return loss is >20dB at 1.45GHz.



Sheet
16 of 17


Final design

To physically realise the design we need to add the RF bias circuits and DC blocks. The RF
bias circuits consist of wave inductive lines connected to a wave capacitive open-circuit
stub (See tutorial on Bias Circuits for more details).

The final schematic layout of the amplifier together with the RF bias circuits is shown in Figure
13.

As a final check it is a good idea to perform a wide-band analysis of the circuit to ensure that
at all frequencies S11 and S22 <0. The wide-band plots of the circuit are shown in Figure 14.



AT41435
L =7.6mm (36)
L =21.2mm (102)
L =22mm(100)
L =8.6mm (39)
50-ohm chip resistor
Base Bias
Collector Bias

Figure 13 Final Amplifier schematic layout with RF bias circuits added, together with
blocking capacitors.


As can be seen although the pass-band amplifier response is compliant with a pass-band
gain ripple of <1.5dB, output return losses and noise figure (at a maximum values of ~20 dB
& 1.9dB) are also compliant.

The wide-band plots show that the return losses are always <0dB and this should ensure a
stable amplifier design.



Sheet
17 of 17


m2
freq=1.503GHz
dB(S(1,1))=-2.971
0 1 2 3 4 5 6 7 8 9 10
-20
-15
-10
-5
0
m2
m1
freq=1.503GHz
dB(S(2,2))=-32.085
0 1 2 3 4 5 6 7 8 9 10
-40
-30
-20
-10
0
freq, GHz
d
B
(
S
(
2
,
2
)
)
m1
freq, GHz
d
B
(
S
(
1
,
1
)
)

Figure 14 Results of S11 and S22 for the amplifier over a broad-band width (0.5 to
10GHz). The output return is very good as we specifically matched the output to give a
good-return loss. As the input was mismatched to give a particular gain & noise figure
the resulting return loss is poor. If this is deemed a problem, then either a balanced
amplifier be used or an isolator added (NOTE in both cases this would add ~ 0.5dB to
the noise figure of the amplifier).