Substrate Noise Coupling Analysis in Mixed Signal ICs

Substrate Noise Coupling Analysis
In Mixed-Signal ICs
François J. R. Clément
francois@simplex.com
© Copyright 2001 Simplex Solutions, Inc. 1
/ Substrate in Signal Integrity /
HSubstrate
HInterconnects
VSource ZVictim
HPackage

/ Lightly-Doped Substrate Isolation /
VNOISE VVICTIM 10k d [microns]
VGND 20 60 100 180
d d ]
23
P+ P+ P+ V 25
R1 R1 R1 B
d
[ 27
R2 R2 n
o
i 29
R3 t
a
l 31
o
P- Bulk s
I 33
• Lightly doped material Vvictim

• Maximum isolation when source and Isolation= 20log [dBV]
Vnoise
victim are closer to the guard band
• Bonding inductance will affect isolation
/ Noise Dependence on Distance to Ground /
Source
dSR Receiver
Test chip with

lightly-doped
substrate

/ Outline /
Introduction
– Problem Summary
– Various Parasitic Components
– Impact on the Design
• Technology
• Modeling
/ Substrate Crosstalk: the Problem /
3-D Complexity
Technology
Dependence
Trial & Error
Lost Time-to-Market

/ Device Parasitics /
Physical structure Equivalent model
Oxide Polysilicon
Bonding Wire
Diffusion
(substrate contact)
Substrate
With a total capacitance of 10 [pF] and an inductance of 4 [nH],

fR is 800 [MHz]
/ Crosstalk: Parasitic Return Path /

Perturbed Cell
Oxide
Forward Signal Path Metal
Signal Receiver
Signal Source Parasitic Return Path
Substrate

/ Crosstalk: Path to AC Ground /
Noise Source
Diffusion
Parasitic Path to AC Ground (Substrate Contact)
Substrate
/ WARNING !!! /
• Noise coupling is context dependant
• All presented test cases have specific

backgrounds
• Given examples are not provided as final

design rules

/ Outline /
• Introduction
Technology
– Semiconductor Physics
– Wafer Impact
– Fabrication Process
• Modeling
/ Assumptions /
• Circuit is functioning normally
– Well-substrate junctions are reverse biased
– No parasitic surface inversion
– Latch-up under control
• Inductive coupling is neglected inside silicon
– Much smaller than resistive or capacitive coupling

/ Basic Properties /
• Permitivity: εSi = 1.035 [pF/cm]
• Permeability: µSi = 4π [nH/cm]
• Resistivity: σ = q(pµp+nµn)
/ Outline /
• Introduction
Technology
– Wafer Impact
• Modeling

/ Lightly-Doped Wafer /
)s
)s n
n or
or ic
re ic m
fa m 00 ρ
w 0 :
T 0 8 ρ
silicon
4 ~
(
lightly doped (~12 ohm-cm) :
~
epoxy
( re conductive
ei f
d a or isolating
ε oxide
/ Lightly-Doped Wafer Resistivity /

1 2
d«T Wafer
T Wafer
RSubstrate
1 2
R(d) = R 1
; R(2*d) = R : R < 2 * R
2 2 1
Non-conductive Backside
/ Lightly-Doped Substrate Isolation /
VNOISE VVICTIM 10k d [microns]
VGND 20 60 100 180
d d ]
23
P+ P+ P+ V 25
R1 R1 R1 B
d
[ 27
R2 R2 n
o
i 29
R3 t
a
l 31
o
P- Bulk s
I 33
• Lightly doped material Vvictim

• Maximum isolation when source and Isolation= 20log [dBV]
Vnoise
victim are closer to the guard band
• Bonding inductance will affect isolation
/ Lightly-Doped Wafer Resistivity /

5
Non-conductive Epoxy
Conductive Epoxy
4
]
Ω
k[ 3
ec
na
ts
is
eR 2
0
0 200 400 600 800
Distance [µm]
/ Epitaxial Wafer (Heavily-Doped Bulk) /
i
pe
ρsilicon:
T lightly doped (~12 ohm-cm)
kl
ub ρsilicon: ρepoxy:
T heavily doped (~0.01 ohm-cm) conductive
or isolating
εoxide
/ Parasitic Return Path: Skin Effect /
Oxide Metal Jsurface

Forward Signal Path Jsurface
0 e
0
Signal Receiver Tskin
Signal Source Parasitic Return Path
2*Tskin
Substrate
ρ
Tskin = [cm] with r [W⋅cm], m [H] and f [Hz]
πµ f

/ Skin Effect /
/ Wafer Impact Summary /
• Lightly Doped
– Isolation increase with distance with non-conductive
backside
– Backside contact with limited efficiency
– Resistive mesh model
• Heavily-Doped
– Distance doesn’t provide isolation
– Careful substrate grounding
– Backside contact efficient (at high frequency?)
– Simple model

/ Outline /
• Introduction
Technology
– Wafer Impact
• Modeling
/ Process Parameters /
sinker field implant

(~0.005 ohm-cm) (~0.2 ohm-cm)
contact well
(~0.005 ohm-cm) deep
trench (~1 ohm-cm)
p +
p )s
no
p + n rci
buried m
5~
layer
(~0.005
p +
n +
(s
se
ohm-cm) co
p substrate
-
rp
(~12 ohm-cm) T
F.Clement in J. Huijsing et al, KAP, ‘99
/ Lightly-Doped: Channel Stop Break /
depletion
p channel stop
region
V
dd
n well
Substrate
p
- substrate
Current
Depletion increases with Vdd causing well-substrate capacitance to decrease

/ Breaking the Buried Layer /

deep trench n well
(~1 ohm-cm)
p epitaxial layer
(~1 ohm-cm)
Tepi (~3 um)

p buried layer
Tburied (~1 um)
+
(~0.005 ohm-cm
Tbulk (~400 um)

p wafer
-
(~12 ohm-cm)
n buried layer
+
(0.005 ohm-cm)
/ NMOST: Triple Well Isolation /
n sinker
(~0.005 ohm-cm)
p epitaxial layer
(~1 ohm-cm)
N+ N+
T epi
(~3 um)
p buried layer
T
+
buried
(~1 um) (~0.005 ohm-cm)
T bulk
(~400 um)
p wafer
-
(~12 ohm-cm)
n buried layer
+
(~0.005 ohm-cm)
/ Triple Well Isolation /
• Behavior changes with buried layer doping

– Heavily doped layer
• Partially depleted Noise Junction Noise
• Can be biased through sinkers source capacitances victim
– Lightly doped layer
• Fully depleted
• Beyond 1 GHz isolation depends on

– Respective doping levels
P- N P
– Junction biasing substrate well well

/ Technology: Conclusion /
• Significant Wafer Influence
– Doping Variations
– Backside Connection
• Fabrication Process
– Surface Implants
– Well-Substrate Junctions
– Buried Layers
/ Available Processes /
• Memory, RF Processes
– Lightly-Doped Bulk
• aka High-Resistivity or Bulk CMOS
• Digital Processes
– Heavily-Doped Bulk with Lightly-Doped Epitaxial Layer

• aka Low-Resistivity or Epitaxial Substrate or Standard CMOS
• Bipolar / BiCMOS Processes
– Lightly-Doped Bulk and Epitaxial Layer with Heavily-Doped

Buried Layers

/ Available Foundry Processes /
• Lightly-Doped Bulk
– All TSMC & UMC Processes
– IBM (7SF)
• Heavily-Doped Bulk
– Option for All TSMC & UMC Processes
– STMicroelectronics (HCMOS9)
– IBM (5SF, 6SF)
• Lightly-Doped with Heavily-Doped Buried Layers
– STMicroelectronics (BICMOS6G)
– IBM (4S, 5S, 5HP, 6HP)
http://www.tsmc.com/technology/index.html
http://www.umc.com/english/process/
http://eu.st.com/stonline/prodpres/dedicate/asic/liban.htm
http://www-3.ibm.com/chips/techlib/techlib.nsf/pages/main
/ Outline /
• Introduction
• Technology
Modeling
– Generation
– Isolation
– Sensitivity

/ Sources of Substrate Noise /
• Inductive Noise (di/dt, 100 mV)
• Bonding wires
• Large di/dt on power supplies
• Non-ideal power supplies connecting directly to the
substrate
• Capacitive Coupling (dv/dt, 10 mV)
• Interconnect capacitance to substrate

• Junction capacitances
• Impact Ionization (Idrain, Vgs & Vds, 2 mV)
• High electric field near the drain of saturated MOS

devices
• Substrate current injection
/ Inductive Noise /
bond
wire package
trace
chip
di
package V =L
di
dt
dt
Board Gnd Chip Gnd
L
• L changes with:
• Type of package
• Number of pins for a connection

/ Capacitive Noise /
Line CL-L Line
MOST CL-S CL-W
dv
CN-P Well
dt
dv
i=C CW-S
dt
Substrate
Large capacitance to substrate (supply, buses, output drivers, clock, etc.):

Shielding reduces some values
/ Reducing Noise Generation /
• Avoid switching of large capacitive nodes
– The direct coupling into the substrate may be

decreased
– At the same time supply bounce is reduced
– Shielding helps reducing injection into the substrate
• Minimize the instantaneous current
– Slow rise and fall times

– Stagger the timing of output drivers or large blocks of
circuitry
– Lower the voltage swing
– Keep package inductance as low as possible
– Use separate power supply for largest current drivers
• Turn off functions not in use

/ Equivalent Switching-Capacitance Model /
V(f)
N+
P
CEquiv
f = frequency of noise
rise and fall times are important

substrate
T. Blalack in J. Huijsing et al, KAP, ‘99
P. T. M. van Zeijl in proceedings of 38th DAC, IEEE, ‘01
/ Noise Generation: Macro Model /
Detailed Model Macro Model
SPICE Simulation
M. van Heijningen et al, DAC‘00

/ Outline /
• Introduction
• Technology
Modeling
– Generation
– Isolation
– Sensitivity
/ Isolation /
• Techniques vary dramatically between
heavily and lightly-doped substrates.
• Distance isolation is difficult to achieve in
both cases.
• Separate analog and digital supplies.
– Multiple sets of supplies may be necessary to

further divide circuit blocks
– Package inductance together with pin
assignment is critical

/ Heavily-Doped Bulk Acts as Single Node /
Well PMOST NMOST Substrate

Contact Contact
N+ P+ P+ N+ N+ P+
N-well
P+ channel stop
P- Epitaxial layer implant
P+ Bulk
Well Substrate
Contact Contact
Cwell Repi2 Repi3
Repi1 Bulk Node
© Copyright 2001 Simplex Solutions, Inc. D. Su et al., JSSC, April 1993 41
/ Heavily-Doped Substrate Connections /
Vsub Vsub
Substrate Substrate
Contact Contact
P+ P+
P- Epitaxial layer
Repi1 Repi2
Bulk Node
Substrate
P+ Bulk
• Connect substrate to “quiet” supply only
• Minimize inductance

/ Guard Rings in an Heavily-Doped Bulk /
Vss Vss
P+ N+ N+ P+ P+ • Separate pin
A
provides some
P- Epi
benefit
P+ Bulk
Vss
P+ N+ N+ P+ P+ • Connection to
B
substrate contacts
P- Epi
can make things
worse
P+ Bulk
/ Lightly-Doped Substrate Connections /

Substrate Substrate
Vsub Contacts Contacts Vsub
P+ P+ P+ P+
Rbulk Rbulk
Risolation
P- Bulk
• Use multiple supplies to isolate areas

• Minimize inductance
/ Guard Rings in a Lightly-Doped Process /
AGnd AVdd DGnd
P+ N+ N+ P+ N+ P+
N Well
P channel
stop implant
P- Bulk
• Guard rings are more effective in a lightly doped process

• A well region will increase the isolation
/ Noise Dependence on Distance to Ground /
Noise
[V]
Source dSR Receiver
dSG dRG
Ring Osc.
Contact
to Ground
dSG +d RG d SR
[µm] [µm]
Test chip with

lightly-doped
substrate
/ Other Conductive Path /
R2 Sensitive
Asub
Dsub
R1 ANALOG
Substrate
contacts
DIGITAL
Noisy
Equivalent behavior with pad or seal ring !!!

/ Careful Floorplanning /
• Package inductance needs to be minimized for power

supplies directly connected to substrate
• Seal and pad rings affect noise transfer
• Digital signals should not
– be routed over or through the analog portion of the chip
– be routed next to sensitive lines
• The floorplan should ensure that the package pin
assignments do not route sensitive analog signals near
digital I/Os, supplies, or clock signals

/ Heavily-Doped Bulk Simplified Model /
b
Epitaxial layer
a (repi ~ 20 ohm-cm)
Tepi Repi
Heavily doped bulk
(~ 0.01 ohm-cm)
• Area: A = (a + d)(b + d) Perimeter: P = 2(a + b + 2d)

• Repi = Rarea + Rperimeter = (k1 repi / A) // (k2 repi / P)
• k1, k2 and d from measurement
D. Su et al., JSSC, April 1993
Model Extraction Strategy
Technology
Technology
description
description Layout
Layout
IN
3-D
3-DModel
Model
OUT
Electrical
Electrical Visual
Visual
simulation
simulation analysis
analysis

/ Modeling the Substrate /
Bonding Wire
Noise Source Noise Victim
P+ contacts Nwell
N+ contact
• Substrate Abstract View Definition
- Process regions (wells, buried layers, deep trenches, …)
- Ports connecting the ideal circuit to the substrate
- Equivalent ideal circuit model for interactive visual analysis
• RC Model Extraction
}
/ Automated 3D Modeling /
poly LAYOUT
p+
nwell interconnect
y contact device
x
)s
p+ S leif
z nwell So
E rp
Cg
p-substrate Oni
Rp
P od
(

/ RC Extraction /
• Finite elements (FEM)
– Exact solution using Poisson and Continuity Equations

• Finite differences (FDM)
– No carrier diffusion
– Simple RC model applied on 3D Mesh
• Boundary element method (BEM)
– No carrier diffusion
– No lateral doping variation
– Only port-to-port relationship needs to be modeled
/ FDM vs. BEM: Triple-Well Model /
FDM BEM
Triple-well
bias Triple-well
bias
P- P+ N+ electrical node
/ Outline /
• Introduction
• Technology
Modeling
– Generation
– Isolation
– Sensitivity
/ Effects of Substrate Noise /
• Operating conditions
• Threshold voltage
• Junction capacitance
• Bias current
• Degradations
• Gain, bandwidth
• Jitter, phase noise
• Noise figure, RF intermodulation
• Failures
• Latchup

/ Desensitizing the Listener /
• Fully differential circuitry
• High common-mode rejection (CMRR)
• High power supply rejection (PSRR)
• Layout symmetry
– common-centroid may be required for matching of critical
components
• Analog clocks
– minimize supply noise for last stage clock drivers
/ Input Gate Capacitance /
Gate Gate-to-Source
Gate-to-Channel
Capacitance Overlap Capacitance
Source Drain

/ Clock Noise Coupling into the Signal Path /
φ φ
Ap Ap
2.6 V 4.0 V
VCM VCM
2.4 V 1.0 V
Am Am
φ φ
Common-Mode Coupling Differential Coupling
/ Supply Noise Coupling to Clock Lines /
vi

/ Modeling: Conclusion /
• Generation
– Performance & capacity issue
– Gate-level modeling
• Isolation
– Technology characterization
– Simple model for heavily doped bulk
– Mesh required for lightly doped
• Sensitivity
– Accuracy
– Transistor-level modeling
/ References /
BOOKS
• E. Carbon, R. Gharpurey, P. Miliozzi, R. G. Meyer, A. L. Sangiovanni-Vincentelli, Substrate Noise
Analysis and Optimization for IC Design, Kluwer Academic Publishers, 2001.
• X. Aragonès, J. L. González and A. Rubio, Analysis and Solutions for Switching Noise Coupling
in Mixed-Signal ICs, Kluwer Academic Publishers, 1999.
• T. Blalack, “Design Techniques to Reduce Substrate Noise,” Analog Circuit Design, pp. 193-218,
J. Huijsing et al. - Editors, Kluwer Academic Publishers, 1999.
• F. J. R. Clément, “Technology Impact on Substrate Noise,” Analog Circuit Design, pp. 173-192,
J. Huijsing et al. - Editors, Kluwer Academic Publishers, 1999.
• T. Schmerbeck, “Noise coupling in mixed-signal ASICs,” Low-power HF microelectronics: a
unified approach, pp. 373-430, G. Machado - Editor, IEE, 1996.
• N. Verghese, T. Schmerbeck, and D. Allstot, Simulation Techniques and Solutions for Mixed-
Signal Coupling in Integrated Circuits, Kluwer Academic Publishers, 1995.
• R. W. Dutton and Z. Yu, Technology CAD - Computer Simulation of IC Processes and Devices.
Kluwer Academic Publishers, 1993.
• R. M. Warner and B. L. Grung, Semiconductor-Device Electronics, Rinehart and Winston, Inc.,
1991.

/ References /
• J. Y. Chen, CMOS Devices and Technology for VLSI, Prentice-Hall, 1990.
• R. R. Troutman, Latchup on CMOS Technology - The Problem and Its Cure, Kluwer Academic
Publishers, 1986.
THESIS DISSERTATIONS
• R. Singh, “Efficient modelling of substrate noise and coupling in mixed-signal Spice designs”,
Thesis Dissertation, University of Newcastle upon Tyne Department of Electrical and Electronic
Engineering, October 1997.
• T. Blalack, “Switching Noise in Mixed-Signal Integrated Circuits”, Thesis Dissertation, Stanford
University Department of Electrical Engineering, December 1997.
• X. Aragonès, “A Contribution to the Study of Substrate Coupling in Mixed-Signal Integrated
Circuits”, Thesis Dissertation, Universitat Politècnica de Catalunya, Barcelona, October 1997.
• F. Clément, “Computer Aided Analysis of Parasitic Substrate Coupling in Mixed Digital-Analog
CMOS Integrated Circuits”, Thesis Dissertation No. 1449, Swiss Federal Institute of Technology,
Lausanne, 1996.
/ References /
JOURNAL AND CONFERENCE PAPERS
• D. Belot, “A DCS1800/GSM900 RF to Digital Fully Integrated Receiver in SiGe 0.35um
BiCMOS”, Bipolar/BiCMOS Circuits and Technology Meeting, October 2001.
• P. T. M. van Zeijl, “One-Chip Bluetooth ASIC Challenges”, 38th IEEE Design Automation
Conference, p. 262, June 2001.
• M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels and I. Bolsens, “High-Level Simulation
of Substrate Noise Generation Including Power Supply Noise Coupling”, 37th IEEE Design
Automation Conference, pp. 446-451, June 2000.
• R. Singh, “A Review of Substrate Coupling Issues and Modeling Strategies”, IEEE Custom
Integrated Circuit Conference, pp.491-498, May 1999.
• M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, “Modeling of
Digital Substrate Noise Generation and Experimental Verification Using a Novel Substrate Noise
Sensor,” in Proceedings of the ESSCIRC, pp. 186–189, 1999.
• R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal and J. P. Mattia, “R.F. MOSFET Modeling
Accounting for Distributed Substrate and Channel Resistances with Emphasis on the BSIM3v3
SPICE Model”, IEEE International Electron Devices Meeting, pp. 309-312, December 1997.
• R. Gharpurey and S. Hosur, “Transform Domain Techniques for Efficient Extraction of Substrate
Parasitics”, IEEE International Conference on Computer-Aided Design, pp. 461-467, December
1997.
/ References /
• J. Casalta, X. Aragones, and A. Rubio, “Substrate Coupling Evaluation in BiCMOS Technology,”
IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 598-603, April 1997
.
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Substrate Noise Coupling via Planar Spiral Inductor in RF ICs”, IEEE International Electron
Device Meeting, pp. 325-328, December 1997.
• M. Pfost, H. Rein, and T. Holzwarth, “Modeling Substrate Effects in the Design of High-Speed Si-
Bipolar ICs,” IEEE J. Solid-State Circuits, vol. 31, no. 10, pp. 1493-1501, October 1996.
• T. Blalack, J. Lau, F. Clement, and B. Wooley, “Experimental Results and Modeling of Noise
Coupling in a Lightly Doped Substrate,” IEEE International Electron Device Meeting, pp. 623-626,
December 1996.
• K. Makie-Fukuda, T. Kikuchi, T. Matsuura, and M. Hotta, “Measurement of Digital Noise in Mixed-
Signal Integrated Circuits,” IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 87-92, February 1995.
• T. Blalack and B. A. Wooley, “The Effects of Switching Noise on an Oversampling A/D
Converter”, IEEE International Solid-State Circuit Conference, pp. 200-201, February 1995. R.
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Analog/Digital Integrated Circuits,” IEEE International Electron Devices Meeting, pp. 433-436,
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/ References /
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Circuits”, IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 344-353, March 1996.
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and Their Application to Mixed-Signal IC Design”, IEEE J. Solid-State Circuits, vol. 31, no. 3, pp.
354-365, March 1996.
• A. Viviani, J. P. Raskin, D. Flandre, J. P. Colinge and D. Vanhoenacker, “Extended study of
crosstalk in SOI-SIMOX substrates,” IEEE International Electron Devices Meeting, pp. 713-716,
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Substrate Macromodels”, 32nd IEEE Design Automation Conference, pp. 439-444, June 1995.

/ References /
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Substrate Noise Coupling Analysis

© Copyright 2001 Simplex Solutions, Inc. 1

/ Substrate in Signal Integrity /

© Copyright 2001 Simplex Solutions, Inc. 2

• Lightly doped material Vvictim

© Copyright 2001 Simplex Solutions, Inc. 3

/ Noise Dependence on Distance to Ground /

Test chip with

© Copyright 2001 Simplex Solutions, Inc. 4

© Copyright 2001 Simplex Solutions, Inc. 5

/ Substrate Crosstalk: the Problem /

Trial & Error

© Copyright 2001 Simplex Solutions, Inc. 6

With a total capacitance of 10 [pF] and an inductance of 4 [nH],

© Copyright 2001 Simplex Solutions, Inc. 7

/ Crosstalk: Parasitic Return Path /

Signal Source Parasitic Return Path

© Copyright 2001 Simplex Solutions, Inc. 8

© Copyright 2001 Simplex Solutions, Inc. 9

• All presented test cases have specific

• Given examples are not provided as final

© Copyright 2001 Simplex Solutions, Inc. 10

© Copyright 2001 Simplex Solutions, Inc. 11

– Well-substrate junctions are reverse biased

– No parasitic surface inversion

– Latch-up under control

• Inductive coupling is neglected inside silicon

– Much smaller than resistive or capacitive coupling

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• Permitivity: εSi = 1.035 [pF/cm]

• Permeability: µSi = 4π [nH/cm]

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/ Lightly-Doped Wafer Resistivity /

• Lightly doped material Vvictim

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/ Lightly-Doped Wafer Resistivity /

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/ Parasitic Return Path: Skin Effect /

Oxide Metal Jsurface

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/ Wafer Impact Summary /

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sinker field implant

Depletion increases with Vdd causing well-substrate capacitance to decrease

/ Breaking the Buried Layer /

Tepi (~3 um)

Tbulk (~400 um)

/ Triple Well Isolation /

• Behavior changes with buried layer doping

• Beyond 1 GHz isolation depends on

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• Significant Wafer Influence

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– Heavily-Doped Bulk with Lightly-Doped Epitaxial Layer

– Lightly-Doped Bulk and Epitaxial Layer with Heavily-Doped

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• Inductive Noise (di/dt, 100 mV)

• Interconnect capacitance to substrate