Sram controller: 4Mbit (256k x16) SRAM 256k=2^18

module sram_ctrl(clk, wren, d, q, address, BHE, BLE, WE, CE, OE, IO, A);
input clk;
input wren;
input !"#$% d;
input !&#$% address;
output re' !"#$% q;

output re' BHE; (()*te write select input IO!"#$% (acti+e low)
output re' BLE; (()*te write select input IO&#$% (acti+e low)
output re' WE; ((write ena)le (acti+e low)
output re' CE; ((c,ip ena)le (acti+e low)
output re' OE; (( output ena)le (acti+e low)
inout !"#$% IO; (( data
output re' !&#$% A; (( address

re' io-oe;
re' !"#$% )u..er-d;

assi'n IO / io-oe 0 )u..er-d # !"1)2;

alwa*s 3 (posed'e clk)
)e'in
i. (wren)
)e'in (( write data
A 4/ address;
OE 4/ !;
CE 4/ $;
WE 4/ $;
BHE 4/ $;
BLE 4/ $;
io-oe 4/ !;
end
else
)e'in (( read data
A 4/ address;
CE 4/ $;
OE 4/ $;
BHE 4/ $;
BLE 4/ $;
WE 4/ !;
io-oe 4/ $;
end
)u..er-d 4/ d;
end

alwa*s 3 (ne'ed'e clk)
i. (wren//$)
)e'in (( read data
q 4/ IO;
end

endmodule
Behavioral code :
(555555555555555555555555555555555555555555555555555555555(
(( 6O78LE# 9:A6(:O6 Controller
((
(( ;ILE <A6E# sramcon-)e,=+
(( >E:9IO<# !=$
(( 7A?E# @anuar* !, !AAA
(( A8?HO:# Bo) 2eidman, 2eidman Consultin'
((
(( CO7E ?BCE# Be,a+ioral Le+el
((
(( 7E9C:IC?IO<# ?,is module implements a controller .or an
(( 9:A6 or :O6=
((
(555555555555555555555555555555555555555555555555555555555(
(( 7E;I<E9
Dde.ine 7EL ! (( ClockEtoEoutput dela*= 2ero
(( time dela*s can )e con.usin'
(( and sometimes cause pro)lems=
Dde.ine W:-CO8<? ! (( <um)er o. write c*cles needed
Dde.ine :7-CO8<? F (( <um)er o. read c*cles needed
Dde.ine C<?-BI?9 G (( <um)er o. )its needed .or t,e
(( counter to count t,e c*cles
(( ?OC 6O78LE
module sram-control(
clock,
reset-n,=
as-n,
rw,
out-en,
write-en,
ack);
(( I<C8?9
input clock; (( 9tate mac,ine clock
input reset-n; (( Acti+e low, s*nc,ronous reset
input as-n; (( Acti+e low address stro)e
input rw; (( :ead(write command
(( / ! to read
(( / $ to write
(( O8?C8?9
output out-en; (( Output ena)le to memor*
output write-en; (( Write ena)le to memor*
output ack; (( Acknowled'e si'nal to processor
(( I<O8?9
(( 9IH<AL 7ECLA:A?IO<9
wire clock;
wire reset-n;
wire as-n;
wire rw;
wire out-en;
wire write-en;
wire ack;
re' !#$% mem-state; (( 9tate mac,ine
re' DC<?-BI?9E!#$%cnt; (( C*cle counter
(( CA:A6E?E:9
parameter!#$% (( 9tate mac,ine states
I7LE / $,
W:I?E / !,
:EA7 / G;
(( A99IH< 9?A?E6E<?9
(( Create t,e outputs .rom t,e states
assi'n out-en / mem-state!%;
assi'n write-en / mem-state$%;
(( Create t,e acknowled'e com)inatoriall*
assi'n ID7EL ack / Jas-n KK ((Jrw KK (cnt // DW:-CO8<?E!)) LL
( rw KK (cnt // D:7-CO8<?E!)));
(( 6AI< CO7E
(( Look at t,e ed'e o. reset
alwa*s 3(reset-n) )e'in
i. (Jreset-n) )e'in
ID7EL assi'n mem-state / I7LE;
assi'n cnt / DC<?-BI?91,$;
end
else )e'in
ID7EL;
deassi'n mem-state;
deassi'n cnt;
end
end
(( Look at t,e risin' ed'e o. clock .or state transitions
alwa*s 3(posed'e clock) )e'in
case (mem-state)
I7LE# )e'in
(( Look .or address stro)e to )e'in t,e access
i. (Jas-n) )e'in
i. (rw) )e'in
(( ?,is is a read access
mem-state 4/ ID7EL :EA7;
end
else )e'in
(( ?,is is a write access
mem-state 4/ ID7EL W:I?E;
end
end
end
W:I?E# )e'in
(( I. we ,a+e reac,ed t,e .inal c*cle count
(( .or t,e access, t,e access is .inis,ed=
(( I. t,e address stro)e ,as )een deasserted,
(( t,e access is a)orted
i. ((cnt // DW:-CO8<?E!) LL as-n) )e'in
mem-state 4/ ID7EL I7LE;
cnt 4/ ID7EL DC<?-BI?91,$;
end
else
cnt 4/ ID7EL cnt M !;
end
:EA7# )e'in
(( I. we ,a+e reac,ed t,e .inal c*cle count
(( .or t,e access, t,e access is .inis,ed=
(( I. t,e address stro)e ,as )een deasserted,
(( t,e access is a)orted
i. ((cnt // D:7-CO8<?E!) LL as-n) )e'in
mem-state 4/ ID7EL I7LE;
cnt 4/ ID7EL DC<?-BI?91,$;
end
else
cnt 4/ ID7EL cnt M !;
end
endcase
end
endmodule (( sram-control
RTL code
(555555555555555555555555555555555555555555555555555555555(
(( 6O78LE# 9:A6(:O6 Controller
((
(( ;ILE <A6E# sramcon-rtl=+
(( >E:9IO<# !=$
(( 7A?E# @anuar* !, !AAA
(( A8?HO:# Bo) 2eidman, 2eidman Consultin'
((
(( CO7E ?BCE# :e'ister ?rans.er Le+el
((
(( 7E9C:IC?IO<# ?,is module implements a controller .or an
(( 9:A6 or :O6=
((
(555555555555555555555555555555555555555555555555555555555(
(( 7E;I<E9
Dde.ine 7EL ! (( ClockEtoEoutput dela*= 2ero
(( time dela*s can )e con.usin'
(( and sometimes cause pro)lems=
Dde.ine W:-CO8<? ! (( <um)er o. write c*cles needed
Dde.ine :7-CO8<? F (( <um)er o. read c*cles needed
Dde.ine C<?-BI?9 G (( <um)er o. )its needed .or t,e
(( counter to count t,e c*cles
(( ?OC 6O78LE
module sram-control(
clock,
reset-n,
as-n,
rw,
out-en,
write-en,
ack);
(( I<C8?9
input clock; (( 9tate mac,ine clock
input reset-n; (( Acti+e low, s*nc,ronous reset
input as-n; (( Acti+e low address stro)e
input rw; (( :ead(write command
(( / ! to read
(( / $ to write
(( O8?C8?9
output out-en; (( Output ena)le to memor*
output write-en; (( Write ena)le to memor*
output ack; (( Acknowled'e si'nal to processor
(( I<O8?9
(( 9IH<AL 7ECLA:A?IO<9
wire clock;
wire reset-n;
wire as-n;
wire rw;
wire out-en;
wire write-en;
wire ack;
re' !#$% mem-state; (( 9*nt,esis state-mac,ine
re' DC<?-BI?9E!#$%cnt; (( C*cle counter
(( CA:A6E?E:9
parameter!#$% (( 9tate mac,ine states
I7LE / $,
W:I?E / !,
:EA7 / G;
(( A99IH< 9?A?E6E<?9
(( Create t,e outputs .rom t,e states
assi'n out-en / mem-state!%;
assi'n write-en / mem-state$%;
(( Create t,e acknowled'e com)inatoriall*
assi'n ID7EL ack / Jas-n KK ((Jrw KK (cnt // DW:-CO8<?E!)) LL
( rw KK (cnt // D:7-CO8<?E!)));
(( 6AI< CO7E
(( Look at t,e risin' ed'e o. clock .or state transitions
alwa*s 3(posed'e clock or ne'ed'e reset-n) )e'in
i. (Jreset-n) )e'in
mem-state 4/ ID7EL I7LE;
cnt 4/ ID7EL DC<?-BI?91,$;
end
else )e'in
(( 8se parallel-case directi+e
(( to s,ow t,at all states are
(( mutuall* eNclusi+e
(( 8se .ull-case directo+e
(( to s,ow t,at an* ot,er states
(( are don1t cares
case (mem-state) (( s*nt,esis parallel-case .ull-case
I7LE# )e'in
(( Look .or address stro)e to )e'in t,e access
i. (Jas-n) )e'in
i. (rw) )e'in
(( ?,is is a read access
mem-state 4/ ID7EL :EA7;
end
else )e'in
(( ?,is is a write access
mem-state 4/ ID7EL W:I?E;
end
end
end
W:I?E# )e'in
(( I. we ,a+e reac,ed t,e .inal c*cle count
(( .or t,e access, t,e access is .inis,ed=
(( I. t,e address stro)e ,as )een deasserted,
(( t,e access is a)orted
i. ((cnt // DW:-CO8<?E!) LL as-n) )e'in
mem-state 4/ ID7EL I7LE;
cnt 4/ ID7EL DC<?-BI?91,$;
end
else
cnt 4/ ID7EL cnt M !;
end
:EA7# )e'in
(( I. we ,a+e reac,ed t,e .inal c*cle count
(( .or t,e access, t,e access is .inis,ed=
(( I. t,e address stro)e ,as )een deasserted,
(( t,e access is a)orted
i. ((cnt // D:7-CO8<?E!) LL as-n) )e'in
mem-state 4/ ID7EL I7LE;
cnt 4/ ID7EL DC<?-BI?91,$;
end
else
cnt 4/ ID7EL cnt M !;
end
endcase
end
end
endmodule (( sram-control
DMA (Direct Memory Access) l c ch hot ng cho php hai hay nhiu vi ! l" ho#c
ngoi vi chia s$ %us chung& 'hit %( no ang c) *uyn iu +hi,n %us s- c) th, ton
*uyn truy nh.p v trao /i 01 li2u tr3c tip v4i c5c % nh4 nh6 h2 th7ng c) mt vi ! l"&
8ng 09ng ph/ %in nh:t c;a DMA l chia s$ % nh4 chung gi1a hai % vi ! l" ho#c c5c
ngoi vi , truyn 01 li2u tr3c tip gi1a thit %( ngoi vi vo<ra v % nh4 01 li2u c;a
=>?&'ruy nh.p % nh4 tr3c tip 6@c s! 09ng , 5p Ang nhu cBu trao /i 01 li2u vo ra
t7c cao gi1a ngoi vi v4i % nh4& 'hCng th6Dng c5c ngoi vi +t n7i v4i h2 th7ng phEi
chia s$ %us 01 li2u v 6@c iu +hi,n %Fi GHI trong *u5 trJnh trao /i 01 li2u& Kiu ny
lm hn ch t7c trao /iL , tMng c6Dng t7c v loi %N s3 can thi2p c;a GHIL #c
%i2t trong tr6Dng h@p cBn truyn mt l6@ng 01 li2u l4n& G ch hot ng DMA 6@c mC
tE nh6 trong OJnh P&PQ& 'h; t9c 6@c %Rt Bu %Sng vi2c yTu cBu th3c hi2n DMA v4i
GHI& Uau +hi ! l"L nu 6@c ch:p nh.n GHI s- trao *uyn iu +hi,n %us cho ngoi vi
v th3c hi2n *u5 trJnh trao /i 01 li2u& Uau +hi th3c hi2n ong GHI s- nh.n 6@c thCng
%5o v nh.n li *uyn iu +hi,n %us& 'rong c ch DMAL c) hai c5ch , truyn 01 li2uV
+i,u DMA chu +W nL v +i,u DMA chu +W nh)m (%urst)&

Xh(p hot ng DMA
DMA chu +J n v nh)mV 'rong +i,u hot ng DMA chu +W nh)mL ngoi vi s- nh.n
6@c *uyn iu +hi,n v truyn +h7i 01 li2u rYi trE li *uyn iu +hi,n cho GHI&
'rong c ch DMA chu +W n ngoi vi sau +hi nhZn 6@c *uyn iu +hi,n %us ch[
truyn mt t\ 01 li2u rYi trE li ngay *uyn +i,m so5t % nh4 v %us 01 li2u cho GHI&
'rong c ch th3c hi2n DMA cBn c) mt %64c ! l" , *uyt (nh em thit %( no s-
6c nh.n *uyn iu +hi,n trong tr6Dng h@p c) nhiu hn mt thit %( c) nhu cBu s!
09ng DMA& 'hCng th6Dng +i,u DMA chu +W nh)m cBn ]t 01 li2u thCng tin iu +hi,n
(overhea0) nTn c) +hE nMng trao /i v4i t7c cao nh6ng li chim nhiu thDi gian truy
nh.p %us 0o truyn cE +h7i 01 li2u l4n& Kiu ny c) th, Enh h6Fng n hot ng c;a cE
h2 th7ng 0o trong su7t *u5 trJnh th3c hi2n DMA nh)mL GHI s- %( +ho5 *uyn truy nh.p
% nh4 v +hCng th, ! l" c5c nhi2m v9 +h5c c;a h2 th7ng m c) nhu cBu % nh4L v] 09
nh6 c5c 0(ch v9 ngRtL ho#c c5c t5c v9 thDi gian th3c&&&
Ghu +J r^i (Gycle Utealing)V 'rong +i,u ny DMA s- 6@c th3c hi2n trong nh1ng thDi
i,m chu +W %us m GHI +hCng s! 09ng %us 0o ) +hCng cBn th3c hi2n th; t9c ! l" c:p
ph5t *uyn truy nh.p v th3c hi2n DMA& OBu ht c5c vi ! l" hi2n i u s! 09ng gBn
nh6 _QQ` 0ung l6@ng % nh4 v %Mng thCng c;a %us nTn s- +hCng c) nhiu thDi gian
0nh cho DMA th3c hi2n& K, tit +i2m v t7i 6u ti nguyTn thJ cBn c) mt trang ti phZn
! v 01 li2u s- 6@c truyn i p chYng theo thDi gian& X)i chung +i,u DMA 0ng
%urst hi2u *uE nh:t +hi +hoEng thDi gian cBn th3c hi2n DMA t6ng 7i nhN& 'rong
+hoEng thDi gian th3c hi2n DMAL ton % %Mng thCng c;a %us s- 6@c s! 09ng t7i a v
ton % +h7i 01 li2u s- 6@c truyn i trong mt +hoEng thDi gian r:t ngRn& Xh6ng nh6@c
i,m c;a n) l nu 01 li2u cBn truyn l4n v cBn mt +hoEng thDi gian 0i thJ s- 0bn n
vi2c %loc+ GHI v c) th, %N *ua vi2c ! l" c5c s3 +i2n v t5c v9 +h5c& K7i v4i DMA chu
+W n thJ yTu cBu truy nh.p % nh4L truyn mt t\ 01 li2u v giEi ph)ng %us& G ch ny
cho php th3c hi2n truyn interleave v 6@c %it t4i v4i tTn gai inteleave0 DMA& ci,u
truyn DMA chu +W n phd h@p , truyn 01 li2u trong mt +hoEng thDi gian 0i m c)
; thDi gian , yTu cBu truy nh.p v giEi ph)ng %us cho m^i lBn truyn mt t\ 01 li2u&
Gh]nh vJ v.y s- giEm %Mng thCng truy nh.p %us 0o phEi m:t nhiu thDi gian , yTu cBu
truy nh.p v giEi ph)ng %us& 'rong tr6Dng h@p ny GHI v c5c thit %( +h5c vbn c) th,
chia s$ v truyn 01 li2u nh6ng trong mt 0Ei %Mng thCng hep& 'rong nhiu h2 th7ng %us
th3c hi2n c ch ! l" v giEi *uyt yTu cBu truy nh.p (trang ti) thCng *ua 01 li2u
truyn vJ v.y cfng +hCng Enh h6Fng nhiu n t7c truyn DMA& DMA 6@c yTu cBu
+hi +hE nMng iu +hi,n c;a GHI , truyn 01 li2u th3c hi2n *u5 ch.m& DMA cfng th3c
s3 c) " nghga +hi GHI ang phEi th3c hi2n c5c t5c v9 +h5c m +hCng cBn nhu cBu truy
nh.p %u
Hm khi to UART:
void UART_Init(void)

{

#ifdef UART_USE_TIMER1

TM!"#$%$f&

TM! '# $%($& ))Time* 1 mode (+

T,1 # $%-!&

TH1 # $%-!& )) ./0d */te #12$$

TR1 # 1&

#endif

#ifdef UART_USE_TIMER(

R3,4#1&

T3,4#1& ))Time* (: 5/0d R/te 6ene*/to*

R3A7(, # $%!3& ))5/0d R/te 12$$

R3A7(H # $%--& ))5/0d R/te 12$$

TR(#1&

#endif

ES # 1& )) 4i8h ho/t n9/t UART+

I7 # $%1$& )) Thiet :/; m08 00 tien 8ho n9/t UART+

S3< # $%=$& )) 3hon 8he do UART mode 1+

73<#73<"(>($%?$))&))khon9 nh/n doi to8 do ./0d+

@
Hm t*0ABn mCt kD tE */ UART:
void UART_70t3h/*(0nFi9ned 8h/* 8)

{

t*/n_.0FA # 1&

S5U- # 8&

Ghi:e(t*/n_.0FA)&
@
Hm nhHn mCt kD tE UART:
0nFi9ned 8h/* UART_6et3h/*(void)

{

0nFi9ned 8h/* tem;#$&

if(RI##1)

{

RI#$&

tem;#S5U-&

@

*et0*n tem;&

@
h Om g!i mt chu^i +] t3 ra IAi'V
HTM,:
void UART_70tF(0nFi9ned 8h/* IF)

{

Ghi:e (IF)

{

UART_70t3h/*(IF)&

FJJ&

@

@
3. Bi ton v d:
K, hi,u hn v c5ch s! 09ng IAi' trong jQk_ tCi 6a ra mt %i to5n th3c hnh sauV h l!i chu^i +]
t3 mDnMo IAi'p v mqan?inhcien&=np lTn HGL sau ) nh.n +] t3 6@c g!i t\ HG rYi hi,n th( +] t3
nh.n 6@c lTn HG&
Go0e %i to5n nh6 sauV
HTM,:
int m/in(void)

{

0nFi9ned 8h/* keA&

0nFi9ned 8h/* Ft*K(=L&

UART_Init()&

,3!_Init()&

de:/A_mF(1$)&

,3!_70tF(M!EM UARTM)&

de:/A_mF(1$$$)&

,3!_3:e/*()&

EA#1&

UART_70tF(M!EM UARTM)&

,3!_70tF(M5/n,inh4ien+NnM)&

UART_70tF(M5/n,inh4ien+NnM)&

Ghi:e(1)

{

keA#UART_6et3h/*()&

if(keA)

{

F;*intf(Ft*OM4i T0 N!4 nh/n d0o8 : P8MOkeA)&

UART_70tF(Ft*)&

,3!_6oto%A($O1)&

F;*intf(Ft*OM4i T0: P8MOkeA)&

,3!_70tF(Ft*)&

@



@

*et0*n 1&

@