11/14/2004 Example CMOS Logic Gate Synthesis.

doc 1/6
Jim Stiles The Univ. of Kansas Dept. of EECS
Example: CMOS Logic
Gate Synthesis

Problem: Design a CMOS digital circuit that realizes the
Boolean function:


Y A B A C = + +


Solution: Follow the steps of the design synthesis handout!

Step1: Design the PDN

First, we must rewrite the Boolean function as:

( )
Y f A, B,C =

In other words, write the complemented output in terms of
un-complemented inputs.




Time to recall our
Boolean algebra skills!
11/14/2004 Example CMOS Logic Gate Synthesis.doc 2/6
Jim Stiles The Univ. of Kansas Dept. of EECS
We must first complement this equation, and then apply
DeMorgans Theorem (several times!).

( ) ( )
( )
( )
( ) ( )
( )
Y A B A C
Y A B A C
A B A C
A B A C
A B A C
AA AC BA BC
A A B C BC
A BC
= + +
= + +
= +
= + +
= + +
= + + +
= + + +
= +


Logically, this result says:











We can thus realize this logic with the following NMOS PDN:

Y is low if A is high, OR
if both B AND C are high.
11/14/2004 Example CMOS Logic Gate Synthesis.doc 3/6
Jim Stiles The Univ. of Kansas Dept. of EECS


















Step2: Design the PUN

First, we must rewrite the Boolean function as:

( )
Y f A, B,C =

In other words, write the un-complemented output in terms
of complemented inputs.
Y
A
B
C
PDN

Y A BC = +
11/14/2004 Example CMOS Logic Gate Synthesis.doc 4/6
Jim Stiles The Univ. of Kansas Dept. of EECS
Again, using DeMorgans Theorem:

( )
Y A B A C
A B A C
A B C
= + +
= +
= +


Logically, this result says:
















We can thus realize this logic with the following PMOS PUN:

Y is high if A is low AND
either B OR C are low.
11/14/2004 Example CMOS Logic Gate Synthesis.doc 5/6
Jim Stiles The Univ. of Kansas Dept. of EECS






















Thus, the entire CMOS realization is:

Y
B
C
PUN

( )
Y A B C = +
A
V
DD

11/14/2004 Example CMOS Logic Gate Synthesis.doc 6/6
Jim Stiles The Univ. of Kansas Dept. of EECS






























Y A B A C = + +
B
C
A
V
DD

A
B
C