The operation amplifier:

An operational amplifier is a direct coupled high gain amplifier consisting of one or more
differential (OPAMP) amplifiers and followed by a level translator and an output stage. An
operational amplifier is available as a single integrated circuit package.
The block diagram of OPAMP is shown in fig. 1

.
Fig. 1
The input stage is a dual input balanced output differential amplifier. This stage provides most of
the voltage gain of the amplifier and also establishes the input resistance of the OPAMP.The
intermediate stage of OPAMP is another differential amplifier which is driven by the output of
the first stage. This is usually dual input unbalanced output.
Because direct coupling is used, the dc voltage level at the output of intermediate stage is well
above ground potential. Therefore level shifting circuit is used to shift the dc level at the output
downward to zero with respect to ground. The output stage is generally a push pull
complementary amplifier. The output stage increases the output voltage swing and raises the
current supplying capability of the OPAMP. It also provides low output resistance.
Level Translator:
Because of the direct coupling the dc level at the emitter
rises from stages to stage. This increase in dc level tends
to shift the operating point of the succeeding stages and
therefore limits the output voltage swing and may even
distort the output signal.
To shift the output dc level to zero, level translator
circuits are used. An emitter follower with voltage
divider is the simplest form of level translator as shown
in fig. 2
Thus a dc voltage at the base of Q produces 0V dc at the
output. It is decided by R
1
and R
2
. Instead of voltage
divider emitter follower either with diode current bias or
.

Fig. 2
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Fig. 3
Fig. 4, shows a complete OPAMP circuit having input different amplifiers with balanced output,
intermediate stage with unbalanced output, level shifter and an output amplifier.
current mirror bias as shown in fig. 3
In this case, level shifter, which is common collector
amplifier, shifts the level by 0.7V. If this shift is not
sufficient, the output may be taken at the junction of two
resistors in the emitter leg.
may be used to get
better results.
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Fig. 4
Example-1:
For the cascaded differential amplifier shown in fig. 5
The collector current and collector to emitter voltage for each transistor.
, determine:
The overall voltage gain.
The input resistance.
The output resistance.
Assume that for the transistors used h
FE
=100 and V
BE
=0.715V
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Fig. 5
Solution:
(a). To determine the collector current and collector to emitter voltage of transistors Q
1
and Q
2
,
we assume that the inverting and non-inverting inputs are grounded. The collector currents (I
C

I
E
) in Q
1
and Q
2
are obtained as below:

That is, I
C1
=I
C2
=0.988 mA.
Now, we can calculate the voltage between collector and emitter for Q
1
and Q
2
using the
collector current as follows:
V
C1
=V
CC
=-R
C1
I
C1
=10 (2.2k) (0.988 mA) = 7.83 V = V
C2

Since the voltage at the emitter of Q
1
and Q
2
is -0.715 V,
V
CE1
=V
CE2
=V
C1
-V
E1
=7.83 +0715 =8.545 V
Next, we will determine the collector current in Q
3
and Q
4
by writing the Kirchhoff's voltage
equation for the base emitter loop of the transistor Q
3
:
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V
CC
R
C2
I
C2
=V
BE3
- R'
E
I
C3
- R
E2
(2 I
E3
) +V
BE
=0
10 (2.2k) (0.988mA) - 0.715 - (100) (I
E3
) (30k) I
E3
+10=0
10 - 2.17 - 0.715 +10 - (30.1k) I
E3
=0

Hence the voltage at the collector of Q
3
and Q
4
is
V
C3
=V
C4
=V
CC
R
C3
I
C3
=10 (1.2k) (0.569 mA)
=9.32 V
Therefore,
V
CE3
=V
VCE4
=V
C3
V
E3
=9.32 7.12 =2.2 V
Thus, for Q
1
and Q
2
:
I
CQ
=0.988 mA
V
CEQ
=8.545 V
and for Q
3
and Q
4
:
I
CQ
=0.569 mA
V
CEQ
=2.2 V
[Note that the output terminal (V
C4
) is at 9.32 V and not at zero volts.]
(b). First, we calculate the ac emitter resistance r'
e
of each stage and then its voltage gain.

The first stage is a dual input, balanced output differential amplifier, therefore, its voltage gain is

Where
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R
i2
=input resistance of the second stage

The second stage is dual input, unbalanced output differential amplifier with swamping resistor
R'
E
, the voltage gain of which is

Hence the overall voltage gain is
A
d
=(A
d1
) (A
d2
) =(80.78) (4.17) =336.85
Thus we can obtain a higher voltage gain by cascading differential amplifier stages.
(c).The input resistance of the cascaded differential amplifier is the same as the input resistance
of the first stage, that is
R
i
= 2
ac
(r
e1
) = (200) (25.3) = 5.06 k
(d). The output resistance of the cascaded differential amplifier is the same as the output
resistance of the last stage. Hence,
R
O
=R
C
= 1.2 k
Example-2:
For the circuit show in fig. 6
The dc conditions for each state
, it is given that =100, V
BE
=0715V. Determine
The overall voltage gain
The maximum peak to peak output voltage swing.
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Fig. 6
Solution:
(a). The base currents of transistors are neglected and V
BE
drops of all transistors are assumed
same.

From the dc equivalent circuit,

and

b) The overall voltage gain of the amplifier can be obtained as below:
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Therefore, voltage gain of second stage

The input impedance of second stage is

The effective load resistance for first stage is

Therefore, the voltage gain of first stage is

The overall voltge gain is A
V
=A
V1
A
V2


(c). The maximum peak to peak output votage swing =Vopp =2 (V
C7
- V
E7
)
=2 x (5.52 - 3.325)
=4.39 V

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