Tarea MUX 8 A 1 Y 16 A 1

Mux 8 A 1 con asignacin seleccionada

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux8a1w8 is
Port (
--entrada de datos
Ain : in STD_LOGIC_VECTOR (7 downto 0);
Bin : in STD_LOGIC_VECTOR (7 downto 0);
Cin : in STD_LOGIC_VECTOR (7 downto 0);
Din : in STD_LOGIC_VECTOR (7 downto 0);
Ein : in STD_LOGIC_VECTOR (7 downto 0);
Fin : in STD_LOGIC_VECTOR (7 downto 0);
Gin : in STD_LOGIC_VECTOR (7 downto 0);
Hin : in STD_LOGIC_VECTOR (7 downto 0);
--salida de datos
Yout : out STD_LOGIC_VECTOR (7 downto 0);
--entrada de seleccion
Sel : in STD_LOGIC_VECTOR (2 downto 0)
);
end entity mux8a1w8;
architecture arq_mux8a1w8 of mux8a1w8 is
begin
--asignacion seleccionada
with Sel select
Yout <=
Ain when "000" ,
Bin when "001" ,
Cin when "010" ,
Din when "011" ,
Ein when "100" ,
Fin when "101" ,
Gin when "110" ,
Hin when others; -- "111";

end architecture arq_mux8a1w8;

MUX 8 A 1 W 8 ASIGNACION CONDICIONAL

------------------------------------------------------------------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---------------------------------------------------------------------------------entity mux8a1w8 is
Port (
--entrada de datos
Ain : in STD_LOGIC_VECTOR (7 downto 0);
Bin : in STD_LOGIC_VECTOR (7 downto 0);
Cin : in STD_LOGIC_VECTOR (7 downto 0);
Din : in STD_LOGIC_VECTOR (7 downto 0);
Ein : in STD_LOGIC_VECTOR (7 downto 0);
Fin : in STD_LOGIC_VECTOR (7 downto 0);
Gin : in STD_LOGIC_VECTOR (7 downto 0);
Hin : in STD_LOGIC_VECTOR (7 downto 0);
--salida de datos
Yout : out STD_LOGIC_VECTOR (7 downto 0);

--entrada de seleccion
Sel : in STD_LOGIC_VECTOR (2 downto 0));
end entity mux8a1w8;
architecture arq_mux8a1w8 of mux8a1w8 is
begin
--asignacion condicional
Yout <=

Ain when Sel = "000" else

Bin when Sel = "001" else
Cin when Sel = "010" else
Din when Sel = "011" else
Ein when Sel = "100" else
Fin when Sel = "101" else
Gin when Sel = "110" else
Hin when Sel = "111";

end architecture arq_mux8a1w8;

MUX 16 A 1 W 8 ASIGNACION CONDICIONAL

---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------

entity mux16a1w8 is
Port (
Ain : in STD_LOGIC_VECTOR (7 downto 0);
Bin : in STD_LOGIC_VECTOR (7 downto 0);
Cin : in STD_LOGIC_VECTOR (7 downto 0);
Din : in STD_LOGIC_VECTOR (7 downto 0);
Ein : in STD_LOGIC_VECTOR (7 downto 0);
Fin : in STD_LOGIC_VECTOR (7 downto 0);
Gin : in STD_LOGIC_VECTOR (7 downto 0);
Hin : in STD_LOGIC_VECTOR (7 downto 0);
Iin : in STD_LOGIC_VECTOR (7 downto 0);
Jin : in STD_LOGIC_VECTOR (7 downto 0);
Kin : in STD_LOGIC_VECTOR (7 downto 0);
Lin : in STD_LOGIC_VECTOR (7 downto 0);
Min : in STD_LOGIC_VECTOR (7 downto 0);
Nin : in STD_LOGIC_VECTOR (7 downto 0);
Oin : in STD_LOGIC_VECTOR (7 downto 0);
Pin : in STD_LOGIC_VECTOR (7 downto 0);
Sel : in STD_LOGIC_VECTOR (3 downto 0);
Yout : out STD_LOGIC_VECTOR (7 downto 0)
);
end entity mux16a1w8;
architecture arq_mux16a1w8 of mux16a1w8 is
begin
--asignacion condicional
Yout <=

Ain when Sel = "0000" else

Bin when Sel = "0001" else
Cin when Sel = "0010" else
Din when Sel = "0011" else
Ein when Sel = "0100" else
Fin when Sel = "0101" else
Gin when Sel = "0110" else
Hin when Sel = "0111" else
Iin when Sel = "1000" else
Jin when Sel = "1001" else
Kin when Sel = "1010" else
Lin when Sel = "1011" else
Min when Sel = "1100" else
Nin when Sel = "1101" else
Oin when Sel = "1110" else
Pin when Sel = "1111";

end architecture arq_mux16a1w8;

MUX 16 A 1 W 8 ASIGNACION SELECCIONADA

------------------------------------------------------------------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---------------------------------------------------------------------------------entity mux16a1w8_S is
Port (
--entrada de datos
Ain : in STD_LOGIC_VECTOR (7 downto 0);
Bin : in STD_LOGIC_VECTOR (7 downto 0);
Cin : in STD_LOGIC_VECTOR (7 downto 0);
Din : in STD_LOGIC_VECTOR (7 downto 0);
Ein : in STD_LOGIC_VECTOR (7 downto 0);
Fin : in STD_LOGIC_VECTOR (7 downto 0);
Gin : in STD_LOGIC_VECTOR (7 downto 0);
Hin : in STD_LOGIC_VECTOR (7 downto 0);
Iin : in STD_LOGIC_VECTOR (7 downto 0);
Jin : in STD_LOGIC_VECTOR (7 downto 0);
Kin : in STD_LOGIC_VECTOR (7 downto 0);
Lin : in STD_LOGIC_VECTOR (7 downto 0);
Min : in STD_LOGIC_VECTOR (7 downto 0);
Nin : in STD_LOGIC_VECTOR (7 downto 0);
Oin : in STD_LOGIC_VECTOR (7 downto 0);
Pin : in STD_LOGIC_VECTOR (7 downto 0);
--entrada de seleccion
Sel : in STD_LOGIC_VECTOR (3 downto 0);
--salida de datos
Yout : out STD_LOGIC_VECTOR (7 downto 0)
);
end entity mux16a1w8_S;
architecture arq_mux16a1w8_S of mux16a1w8_S is
begin
--asignacion seleccionada
with Sel select
Yout <=

Ain when x"0",

Bin when x"1" ,
Cin when x"2",
Din when x"3",
Ein when x"4",
Fin when x"5",
Gin when x"6",
Hin when x"7",
Iin when x"8",
Jin when x"9",
Kin when x"A",

Lin when x"B",

Min when x"C",
Nin when x"D",
Oin when x"E",
Pin when others; -- "F";
end architecture arq_mux16a1w8_S;