module vsync(

//vsync is main module

input clk,

//50 MHz, internal clock, C9 pin

input rst,

//switch

output xclk

//5 MHz clock- output

output reg[8:0] encoderdata;

// inputs to 9 bit encoder

);
wire clk0, clk90, clkdiv0, clk200,locked;

//clk 90 means, it's phase is

shifted by 90 degrees

sysclks clks (.CLKIN1_IN(clk),

//Module instantiation

.RST_IN(rst),

//sysclks is dcm module

.CLKOUT0_OUT(clk0),
.CLKOUT1_OUT(clk90),
.CLKOUT2_OUT(clkdiv0),
.CLKOUT3_OUT(clk200),
.CLKOUT4_OUT(xclk),

//output 5 MHz clock

.LOCKED_OUT(locked)
);
reg [8:0] data=9'b001100110;

//sample 9 byte data

always @(posedge of xclk)

rate

// Sending data at 5 MHz

begin
for (i=0;i<9;i++)
begin
encoderdata=data;
end
end

//parallel output, input to your encoder