C26a2 COmpal LA-8941P

A
Compal Confidential
1
Model Name : Q1VZC

File Name :LA-8941P
BOM P/N:43
ZZZ1
ZZZ2
ZZZ3
ZZZ4
LA-8941P
DA2@
LS-8941P
DA2@
LS-8942P
DA2@
LS-8943P
DA2@
ZZZ5
PCB
DAZ@
Compal Confidential
2
Q1VZC M/B Schematics Document

Intel Sandy Bridge ULV Processor + Panther Point PCH
2012-04-19
REV:1.0
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/11/22
2012/11/22
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cover Page
Rev
1.0
Q1VZC M/B LA-8941P Schematic
Date:
A
Sheet
Friday, April 20, 2012

E
of
45
Compal Confidential
Model Name : Q1VZC
File Name :LA-8941P
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
Intel
Sandy Bridge ULV
page 11,12
BANK 0, 1, 2, 3
Dual Channel
1.5V DDRIII 1066/1333
Processor
BGA1023
17W
eDP(UMA)
page 4~10
FDI x8
CRT Conn
page 24
HDMI Conn.
LVDS/eDP Conn.
page 23
CLK=100MHz
page 22
DMI x4
CLK=100MHz
2.7GT/s
USB 2.0
conn x1(Option for USB3.0)
page 34
2.5GB/s x4
TMDS(UMA)
RGB(UMA)
Intel
HD Audio
Broadcom
57785page
MINI Card
WLAN
25
page 36
Port 2
PCI-Express x 8
(PCIE2.0 5GT/s) 100MHz
PCH
Port 10
Port 8
Port 3
3.3V 24MHz
page 22
Port 2,3
LAN(GbE)/CardReader
Panther Point-M
CMOS
Camera
page 30
Port 1
USBx14
3.3V 48MHz
LVDS(UMA)
USB 2.0
conn x2
SPI
SATA x 6 (GEN2 3.0GT/S ,GEN3 6GT/S)
HDA Codec
100MHz
ALC271X-VB6
989pin BGA
page 31
page 13~21
3
Int. Speaker
page 31
SPI ROM x2
LPC BUS
page 13
GEN3
Port 0
LS-8941P
SATA HDD
Conn.
LED/B
LS-8942P
CLK=33MHz
IO/B
ENE
KB9012
RTC CKT.
page 30
page 24
page 28
page 29
LS-8943P
page 13
HDD/B
page 24
Power On/Off CKT.

Touch Pad
page 36
Int.KBD
page 30
page 30
TPM
page 30
DC/DC Interface CKT.
page 33
2011/11/22
Issued Date
page 34~43
Compal Secret Data
Power Circuit DC/DC
Deciphered Date
2012/11/22
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Title
Rev
1.0
Date:
A
Block Diagrams
Size
Document Number
Custom
Sheet

E
of
45
SIGNAL
STATE
Voltage Rails
Power Plane
+VALW
+V
+VS
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Full ON
Description
S1
S3
S5
N/A
VIN
Adapter power supply (19V)
N/A
N/A
BATT+
Battery power supply (12.6V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+VGFX_CORE
Core voltage for UMA graphic
ON
OFF
OFF
Board ID / SKU ID Table for AD channel
+0.75VS
+0.75VP to +0.75VS switched power rail for DDR terminator
ON
OFF
OFF
+1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU
ON
OFF
OFF
+1.5V
+1.5VP to +1.5V power rail for DDRIII
ON
ON
OFF
Vcc
Ra/Rc/Re
+1.5VS
+1.5V to +1.5VS switched power rail
ON
OFF
OFF
Board ID
+1.8VS
(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
ON
OFF
OFF
ON*
0
1
2
3
4
5
6
7
+3VALW
+3VALW always on power rail
ON
ON
+3VALW to +VCCSUS3_3 power rail for PCH (Short Jump)
ON
ON
ON*
+3VS
+3VALW to +3VS power rail
ON
OFF
OFF
+5VALW
+5VALWP to +5VALW power rail
ON
ON
ON*
+5VREF_SUS
+5VALW to +5VREF_SUS power rail for PCH (Short resister)
ON
ON
ON*
+5VS
+5VALW to +5VS switched power rail
ON
OFF
OFF
+VSB
+VSBP to +VSB always on power rail for sequence control
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
Clock
+1.05VS_VTT
+VCCSUS3_3
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
BOARD ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC SM Bus1 address
Device
Address
Smart Battery
0001 011X b
PCH SM Bus address

Device
ChannelA
ChannelB
A0
B0
1010 000X
1010 010X
BTO Option Table
PCB Revision
0.1
0.2
0.3
1.0
BTO Item
BOM Structure
Celeron 867
C867@
Pentium 977
P977@
Unpop
@
eDP Panel
EDP@
LVDS Panel
LVDS@
Connector
CONN@
USB3 Only
USB3@
Deep S3
DS3@
Normal S3
S3@
Intel i5/i7 CPU only I57@
Celeron/Pentium/i3
CP3@
CPU only
USB Port Table

USB 2.0 USB 1.1 Port
Address
DIMM0
DIMM0
Board ID
0
1
2
3
4
5
6
7
JDIMM1(STD)
JDIMM2(REV)
UHCI0
UHCI1
EHCI1
UHCI2
UHCI3
UHCI4
EHCI2
UHCI5
UHCI6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
3 External
USB Port
USB 2.0(Options for USB3.0)
USB port(Left 2.0)
USB Port(Left 2.0)
USB 3.0 Port

1
2
XHCI
3
4
Mini Card(WLAN)
Camera
USB Port(Right 3.0)
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
Notes List
Rev
1.0
Date:
A
Sheet

E
of
45
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
+1.05VS_VTT
R1
24.9_0402_1%
UCPU1A
1
<15>
<15>
<15>
<15>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<15>
<15>
<15>
<15>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
U7
W11
W1
AA6
W6
V4
Y2
AC9
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
U6
W10
W3
AA7
W7
T4
AA3
AC8
<15>
<15>
FDI_FSYNC0
FDI_FSYNC1
<15>
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
EDP_HPD#
U11
AA10
AG8
EDP_AUXN
EDP_AUXP
<22>
<22>
EDP_TXN0
EDP_TXN1
<22>
<22>
EDP_TXP0
EDP_TXP1
AG4
AF4
AC3
AC4
AE11
AE7
<22>
<22>
AF3
AD2
AG11
AC1
AA4
AE10
AE6
EDP_HPD#
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX#
eDP_AUX
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
eDP
EDP_HPD#
AA11
AC12
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
W=12mil L=500mil S=15mil
<22>
K3
M7
P4
T3
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
EDP_COMP
R3
1K_0402_5%
EDP@
K1
M8
N4
R2
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
R2
<15>
24.9_0402_1%
+1.05VS_VTT
N3
P7
P3
P11
PCI EXPRESS -- GRAPHICS
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
eDP_COMPIO and ICOMPO signals

should be shorted near balls and
routed with typical impedance
<25 mohms
can't be left floating
,even if disable eDP function...
<15>
<15>
<15>
<15>
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
Intel(R) FDI
+1.05VS_VTT
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI
<15>
<15>
<15>
<15>
M2
P6
P1
P10
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
IVY-BRIDGE_BGA1023
C867@
G3
G1
G4
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_COMP
SA00005BH40(S IC AV8062701148901 SR0FK J1 1.3G ABO!)
C867@
Celeron 867
HR
1.3G
P977@
Pentium 977
HR
1.4G
SA00005BJ50(S IC AV8062701147701 SR0FB J1 1.4G ABO!)
I2467@
i5-2467M
HR
1.6G
SA00004X010(S IC AV8062701047504 SR0D6 J1 1.6G ABO!)
I2367@
i3-2367M
HR
1.4G
SA000051H60( S IC AV8062701047904 SR0CV J1 1.4G ABO! )
C877@
Celeron 877
HR
1.4G
SA00005QI00( S IC AV8062701148001 QB35 J1 1.4G BGA)
P987@
Pentium 987
HR
1.5G
SA00005QH00(S IC AV8062701147601 QB31 J1 1.5G BGA)
P967@
Pentium 967
HR
1.3G
SA000051J40(S IC AV8062701147801 SR0FC J1 1.3G ABO!)
I2377@
i3-2377M
HR
1.5G
SA00005MX10(S IC AV8062701048004 QAXQ J1 1.5G BGA)
I3317@
i5-3317U
CR
1.7G
SA00005K650(S IC AV8063801058002 QC9E L1 1.7G BGA)
I3667@
i7-3667U
CR
2G
SA00005LA50(S IC AV8063801057405 QC9B L1 2G BGA 1023)
I3217@
i3-3217U
CR
1.8G
SA00005L530(S IC AV8063801058400 QC56 L0 1.8G ABO!)
I3427@
i5-3427U
CR
1.8G
SA00005L9A0(S IC AV8063801057801 SR0N7 L1 1.8G BGA)
I3517@
i7-3517U
CR
1.9G
SA00005K540(S IC AV8063801057605 QC9C L1 1.9G BGA)
UCPU1
UCPU1
UCPU1
UCPU1
AV8062701147701
P977@
AV8062701047504
I2467@
AV8062701047904
I2367@
AV8062701148001
C877@
SA00004X010
SA000051H60
SA00005QI40
SA00005BJ50
UCPU1
UCPU1
UCPU1
AV8062701147601
P987@
AV8062701147801
P967@
AV8062701048004
I2377@
SA00005QH50
SA000051J40
SA00005MX60
UCPU1
UCPU1
UCPU1
AV8063801058002
I3317@
AV8063801057405
I3667@
AV8063801058401
I3217@
SA00005K6B0
SA00005LAA0
SA00005L5C0
UCPU1
UCPU1
AV8063801057801
I3427@
AV8063801057605
I3517@
SA00005L9B0
SA00005K5B0
HR(Sandy Bridge)
CR(Ivy Bridge)
Compal Secret Data
2011/11/22
Issued Date
Deciphered Date
2012/11/22
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PROCESSOR(1/7) DMI,FDI,PEG
Sheet
E
of
45
0921 LVDS@->@
+1.05VS_VTT
CLK_CPU_DPLL#
R4
2 LVDS@ 1 1K_0402_5%
CLK_CPU_DPLL
R5
2 LVDS@ 1 1K_0402_5%
Checklist1.5 P.67 Graphis Disable Guide

eDP disable:
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PU 1K_5% to +1.05VS_VTT
UCPU1B
CPU
Follow DG 1.5& Tacoma_Fall2 1.0

reserve
XBOX
1 0.1U_0402_16V4Z
T1
PAD @
H_CATERR#
C49
H_PECI
A48
PROC_DETECT#
1 10K_0402_5%
+1.05VS_VTT
<29,35>
R7
<18,29>
H_PECI
1 62_0402_5%
R8
56_0402_5%
1
2
H_PROCHOT#
H_PROCHOT#
H_PROCHOT#_R
<18>
Follow DG 1.5 & Tacoma_Fall2 1.0

Buffered reset to CPU
C45
D45
H_THRMTRIP#
PECI
PROCHOT#
5
P
1
2
BUFO_CPU_RST#
<18>
H_CPUPW RGD
BUF_CPU_RST#
R13
2 H_CPUPW RGD_R
0_0402_5%
COREOK
B46
UNCOREPWRGOOD
UNCOREPWRGOOD:
PM_DRAM_PW RGD_R
PLT_RST#
R15
43_0402_1%
1
2
BE45
SM_DRAMPWROK
SN74LVC1G07DCKR_SC70-5
SM_DRAMPWROK:DRAM power ok
okCPUreset
BUF_CPU_RST#
RESET#:
Follow DG 1.5 & Tacoma_Fall2 1.0
Use open drain logic gate:

+1.5V_CPU_VDDQ PU pop 200ohm
resister pop 130ohm
+3VALW
+1.5V_CPU_VDDQ series
1
R16
200_0402_5%
<15>
PM_DRAM_PW RGD
B
A
<15>
SYS_PW ROK
G VCC
U2
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
AT30
SM_DRAMRST#
BF44
BE43
BG43
SM_RCOMP0 R9
SM_RCOMP1 R10
SM_RCOMP2 R11
PM_SYS_PW RGD_BUF
1
R18
SM_DRAMRST#
2
2
2
<6>
1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%
DDR3 Compensation Signals
RESET#
TCK
TMS
TRST#
TDI
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
N53
N55
L56
L55
J58
XDP_TCK
@
XDP_TMS
@
XDP_TRST# @
PAD T2
PAD T3
PAD T4
M60
L59
XDP_TDI
XDP_TDO
PAD T5
PAD T6
K58
XDP_DBRESET#
@
@
XDP_DBRESET#
<15>
G58
E55
E59
G55
G59
H60
J59
J61
H_CPUPW RGD_R
+3VS
IVY-BRIDGE_BGA1023
C867@
XDP_DBRESET# R17
12/22 Add(ESD request)
1 1K_0402_5%
Tacoma_Fall2 1.0 PU 1K +3VS

Check list 1.5 PU 1K +3VS
Debug port DG1.1-1.3 50~5K ohm
CLK_CPU_DPLL <14>
CLK_CPU_DPLL# <14>
C476
180P_0402_50V8J
C67
0.1U_0402_16V4Z
@
2
D44
PWR MANAGEMENT
<17>
PLT_RST#
U1
NC
PM_SYNC
R12
75_0402_5%
2
R14
0_0402_5%
1
2 1
@
C48
H_PM_SYNC
CLK_CPU_DPLL
CLK_CPU_DPLL#
SM_RCOMP2
PRDY#
PREQ#
<15>
AG3
AG1
THERMTRIP#
+1.05VS_VTT
C66
0.1U_0402_16V4Z
CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>
SM_RCOMP0,SM_RCOMP1
Use open drain logic gate:

+1.05VS_VTT PU pop 75ohm
series resister pop 43ohm
+3VS
DPLL_REF_CLK
DPLL_REF_CLK#
J3
H2
CATERR#
H_CPUPW RGD
follow Checklist 1.5

2
R6
PROC_SELECT#
JTAG & BPM
C57
THERMAL
@
C65
H_SNB_IVB#
BCLK
BCLK#
CLOCKS
<17>
F49
DDR3
MISC
MISC
PROC_SELECT#
PH VCPLL and connect to PCH DF_TVS
PCH->CPU
UNCOREPWRGOOD: CORE
OK
SM_DRAMPWROK:DRAM power ok
CPU reset
RESET#: ok
2
PM_DRAM_PW RGD_R
130_0402_5%
MC74VHC1G09DFT2G_SC70-5
Compal Secret Data
2011/11/22
Issued Date
Deciphered Date
2012/11/22
Title
Size
Document Number
Custom
Date:
A
PROCESSOR(3/7) DDRIII
Sheet

E
of
45
Rev
1.0
UCPU1C
UCPU1D
<12>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
<11>
<11>
<11>
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
<11>
<11>
<11>
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
BD37
BF36
BA28
BE39
BD39
AT41
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
AU36
AV36
AY26
DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
SA_CLK_DDR0 <11>
SA_CLK_DDR#0 <11>
DDRA_CKE0_DIMMA <11>
AT40
AU40
BB26
SA_CLK_DDR1 <11>
SA_CLK_DDR#1 <11>
DDRA_CKE1_DIMMA <11>
BB40
BC41
DDRA_CS0_DIMMA#
DDRA_CS1_DIMMA#
AY40
BA41
SA_ODT0
SA_ODT1
AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
<11>
<11>
<11>
<11>
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
<11>
<11>
<11>
<12>
<12>
<12>
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
<12>
<12>
<12>
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
BG39
BD42
AT22
AV43
BF40
BD45
IVY-BRIDGE_BGA1023
C867@
1
DIMM_DRAMRST#_R
Q1
BSS138_NL_SOT23-3
SM_DRAMRST#
<29>
R23
0_0402_5%
1
2
DS3@
RST_GATE
R24
0_0402_5%
1
2
DS3@
EC_RST_GATE
R22
4.99K_0402_1%
<14>
SB_CLK_DDR0 <12>
SB_CLK_DDR#0 <12>
DDRB_CKE0_DIMMB <12>
1
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
BA36
BB36
BF27
SB_CLK_DDR1 <12>
SB_CLK_DDR#1 <12>
DDRB_CKE1_DIMMB <12>
BE41
BE47
DDRB_CS0_DIMMB#
DDRB_CS1_DIMMB#
AT43
BG47
SB_ODT0
SB_ODT1
<12>
<12>
<12>
<12>
AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS#[0..7]
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS[0..7]
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
<12>
DDR_B_MA[0..15]
<12>
<12>
IVY-BRIDGE_BGA1023
C867@
R20
1K_0402_5%
SM_DRAMRST#
BA34
AY34
AR22
R19
0_0402_5%
1
2
@
DIMMreset
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
CPU
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
+1.5V
Follow CRB1.0
<5>
AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
DDR SYSTEM MEMORY B
DDR_A_D[0..63]
DDR SYSTEM MEMORY A
<11>
RST_GATE_R
RST_GATE_R
C68
0.047U_0402_16V7K
<11,12>
1
R21
2
1K_0402_5%
DIMM_DRAMRST#
<11,12>
S0
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
Dimm not reset
S3
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# HIGH
Dimm not reset
S4,5
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# low
Dimm reset
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
PROCESSOR(3/7) DDRIII
Rev
1.0
Date:
A
Sheet

E
of
45
CFG Straps for Processor

CFG2
PAD @
PAD @
VCC_VAL_SENSE
VSS_VAL_SENSE
H43
K43
T39
T40
PAD @
PAD @
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
H45
K45
T8
PAD @
F48
H48
K48
BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_DIE_SENSE
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
R25
1K_0402_1%
@
N42
L42
L45
L47
PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches
socket pin map definition
CFG2
M13
M14
U14
W14
P13
0:Lane Reversed
CFG4
AT49
K24
UMA,Optimus eDP
DISO eDP
RSVD39
RSVD40
EDP@
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
AH2
AG13
AM14
AM15
N50
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1
A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1
R28
1K_0402_1%
eDP enable
CFG4
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
N59
N58
T37
T38
BCLK_ITP
BCLK_ITP#
DC_TEST_C4_D3
1:Disable
0:Enable
CFG6
CFG5
These pins are for solder joint

reliability and non-critical to
function. For BGA only.
DC_TEST_A59_C59
CFG4
CFG5
CFG6
CFG7
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
R31
1K_0402_1%
@
DC_TEST_A61_C61
R32
1K_0402_1%
@
CFG2
1
B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53
CFG0
PAD @
RESERVED
T7
UCPU1E
DC_TEST_BE59_BE61
DC_TEST_BG59_BG61
DC_TEST_BE3_BG3
PCIE Port Bifurcation Straps
DC_TEST_BE1_BG1
11: (Default) 1x16 PCI Express

CFG[6:5]
IVY-BRIDGE_BGA1023
C867@
10: 2x8 PCI Express

*01:
Reserved
00: 1x8,2x4 PCI Express
CFG7
R33
1K_0402_1%
Tacoma_Fall2 1.0 P.12
PEG DEFER TRAINING

CFG7
1: (Default) PEG Train immediately following

xxRESETB de assertion
0: PEG Wait for BIOS for training
Compal Secret Data
2011/11/22
Issued Date
Deciphered Date
2012/11/22
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PROCESSOR(4/7) RSVD,CFG
Sheet

E
of
45
UCPU1F
ULV type
DC 33A
POWER
8.5A
+1.05VS_VTT
INTEL Recommend VCCIO

2*330UF,10*10uF(0603) and 26*1uF(0402)
PD0.8
CAP at P.51
AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15
For PEG
+3VS
R34
10K_0402_5%
@
W16
W17
VCCIO_SEL
VCCIO_SEL after Ivy bridge ES2 Voltage support
R35
10K_0402_5%
@
BC22
2
VCCIO_SEL
BC22
1/NC : (Default) +1.05VS_VTT

0: +1.0VS_VTT
VCCIO_SEL
+1.05VS_VTT
A44
B43
C44
Place the PU
resistors close to CPU
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
R38
R39
R40
1
1
1
2 43_0402_1%
2 0_0402_5%
2 0_0402_5%
SVID_ALERT#
<41>
SVID_CLK <41>
SVID_DATA <41>
R44
AN16
AN17
1
1
2
2
0_0402_5%
0_0402_5%
2 10_0402_5% +1.05VS_VTT
VCCIO_SENSE
VSSIO_SENSE
VCCSENSE
VSSSENSE
R46
10_0402_5%
Should change to connect form

power cirucit & layout differential
with VCCIO_SENSE.
IVY-BRIDGE_BGA1023
C867@
<41>
<41>
R45
100_0402_1%
<40>
VCCIO_SENSE
VSS_SENSE_VCCIO
R42
R43
F43 VCCSENSE_R
G43 VSSSENSE_R
R41
100_0402_1%
VCC_SENSE
VSS_SENSE
+CPU_CORE
SENSE LINES
R37
75_0402_5%
R36
130_0402_5%
1
2
C69
1U_0402_6.3V6K
VIDALERT#
VIDSCLK
VIDSOUT
+1.05VS_VTT
AM25
AN22
+1.05VS_VTT
VCCPQE[1]
VCCPQE[2]
Place the PU
resistors close to VR
PEG IO AND DDR IO
For DDR
+1.05VS_VTT
VCCIO50
VCCIO51
SVID
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
QUIET
RAILS
CORE SUPPLY
INTEL Recommend VCC

4*470UF,12*22uF(0805) and 35*2.2uF(0402)
PD0.8
CAP at P.51
VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48
VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
+CPU_CORE
A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38
Check list 1.5
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
PROCESSOR(5/7) PWR,BYPASS
Size
Document Number
Custom
Rev
1.0
Date:
A
Sheet
E
of
45
+V_SM_VREF should
have 20 mil trace width
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
R50
1K_0402_1%
@
C80
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C79
C78
C77
C76
C75
C74
C73
C72
C71
1U_0402_6.3V6K
+1.5VS
J1
1
1U_0402_6.3V6K
JUMP_43X118
@
1
+ C81
330U_D2_2V_Y
C89
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C88
C87
C86
C85
C84
C83
C82
10U_0603_6.3V6M
Place BOT OUT BGA
- 1.5V RAILS
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Check list1.5 P18 M1 default M3 no stuff
+1.5V_CPU_VDDQ
Place TOP IN BGA

1U_0402_6.3V6K
DDR3
R48
1K_0402_5%
INTEL Recommend VDDQ

1*330uF,8*10uF(0603) ,10*1uF(0402)
PD0.8
10U_0603_6.3V6M
GRAPHICS
AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33
5A
VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]
C70
0.1U_0402_16V4Z
<11>
<12>
1
2
R49
1K_0402_1%
@
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
1U_0402_6.3V6K
+V_SM_VREF
BE7
BG7
10U_0603_6.3V6M
+VGFX_CORE
AY43
1U_0402_6.3V6K
CR CheckList Rev1.5
SM_VREF
1U_0402_6.3V6K
VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]
1U_0402_6.3V6K
AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61
R47
1K_0402_5%
DC 16A
INTEL Recommend VAXG

2*470uF,6*22uF(0805) and 6*10uF(0603)
11*1U(0402)
PD0.8
POWER
UCPU1G
+VGFX_CORE
+1.5V_CPU_VDDQ
SGA20331E10 S POLY C 330U

2V Y D2 LESR9M EEFSX H1.9
2
R51
+1.5V_CPU_VDDQ
100_0402_5%
+VCCSA
Place TOP IN BGA

+VCCSA
1
2
1
2
1
2
C99
1U_0402_6.3V6K
C98
1U_0402_6.3V6K
C97
1U_0402_6.3V6K
C96
1U_0402_6.3V6K
SGA20331E10 S POLY C 330U

2V Y D2 LESR9M EEFSX H1.9
+ C94
330U_D2_2V_Y
C95
1U_0402_6.3V6K
6A
L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20
VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]
1
C90
1U_0402_6.3V6K
BC43
BA43
VDDQ_SENSE
VSS_SENSE_VDDQ
VCCSA
U10
VCCSA_SENSE
VCCSA_SENSE
CPU EDS1.3 P.93

VCCSA_VID0 Must PD
D48
D49
VCCSA_VID[0]
VCCSA_VID[1]
H_VCCSA_VID0
H_VCCSA_VID1
H_VCCSA_VID0
H_VCCSA_VID1
+ C91
@
220U_B2_2.5VM_R35
C93
1U_0402_6.3V6K
C92
1U_0402_6.3V6K
SGA00001700 S POLY C 220U

220U 2.5V M B2 ESR35 TPE H1.9
VCCPLL[1]
VCCPLL[2]
VCCPLL[3]
SENSE LINES
BB3
BC1
BC4
VCCSA VID
lines
Place BOT OUT Conn
SA RAIL
+1.8VS
3
1.2A
100_0402_5%
1.8V RAIL
R52
AM28
AN26
VCCDQ[1]
VCCDQ[2]
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
F45
G45
VCC_GFXSENSE
VSS_GFXSENSE
<41>
<41>
QUIET RAILS
INTEL Recommend VCCPLL

1*330uF,2*1uF(0402)
PD0.8
<39>
<39>
<39>
R53
0_0402_5%
VID0 VID1 Vout
HR
CR
0.9V
0.85V
0.775V
0.75V
10U_0603_6.3V6M
C104
C103
C102
10U_0603_6.3V6M
C101
10U_0603_6.3V6M
C100
10U_0603_6.3V6M
INTEL Recommend VCCSA

1*330uF,5*10uF(0603) ,5*1uF(0402)
PD0.8
10U_0603_6.3V6M
IVY-BRIDGE_BGA1023
C867@
Place BOT OUT BGA
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
PROCESSOR(6/7) PWR
Size
Document Number
Custom
Rev
1.0
Date:
A
Sheet
E
of
45
UCPU1H
UCPU1I
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13
BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS
NCTF
A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48
A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61
IVY-BRIDGE_BGA1023
C867@
Issued Date
IVY-BRIDGE_BGA1023
C867@
Compal Secret Data
2011/11/22
Deciphered Date
2012/11/22
Title
Rev
1.0
Date:
A
PROCESSOR(7/7) VSS
Sheet
E
10
of
45
+1.5V
+V_DDR_REFA
+1.5V
<6,12>
RST_GATE_R
DDR_A_DQS#[0..7]
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
<6>
DDR_A_DQS[0..7]
DDR_A_D[0..63]
DDR_A_D16
DDR_A_D17
<6>
<6>
DDR_A_MA[0..15]
DDR_A_DQS#2
DDR_A_DQS2
<6>
DDR_A_D18
DDR_A_D19
All VREF traces should

Layout Note:
Place near JDIMM1
DDR_A_D24
DDR_A_D25
+1.5V
DDR_A_D26
DDR_A_D27
C110
1U_0402_6.3V6K
C109
1U_0402_6.3V6K
C108
1U_0402_6.3V6K
C107
1U_0402_6.3V6K
<6>
<6>
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
+1.5V
DDR_A_MA3
DDR_A_MA1
C114
10U_0603_6.3V6M
C113
10U_0603_6.3V6M
C112
10U_0603_6.3V6M
C111
10U_0603_6.3V6M
DDR_A_MA8
DDR_A_MA5
<6>
<6>
<6>
+1.5V
@
2
SA_CLK_DDR0
SA_CLK_DDR#0
<6>
DDR_A_BS0
<6>
<6>
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDRA_CS1_DIMMA#
DDRA_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
1
+
C118
330U_D2_2V_Y
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
SGA20331E10
330U 2V H1.9
9mohm POLY
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
+0.75VS
DDR_A_D48
DDR_A_D49
C124
1U_0402_6.3V6K
C123
1U_0402_6.3V6K
C122
1U_0402_6.3V6K
C121
1U_0402_6.3V6K
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
Layout Note:
Place near JDIMM1.203,204
+3VS
205
G1
R60
TYCO_2-2013022-1
CONN@
10K_0402_5%
SP07000JN10
G2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
1
DIMM_DRAMRST#
DIMM_DRAMRST#
<6,12>
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDRA_CKE1_DIMMA
DDRA_CKE1_DIMMA
<6>
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
SA_CLK_DDR1
SA_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDRA_CS0_DIMMA#
SA_ODT0
SA_ODT1
SA_CLK_DDR1
SA_CLK_DDR#1
<6>
<6>
+1.5V
DDR_A_BS1
<6>
DDR_A_RAS#
<6>
DDRA_CS0_DIMMA#
SA_ODT0 <6>
SA_ODT1
<6>
R57
1K_0402_1%
<6>
+VREF_CA
DDR_A_D36
DDR_A_D37
1
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
R58
1K_0402_1%
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
D_CK_SDATA
D_CK_SCLK
D_CK_SDATA <12,14,30>
D_CK_SCLK <12,14,30>
+0.75VS
206
Channel A
R59
10K_0402_5%
C126
2.2U_0603_6.3V6K
C125
0.1U_0402_16V4Z
+0.75VS
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR_A_DQS#0
DDR_A_DQS0
C120
0.1U_0402_16V4Z
C117
10U_0603_6.3V6M
C116
10U_0603_6.3V6M
C115
10U_0603_6.3V6M
SA_CLK_DDR0
SA_CLK_DDR#0
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDR_A_D4
DDR_A_D5
C119
2.2U_0603_6.3V6K
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDRA_CKE0_DIMMA
DDRA_CKE0_DIMMA
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
2
R56
1K_0402_1%
C106
0.1U_0402_16V4Z
1
Q2
C105
2.2U_0603_6.3V6K
1
3
@
BSS138_NL_SOT23-3
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
SA_DIMM_VREFDQ
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
<9>
M3 support(unpop)
DDR_A_D0
DDR_A_D1
JDIMM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
+V_DDR_REFA
R54
1K_0402_1%
R55
0_0402_5%
1
2
@
+1.5V
<Address: SA1:SA0=00>
1/3 Modify
DIMM_1 Standard H:4.0mm

Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
Size
Document Number
Custom
DDRIII DIMMA
Rev
1.0
Date:
A
Sheet
E
11
of
45
+1.5V
+V_DDR_REFB
+1.5V
<6,11>
RST_GATE_R
DDR_B_DQS#[0..7]
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
<6>
DDR_B_DQS[0..7]
DDR_B_D[0..63]
DDR_B_D2
DDR_B_D3
DDR_B_D16
DDR_B_D17
<6>
<6>
DDR_B_MA[0..15]
DDR_B_DQS#2
DDR_B_DQS2
<6>
DDR_B_D18
DDR_B_D19
All VREF traces should

Layout Note:
Place near JDIMM2
DDR_B_D24
DDR_B_D25
+1.5V
DDR_B_D26
DDR_B_D27
C143
1U_0402_6.3V6K
C145
1U_0402_6.3V6K
C128
1U_0402_6.3V6K
C141
1U_0402_6.3V6K
<6>
DDRB_CKE0_DIMMB
DDRB_CKE0_DIMMB
<6>
DDR_B_BS2
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
+1.5V
DDR_B_MA3
DDR_B_MA1
C137
10U_0603_6.3V6M
C133
10U_0603_6.3V6M
C131
10U_0603_6.3V6M
C147
10U_0603_6.3V6M
<6>
<6>
<6>
SB_CLK_DDR0
SB_CLK_DDR#0
SB_CLK_DDR0
SB_CLK_DDR#0
DDR_B_MA10
DDR_B_BS0
<6>
DDR_B_BS0
<6>
<6>
DDR_B_WE#
DDR_B_CAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDRB_CS1_DIMMB#
DDRB_CS1_DIMMB#
+1.5V
@
2
DDR_B_DQS#4
DDR_B_DQS4
C139
330U_D2_2V_Y
@
DDR_B_D34
DDR_B_D35
SGA20331E10
330U 2V H1.9
9mohm POLY
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
+0.75VS
DDR_B_DQS#6
DDR_B_DQS6
C132
1U_0402_6.3V6K
C146
1U_0402_6.3V6K
C140
1U_0402_6.3V6K
C138
1U_0402_6.3V6K
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
Layout Note:
Place near JDIMM2.203,204
+3VS
R61
2 10K_0402_5%
R64
10K_0402_5%
C134
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
C135
+0.75VS
205
207
GND1
BOSS1
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DIMM_DRAMRST#
DIMM_DRAMRST#
<6,11>
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDRB_CKE1_DIMMB
DDRB_CKE1_DIMMB
<6>
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
SB_CLK_DDR1
SB_CLK_DDR#1
DDR_B_BS1
DDR_B_RAS#
DDRB_CS0_DIMMB#
SB_ODT0
SB_ODT1
SB_CLK_DDR1
SB_CLK_DDR#1
<6>
<6>
+1.5V
DDR_B_BS1
<6>
DDR_B_RAS#
<6>
DDRB_CS0_DIMMB#
SB_ODT0 <6>
SB_ODT1
<6>
R65
1K_0402_1%
<6>
+VREF_CB
DDR_B_D36
DDR_B_D37
1
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
C129
0.1U_0402_16V4Z
C130
10U_0603_6.3V6M
C142
10U_0603_6.3V6M
C149
10U_0603_6.3V6M
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
DDR_B_DQS#0
DDR_B_DQS0
C136
2.2U_0603_6.3V6K
DDR_B_D32
DDR_B_D33
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_B_D4
DDR_B_D5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
2
R63
1K_0402_1%
C148
0.1U_0402_16V4Z
1
Q3
C127
2.2U_0603_6.3V6K
1
3
@
BSS138_NL_SOT23-3
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
SB_DIMM_VREFDQ
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
R66
1K_0402_1%
1
<9>
DDR_B_D0
DDR_B_D1
R62
0_0402_5%
1
2
@
M3 support(unpop)
+1.5V
JDIMM2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
+V_DDR_REFB
R67
1K_0402_1%
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK
D_CK_SDATA <11,14,30>
D_CK_SCLK <11,14,30>
+0.75VS
206
208
TYCO_2-2013287-1
CONN@
SP07000KW00
Channel B
<Address: SA1:SA0=10>
12/21 Modify
DIMM_2 Reverse H:4.0mm
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
DDRIII DIMMB
Size
Document Number
Custom
Rev
1.0
Date:
A
Sheet
E
12
of
45
RTCRST close RAM door J1

1
+RTCBATT
1
C163
1U_0603_10V6K
@
2
2
R75
20K_0402_5%
1
2
R76
20K_0402_5%
20mil
2
PCH_RTCRST#
PCH_SRTCRST#
1
R77
0_0603_5%
D1
BAS40-04_SOT23-3
+RTCVCC
20mil
+CHGRTC
+RTCVCC
U16
R78
2 1M_0402_5%
SM_INTRUDER#
R79
2 330K_0402_5%
PCH_INTVRMEN
Integrated VRM enable

Integrated VRM disable
BD82HM70
HM70@
(INTVRMEN should always be pull high.)
D20
PCH_SRTCRST#
G22
SM_INTRUDER#
K22
PCH_INTVRMEN
C17
RTCX2
RTCRST#
FWH4 / LFRAME#
SRTCRST#
INTRUDER#
LDRQ0#
LDRQ1# / GPIO23
INTVRMEN
SERIRQ
HDA_SYNC_PCH
<31>
PCH_SPKR
N34
HDA_BCLK
L34
PCH_SPKR
T10
HDA_RST_PCH#
K34
HDA_SYNC
SPKR
HDA_RST#
E34
This signal has a weak internal pull-down
+5VS
G
1.8V when sampled low

Needs to be pulled High for Huron River platfrom
<31>
<31>
HDA_RST_AUDIO#
HDA_SDOUT_AUDIO
HDA_RST_PCH#
2 HDA_SDOUT_PCH
2
@
HDA_SYNC_AUDIO
HDA_SYNC_PCH_R
HDA_SDO
HDA_DOCK_EN# / GPIO33
N32
R91
51_0402_5%
2
1
R90
2
A36
C36
PCH_JTAG_TCK
J3
PCH_JTAG_TMS
H7
PAD
T9
PAD
T10 @
PCH_JTAG_TDI
K5
PAD
T11 @
PCH_JTAG_TDO
H1
1 33_0402_5%
PCH_SPI_CLK_1
R98
1 33_0402_5%
PCH_SPI_CLK
T3
PCH_SPI_CS0#_1
R100
1 33_0402_5%
PCH_SPI_CS0#
Y14
PCH_SPI_CS1#_2
R101
1 33_0402_5%
PCH_SPI_CS1#
T1
2
2
R103
1 33_0402_5%
1 33_0402_5%
PCH_SPI_MOSI
JTAG_TCK
JTAG_TMS
JTAG_TDI
SATAICOMPO
SATAICOMPI
Y1
+3VS
18P_0402_50V8J
HM70 not support

SATA for port1/port3
Y11
L=500mil S=15mil
Y10
SATA_COMP
2
37.4_0402_1%
R94
AB12
L=500mil S=15mil
AB13
SATA3_COMP
AH1
RBIAS_SATA3
+1.05VS_VTT
2
49.9_0402_1%
2
750_0402_1%
R97
SATA3RBIAS
R99
+3VS
R102
4.7K_0402_5%
SPI_CS1#
SPI_MOSI
SATALED#
P3
PCH_SATALED#
V14
PCH_GPIO21
P1
PCH_GPIO19
PCH_GPIO19
SATA0GP / GPIO21
SPI_MISO
33_0402_5%
SATA1GP / GPIO19
No use PU 10K +3VS
Debug Port DG 1.2 PU 4.7K +3VS
GPIO19 has internal Pull up
Boot BIOS Strap

Reserve for EMI
+3VS
PCH_SPI_CS0#_1
SPI_WP1#
SPI_HOLD1#
2 3.3K_0402_5%
2 3.3K_0402_5%
1
3
7
4
CS#
WP#
HOLD#
GND
VCC
SCLK
SI
SO
8
6
5
2
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
MX25L3206EM2I-12G_SO8
SA000041P00
+3VS
+3VS
U18
R111
+1.05VS_VTT
COUGARPOINT_FCBGA989
HM77@
+3VS
C168
18P_0402_50V8J
PCH_SPI_CS1#_2
PCH_SPI_MISO_2
2 3.3K_0402_5% SPI_WP2#
SPI ROM FOR ME (1MB)

Footprint 200mil
PCH_SPI_CLK
33_0402_5%
PCH_SPI_CLK_1
33_0402_5%
PCH_SPI_CLK_2
33_0402_5%
1
2
3
4
CS#
SO
WP#
GND
VCC
HOLD#
SCLK
SI
8
7
6
5
SPI_HOLD2#
PCH_SPI_CLK_2
PCH_SPI_MOSI_2
MX25L8006EM2I-12G_SO8
SA000041O00
R112
1
2
3.3K_0402_5%
2
R110
2
R466
22P_0402_50V8J
1
2 C465
@
2
R467
22P_0402_50V8J
1
2 C466
@
11/30 Add
LPC
Reserved
SPI
2011/11/22
2012/11/22
Deciphered Date
C
GPIO51
0
0
1
1
GPIO19
0
1
0
1
Compal Secret Data
Issued Date
Boot BIOS
C166
10P_0402_50V8J
1
2
@
Title
PCH (1/9) SATA,HDA,SPI, LPC, XDP

Custom
Rev
1.0
Date:
A
R86
10K_0402_5% @
R234
1K_0402_5%
@
HDD1
PCH_SPI_MISO
12/7 Change symbol of U18 from SA00000XT00 to SA000041O00
C167
PCH_GPIO21
12/1 Del
32.768KHZ_12.5PF_1TJF125DP1A000D
<29,30>
SATA_PRX_DTX_N0 <24>
SATA_PRX_DTX_P0 <24>
SATA_PTX_DRX_N0 <24>
SATA_PTX_DRX_P0 <24>
U17
R109 1
R108 1
SERIRQ
SPI_CS0#
V4
33_0402_5%
SPI ROM FOR ME (4MB)

Footprint 200mil
SPI_CLK
R85
10K_0402_5%
R230
10K_0402_5%
Y3
Y1
AB3
AB1
JTAG_TDO
U3
PCH_RTCX1
PCH_RTCX2
SERIRQ
+3VS
+3VS
<29,30>
Y7
Y5
AD3
AD1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SPI
R96
2
PCH_SPI_MISO_1
R105
2
PCH_SPI_MISO_2
R106
2
10M_0402_5%
PCH_GPIO23
LPC_FRAME#
AB8
AB10
AF3
AF1
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA3COMPI
R104
1
R107
E36
K36
V5
AD7
AD5
AH5
AH4
SATA3RCOMPO
PCH_SPI_CLK_2
PCH_SPI_MOSI_2
PCH_SPI_MOSI_1
LPC_FRAME#
<29,30>
<29,30>
<29,30>
<29,30>
AM10
AM8
AP11
AP10
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
HDA_DOCK_RST# / GPIO13
0_0402_5%
R93
1M_0402_5%
2
<31>
3
2 HDA_BITCLK_PCH
HDA_SDIN3
HDA_BITCLK_AUDIO
HDA_SDOUT_PCH
Q4
BSS138_NL_SOT23-3
1HDA_SYNC_PCH
<31>
HDA_SDIN2
A34
Prevent back drive issue.
D36
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
AM3
AM1
AP7
AP5
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
HDA_SDIN1
C34
On Die PLL VR Select is supplied by
R88
33_0402_5%
1
R89
33_0402_5%
1
R92
33_0402_5%
1
R95
33_0402_5%
1
HDA_SDIN0
G34
SATA
HDA_SDIN0
HDA_SDIN0
IHDA
<31>
HDA_SYNC_PCH
1.5V when sampled high
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
PCH_GPIO23
HDA_BITCLK_PCH
JTAG
1 1K_0402_5%
C38
A38
B37
C37
C467
22P_0402_50V8J
@
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
PCH_RTCRST#
RTCX1
+VCCSUS3_3
2
1 10K_0402_5%
HDA_SDOUT_PCH
ME debug mode,this signal has a weak internal PD

Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
R87
C20
HDA_BITCLK_AUDIO
HDA_SDO
R81
HDA_SDO
PCH_SATALED#
<29>
R84
1K_0402_5%
2
1
@
R83
0_0402_5%
2
1
1 10K_0402_5%
11/30 Add (EMI request)

+VCCSUS3_3
PCH_RTCX2
SATA 6G
LOW= Disable (Default internal PD)
HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature
A20
LPC
PCH_SPKR
PCH_RTCX1
RTC
2 1K_0402_5%
R80
U16A
+3VS
1
SERIRQ
SA00005MQ60
R82
20mil
+3VS
INTVRMEN
3/7 Add
C165
0.1U_0402_16V4Z
C164
1U_0603_10V6K
+RTCVCC
R74
0_0603_5%
Sheet
E
13
of
45
+VCCSUS3_3
U16B
1 10K_0402_5%
MINI1_CLKREQ#
R123
1 10K_0402_5%
PCH_GPIO20
+VCCSUS3_3
R124
R126
1 10K_0402_5%
PCH_GPIO73
1 10K_0402_5%
LAN_CLKREQ#
R127
1 10K_0402_5%
PCH_GPIO26
R128
1 10K_0402_5%
PCH_GPIO44
R129
1 10K_0402_5%
PCH_GPIO45
R130
1 10K_0402_5%
PCH_GPIO46
R142
1 10K_0402_5%
PCH_GPIO56
HM70 not support

PCIE port 5-8
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40
BE38
BC38
AW 38
AY38
Y40
Y39
No use PU 10K +3VALW

<27>
<27>
WLAN
No use PU 10K +3VS
PCH_GPIO73
AB49
AB47
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
<27>
MINI1_CLKREQ#
J2
MINI1_CLKREQ#
M1
AA48
AA47
PCH_GPIO20
No use PU 10K +3VS

<25>
<25>
PCIE LAN
Y37
Y36
CLK_PCIE_LAN#
CLK_PCIE_LAN
<25>
LAN_CLKREQ#
V10
LAN_CLKREQ#
A8
Y43
Y45
PCH_GPIO26
L12
V45
V46
PCH_GPIO44
L14
AB42
AB40
PCH_GPIO56
E6
V40
V42
PCH_GPIO45
PCH_GPIO46
T13
V38
V37
K12
AK14
AK13
PERN5
PERP5
PETN5
PETP5
SML0DATA
SML1ALERT# / PCHHOT# / GPIO74

SML1CLK / GPIO58
SML1DATA / GPIO75
PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
CL_CLK1
CL_DATA1
CL_RST1#
A12
<27> DDR,WLAN,SMBUS
PCH_SMBDATA
RST_GATE
RST_GATE
C8
PU 2.2K +3VALW
<27>
<6>
S3 reduse
PCH_SMBCLK
R114
2.2K_0402_5%
PCH_SMBDATA
R115
2.2K_0402_5%
RST_GATE
R116
1K_0402_5%
PCH_GPIO74
R117
10K_0402_5%
PCH_SML1CLK
R118
2.2K_0402_5%
PCH_SML1DATA
R119
2.2K_0402_5%
PCH_GPIO47
R120
10K_0402_5%
G12
C13
PCH_GPIO74
E14
PCH_SML1CLK
EC-PCH SMBUS
M16
PCH_SML1DATA
PU 2.2K +3VALW
S3 reduse
+3VS
For DDR , TP
R122
4.7K_0402_5%
1
2
M7
PCH_SMBDATA 6
T11
Q5A
DMN66D0LDW-7_SOT363-6
P10
+3VS
D_CK_SDATA
D_CK_SDATA
<11,12,30>
D_CK_SCLK
<11,12,30>
R125
4.7K_0402_5%
1
2
+3VS
D_CK_SCLK
Q5B
PEG_A_CLKRQ# / GPIO47
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCH_SMBDATA
<29>
10K_0402_5%
PCH_SMBCLK
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
C9
SMB_ALERT#
PCH_SMBCLK
R121
BG37
BH37
AY36
BB36
SML0CLK
PCH_SMBCLK
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
M10
PCH_GPIO47
+3VS
Pull up at EC side.
AB37
AB38
PCH_SML1DATA 6
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_DMI2_N
CLKIN_DMI2_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
CLKIN_PCILOOPBACK
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
XTAL25_IN
XTAL25_OUT
AV22
AU22
CLK_CPU_DMI#
CLK_CPU_DMI
AM12
AM13
CLK_CPU_DPLL#
CLK_CPU_DPLL
CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
CLK_CPU_DPLL# <5>
CLK_CPU_DPLL <5>
120MHz for eDP.
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
R131 1
R132 1
2 10K_0402_5%
2 10K_0402_5%
BJ30
BG30
CLKIN_GND1#
CLKIN_GND1
R133 1
R134 1
2 10K_0402_5%
2 10K_0402_5%
G24
E24
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
R135 1
R136 1
2 10K_0402_5%
2 10K_0402_5%
AK7
AK5
CLK_BUF_PCIE_SATA# R137 1
CLK_BUF_PCIE_SATA
R138 1
2 10K_0402_5%
2 10K_0402_5%
K45
CLK_BUF_ICH_14M
R139 1
2 10K_0402_5%
H45
CLK_PCI_LPBACK
V47
V49
XTAL25_IN
XTAL25_OUT
2
1
R140 @
33_0402_5%
Y47
PCH_SML1CLK
1
C175 @
CLK_PCI_LPBACK
2
22P_0402_50V8J
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
CLKOUTFLEX3 / GPIO67
EC_SMB_CK2
EC_SMB_CK2
<29>
XCLK_RCOMP
+1.05VS_VTT
XTAL25_IN
2
1M_0402_5%
R144
<29>
<17>
XTAL25_OUT
EC_SMB_DA2
Pull down 10K ohm

for using internal Clock
Q6B
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
EC_SMB_DA2
Reserve for EMI please close to PCH

R141
90.9_0402_1%
1
2
W=12mil S=15mil
XCLK_RCOMP
Q6A
BF18
BE18
PEG_B_CLKRQ# / GPIO56
+3VS
PERN4
PERP4
PETN4
PETP4
SML0ALERT# / GPIO60
SMB_ALERT#
R113
BF36
BE36
AY34
BB34
PERN3
PERP3
PETN3
PETP3
E12
H14
SMB_ALERT#
BG36
BJ36
AV34
AU34
Link
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
SMBDATA
SMBUS
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PERN2
PERP2
PETN2
PETP2
Controller
C169
C174
1
1
SMBCLK
FLEX CLOCKS
PCIE LAN
<25> PCIE_PRX_DTX_N3
<25> PCIE_PRX_DTX_P3
<25> PCIE_PTX_C_DRX_N3
<25> PCIE_PTX_C_DRX_P3
C170
C171
BE34
BF34
BB32
AY32
SMBALERT# / GPIO11
CLOCKS
WLAN
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PERN1
PERP1
PETN1
PETP1
PCI-E*
BG34
BJ34
AV32
AU32
K43
CLK_FLEX0
F47
CLK_FLEX1
H47
CLK_FLEX2
K49
CLK_FLEX3
T12
PAD
T13
PAD
T14
PAD
T33
PAD
25MHZ_10PF_7V25000014
3
1
C176
12P_0402_50V8J
1
GND
4
GND
Y2
1
1
C177
12P_0402_50V8J
HM77@
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
PCH (2/9) PCIE, SMBUS, CLK
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
Rev
1.0
Date:
A
Sheet
E
14
of
45
U16C
1 10K_0402_5%
PCH_ACIN
+VCCSUS3_3
1
R153
1 10K_0402_5%
SUSWARN#_R
R154
1 10K_0402_5%
PCH_GPIO72
R155
1 10K_0402_5%
RI#
R157
1 200_0402_5%
PM_DRAM_PWRGD
1 10K_0402_5%
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<4>
<4>
<4>
<4>
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
<4>
<4>
<4>
<4>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
AW24
AW20
BB18
AV18
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AY24
AY20
AY18
AU18
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
+1.05VS_VTT
BJ24
L=500mil S=15mil
PCH_RSMRST#
1
R160
1
R161
DMI_ZCOMP
BG25
2
DMI_IRCOMP
49.9_0402_1%
2
DMI2RBIAS
750_0402_1%
BH21
FDI_FSYNC0
DMI_IRCOMP
FDI_FSYNC1
DMI2RBIAS
FDI_LSYNC0
FDI_LSYNC1
4mil width and place

within 500mil of the PCH
<5>
SUSACK#
XDP_DBRESET#
2
SUSACK#_R
0_0402_5%
2 XDP_DBRESET#_R
0_0402_5%
R164
not support AMT APWROK can mux

with PWROK (check list1.5 P.47)
PCH_PWROK
DSWVRMEN
2 0_0402_5%
1 DS3@
1
R166
C12
SUSACK#
K3
SYS_PWROK
P12
2 PCH_PWROK_R
0_0402_5%
L22
SYS_RESET#
SYS_PWROK
PWROK
L10
<5>
PM_DRAM_PWRGD
<29>
<29>
1/11 Add "ACPRESENT" signal. (follow Q5LJ1)
PCH_RSMRST#
R179 1 S3@
1 DS3@
R196
SUS_PWR_DN_ACK
<29> SUSWARN#
<29>
<29>
1
2
0_0402_5%
ACPRESENT
B13
PCH_RSMRST#
C21
2 0_0402_5%
2
0_0402_5%
PBTN_OUT#
R177
PM_DRAM_PWRGD
SUSWARN#_R
APWROK
DRAMPWROK
RSMRST#
K16
PBTN_OUT#
E20
PCH_ACIN
H20
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
AW16
FDI_INT
AV12
FDI_FSYNC0
BC10
FDI_FSYNC1
AV14
FDI_LSYNC0
BB10
FDI_LSYNC1
A18
E22
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
FDI_INT
<29,33,36>
ACIN
RB751V-40_SOD323-2
PCH_GPIO72

3
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#

PWRBTN#
Ring Indicator CRB1.0 PU 10K +3VALW
E10
A10
RI#
DSWODVREN
R150
R152
1 330K_0402_5%
1 330K_0402_5%
DSWODVREN - On Die DSW VR Enable

H Enable internal DSW +1.05VS
1
L Disable
Must always PU at +RTCVCC
+VCCSUS3_3
PCH_PCIE_WAKE# R156
PCH_GPIO29
R158
CLKRUN#
R162
2 10K_0402_5%
<4>
FDI_FSYNC0
<4>
FDI_FSYNC1
<4>
FDI_LSYNC0
<4>
FDI_LSYNC1
<4>
2 10K_0402_5%
+3VS
2 8.2K_0402_5%
DSWODVREN
R483 1
1
R482
0_0402_5%
S3@ 2 PCH_RSMRST#
2
DS3@ 0_0402_5%
B9
PCH_PCIE_WAKE#
N3
CLKRUN#
G8
SUS_STAT#
N14
SUSCLK
D10
PM_SLP_S5#
H4
PM_SLP_S4#
F4
PM_SLP_S3#
G10
SLP_A#
G16
SLP_SUS#
PCH_DPWROK
<29>
not support Deep S4,S5 DPWROK mux with

RSMRST#
check list1.5 P.50
PCH_PCIE_WAKE#
CLKRUN#
<25,27>
PCH_DPWROK
No use PU 10K +3VS
<30>
R165
100K_0402_5%
@
T15 @ PAD
SLP_A#
SUSCLK
T34 @ PAD
T35 @ PAD
T36 @ PAD
<29>
PM_SLP_S5#
<29>
PM_SLP_S4#
<29>
PM_SLP_S3#
<29>
T16 @ PAD
D2 @
PCH_ACIN
+RTCVCC
<29>
SUSACK#
R163
System Power Management
R178 1 S3@
SUS_PWR_DN_ACK
not support Deep S4,S5

can be left unconnected.
Check list1.5 P.81
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
Follow Tacoma 1.0

R159
<4>
<4>
<4>
<4>
BC24
BE20
BG18
BG20
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
FDI
R151
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI
+3VALW_PCH
<4>
<4>
<4>
<4>
ACPRESENT / GPIO31
SLP_SUS#
BATLOW# / GPIO72
PMSYNCH
RI#
SLP_LAN# / GPIO29
AP14
H_PM_SYNC
K14
PCH_GPIO29
SLP_SUS#
H_PM_SYNC
<29>
Can be left NC
when IAMT is not
support on the
platfrom
not support
Deep S4,S5 can NC
PCH EDS1.5 P.75
<5>
3
HM77@
+3VS
ALL power OK
Y
A
SYS_PWROK
SYS_PWROK
R168
10K_0402_5%
R167
10K_0402_5%
<5>
VGATE
<41>
C178
@
0.047U_0402_16V7K
2
U19
2
B
PCH_PWROK
<29>
tell PCH all power ok

but cpu core
Issued Date
Compal Secret Data
2011/11/22
Deciphered Date
2012/11/22
Title
PCH (3/9) DMI,FDI,PM
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
Rev
1.0
Date:
A
Sheet
E
15
of
45
IGPU_BKLT_EN
PD 100K
at EC side
1
<22>
PCH_ENVDD
<22>
DPST_PWM
<22>
<22>
+3VS
1 LVDS@ 2 2.2K_0402_5%
CTRL_CLK
R172
1 LVDS@ 2 2.2K_0402_5%
CTRL_DATA
PCH_LCD_CLK
PCH_LCD_DATA
R171
DIS only can NC
2.37K_0402_1%
2
1
2
R173
0_0402_5%
1 LVDS@ 2 2.2K_0402_5%
PCH_LCD_CLK
R175
1 LVDS@ 2 2.2K_0402_5%
PCH_LCD_DATA
CTRL_CLK
CTRL_DATA
W=10mil S=30mil
UMA LVDS DDC

R174
T40
K47
L=500mil S=30mil
Change to eDP only

R170
P45
Check list1.5 P.60 disable Graphics

ALL Can NC
but DAC_IREF still need PD
LVDS disable:
DATA/Clock/Control an NC
VCC_TX_LVDS,VCCA_LVDS PD to GND
<22>
<22>
PCH_TXCLKPCH_TXCLK+
<22>
<22>
<22>
PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-
<22>
<22>
<22>
PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+
T45
P39
LVDS_IBG
AF37
AF36
LVD_VREF
AE48
AE47
1
PCH_TXCLKPCH_TXCLK+
AK39
AK40
PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+
AF40
AF39
UM77 not support

LVDS/CRT
AH45
AH47
AF49
AF45
+3VS
R484
R485
1
1
2 2.2K_0402_5%
2 2.2K_0402_5%
PCH_CRT_CLK
PCH_CRT_DATA
R486
R487
R488
1
1
1
2 150_0402_1%
2 150_0402_1%
2 150_0402_1%
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
AH43
AH49
AF47
AF43
<24>
<24>
<24>
<24>
<24>
<24>
<24>
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_CRT_CLK
PCH_CRT_DATA
PCH_CRT_HSYNC
PCH_CRT_VSYNC
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
N48
P49
T49
PCH_CRT_CLK
PCH_CRT_DATA
T39
M40
PCH_CRT_HSYNC
PCH_CRT_VSYNC
M47
M49
T43
T42
SDVO_TVCLKINN
SDVO_TVCLKINP
L_BKLTCTL
SDVO_STALLN
SDVO_STALLP
L_DDC_CLK
L_DDC_DATA
SDVO_INTN
SDVO_INTP
LVD_IBG
LVD_VBG
SDVO_CTRLCLK
SDVO_CTRLDATA
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
R531
FBMA-11-100505-301T 0402
AM42
AM40
AP39
AP40
SDVO_CTRLDATA strap pull high

at level shift page
P38
M39
SDVO_SCLK
SDVO_SDATA
AT49
AT47
AT40
PCH_DPB_HPD
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3
SDVO_SCLK <23>
SDVO_SDATA <23>
PCH_DPB_HPD
<23>
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3
<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
HM77@
R176
1K_0402_0.5%
AP43
AP45
L_CTRL_CLK
L_CTRL_DATA
CRT_IREF
CRT_IRTN
L_BKLTEN
L_VDD_EN
Digital Display Interface
1 0_0402_5%
LVDS
ENBKL
J47
M45
IGPU_BKLT_EN
CRT
<29>
R169
U16D
UMA Panel Backlight ON/OFF

ENBKL
Issued Date
Compal Secret Data
2011/11/22
Deciphered Date
2012/11/22
Title
PCH (4/9) LVDS,CRT,DP,HDMI
Document Number
Custom
Rev
1.0
Date:
A
Sheet
E
16
of
45
U16E
1
1
1
1
R469
R470
R471
R472
PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQD#
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
2
2
2
2
1
1
1
1
R473
R474
R475
R476
PCH_GPIO55
PCH_GPIO53
PCH_GPIO52
PCH_GPIO5
8.2K_0402_5% 2
8.2K_0402_5% 2
1
1
R477
R478
PCH_GPIO51
PCH_GPIO2
8.2K_0402_5% 2
R480
PCH_GPIO4
8.2K_0402_5% 2
10K_0402_5% 2
1
1
R523
R180
PCH_GPIO3
PCH_GPIO54
B21
M20
AY16
BG46
+3VS
2
8.2K_0402_5%
PCH_GPIO50
<28>
PCH_USB3_RX2_N
<28>
PCH_USB3_RX2_P
PCH_USB3_RX2_N
PCH_USB3_RX2_P
USB3.0
<28>
PCH_USB3_TX2_N
PCH_USB3_TX2_N
Boot BIOS Strap

GPIO19 GPIO51 Boot BIOS
Bit10 Destination
<28>
PCH_USB3_TX2_P
PCH_USB3_TX2_P
Bit11
GNT1#/
GPIO51
Internal
PH
TP21
TP22
TP23
TP24
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
NV_ALE
NV_CLE
NV_RCOMP
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
NV_RE#_WRB0
NV_RE#_WRB1
NV_WE#_CK0
NV_WE#_CK1
Reserved
PCI
SPI
LPC
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
K40
K38
H38
G38
CR Check list 1.5 only use for GPIO

No use PU +3VS
PCH_GPIO50
PCH_GPIO52
PCH_GPIO54
C46
C44
E40
PCH_GPIO51
PCH_GPIO53
PCH_GPIO55
D47
E42
F46
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
PCI Interrupt Requests
CR Check list 1.5 only use for GPIO

PH(Internal PH),
GPIO PU +3VS
PAD
<5>
<14>
<29>
<30>
CLK_PCI_LPBACK
CLK_PCI_LPC
CLK_PCI_TPM
CLK_PCI_LPBACK
CLK_PCI_LPC
CLK_PCI_TPM
R191
R192
R193
K10
T17 @
PLT_RST#
PLT_RST#
1
1
1
2 22_0402_5% CLK_PCI0
2 22_0402_5% CLK_PCI1
2 22_0402_5% CLK_PCI2
CLK_PCI3
T18 @
CLK_PCI4
T19 @
PAD
PAD
C6
H49
H43
J48
K42
H40
PIRQA#
PIRQB#
PIRQC#
PIRQD#
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AY1
DF_TVS
*Note:457511 Rev 1.3-p.20
DMI,FDI Termination Voltage
AV10
AT8
DF_TVS
AY5
BA2
AT12
BF3
Set to Vcc when HIGH
HR CPU NC
Set to Vss when LOW
HR&CR co-lay CPU PU
CR Check list P.89 PU 2.2K series 1K

+1.8VS
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
USB
NV_DQS0
NV_DQS1
NV_RB#
2
8.2K_0402_5%
1
R182
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
PCI
1
R181
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
2
2
2
2
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
<28>
<28>
<28>
<28>
<28>
<28>
USB2 (Left side2)
USBRBIAS
EHCI 1
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
R184
USB20_N8
USB20_P8
USB20_N8
USB20_P8
USB20_N10
USB20_P10
USB20_N10
USB20_P10
<27>
<27>
Mini Card (WLAN)
<22>
<22>
<5>
+VCCSUS3_3
CMOS Camera (LVDS)
EHCI 2
USB_OC0#
USB_OC7#
USB_OC5#
USBRBIAS
B33
A14
K20
B17
C16
L16
A16
D14
C14
H_SNB_IVB#
HM70 not support USB2.0 for port 4-7 &12 &13
1
R189
2
22.6_0402_1%
USB_OC1#
USB_OC4#
L=500mil S=15mil
USB_OC3#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
1
1K_0402_5%
CLOSE TO THE BRANCHING POINT
PME#
PLTRST#
DF_TVS
USB2 (Left side1)
USB_OC6#
USBRBIAS#
C33
R183
2.2K_0402_5%
USB3 (Left side)

2
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
NVRAM
12/6 Add R469~R480
RSVD
+3VS
Only GPIO
function
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC0#
USB_OC1#
<28>
<28>
USB_OC2#
2
R185
2
R186
2
R187
2
R188
2
R197
2
R208
2
R215
2
R217
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%

HM77@
C469
@
CLK_PCI_LPC
22P_0402_50V8J
C474
@
CLK_PCI_LPBACK
22P_0402_50V8J
C482
@
CLK_PCI_TPM
22P_0402_50V8J
R194
0_0402_5%
2
1
@
+3VS
PLT_RST_BUF#
<25,27,29,30>
Issued Date
Compal Secret Data
R195
100K_0402_5%
PLT_RST#
U20
2
B
1
A
2011/11/22
2012/11/22
Deciphered Date
Title
PCH (5/9) PCI, USB, NVRAM
Rev
1.0
Date:
A
Sheet

E
17
of
45
HDA_SYNC PH(PLL =+1.5VS)
1
R204
10K_0402_5%
U16F
A42
No use PU 10K +3VS
PCH_GPIO6
H36
EC_SCI#
E38
EC_SMI#
C10
2 10K_0402_5%
<29>
EC_SMI#
No use PU +3VALW
<29>
EC_LID_OUT#
No use PU +3VS
PCH_GPIO27
+3VS
R211
EC_SCI#
1 200K_0402_5% PCH_GPIO36
No use PU +3VS
R214
2 1K_0402_5%
EC_SMI#
EC_LID_OUT#
G2
PCH_GPIO16
U2
PCH_GPIO17
D40
RAM flag
PCH_GPIO22
T5
No use PU +3VALW
DDR3/DDR3L
PCH_GPIO24
E8
No use PD 10K to GND
PCH_GPIO27
E16
PCH_GPIO28
P8
No use PU 10K +3VS
BT ON/OFF
PAD
T20 @
Can't PU
PCH_GPIO34
K1
PCH_GPIO35
K4
PCH_GPIO36
V8
PCH_GPIO37
M5
No use PU 10K +3VS
PCH_GPIO38
N2
No use PU 10K +3VS
PCH_GPIO39
M3
No use PU 10K +3VS
PCH_GPIO48
V13
SATA5GP&TEMP_ALERT# CRB PU 10K +3VS
PCH_GPIO49
V3
No use PU +3VALW
PCH_GPIO57
D6
PAD
Can't PU
SATA2GP/GPIO36 & SATA3GP/GPIO37
Sampled at Rising edge of PWROK.
Weak internal pull-down.
(weak internal pull-down is disabled
after PLTRST# de-asserts)
NOTE: This signal should NOT be
pulled high when strap is sampled
C4
No use PU 10K +3VS
No use can NC
+3VALW_PCH
PCH_GPIO12
RAM flag
T21 @
TACH5 / GPIO69
TACH2 / GPIO6
TACH6 / GPIO70
TACH3 / GPIO7
TACH7 / GPIO71
+3VS
A45
R216
2 10K_0402_5%
PCH_GPIO0
A46
R218
2 10K_0402_5%
PCH_GPIO1
R219
2 10K_0402_5%
PCH_GPIO6
R220
2 10K_0402_5%
PCH_GPIO16
B3
R221
2 10K_0402_5%
PCH_GPIO17
B47
R522
2 10K_0402_5%
PCH_GPIO38
BD1
A5
A6
BD49
12/13 Add
R222
2 10K_0402_5%
PCH_GPIO34
BE1
R223
2 10K_0402_5%
PCH_GPIO48
BE49
R225
2 10K_0402_5%
PCH_GPIO49
BF1
+VCCSUS3_3
BF49
+VCCSUS3_3
PCH_GPIO69
C41
PCH_GPIO70
A40
PCH_GPIO71
+3VS
R206
10K_0402_5%
LAN_PHY_PWR_CTRL / GPIO12
GPIO15
A20GATE
SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24 / MEM_LED
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
P4
GATEA20
AU16
PCH_PECI_R
P5
EC_KBRST#
1
2
@
0_0402_5% R207
GPIO28
NC_1
STP_PCI# / GPIO34
NC_2
GPIO35
NC_3
SATA2GP / GPIO36
NC_4
SATA3GP / GPIO37
NC_5
H_PECI
AY10
PECI CPU-EC
CTRL+ALT+DEL
<29>
H_CPUPWRGD
PCH_THRMTRIP#_R 1
R210
non CPU power ok
<5>
2
H_THRMTRIP#
390_0402_5%
H_THRMTRIP#
INIT3_3V
Checklist1.5 P.69
+3VS
This signal has weak internal

PU, can't pull low,leave NC
AH8
AK11
AH10
TS_VSS1~4
PD to GND
AK10
2 10K_0402_5%
PCH_GPIO12
2 1K_0402_5%
EC_LID_OUT#
R232
2 10K_0402_5%
PCH_GPIO57
2 10K_0402_5%
R213
2 10K_0402_5%
P37
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48
VSS_NCTF_15
SATA5GP / GPIO49
VSS_NCTF_16
GPIO57
VSS_NCTF_17
VSS_NCTF_1
VSS_NCTF_19
VSS_NCTF_2
VSS_NCTF_20
VSS_NCTF_3
VSS_NCTF_21
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_6
VSS_NCTF_24
VSS_NCTF_7
VSS_NCTF_25
VSS_NCTF_8
VSS_NCTF_26
VSS_NCTF_9
VSS_NCTF_27
VSS_NCTF_10
VSS_NCTF_28
VSS_NCTF_11
VSS_NCTF_29
VSS_NCTF_12
VSS_NCTF_30
VSS_NCTF_13
VSS_NCTF_31
VSS_NCTF_14
VSS_NCTF_32
BG2
BG48
BH3
BH47
BJ4
9/15 Layout
request remove
Test point
They will route
by itself
BJ44
BJ45
BJ46
BJ5
3
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
+3VS
PCH_GPIO24
+3VS
R229
10K_0402_5%
2 10K_0402_5%
R231
10K_0402_5%
PCH_GPIO39
GPIO36/GPIO37 is Strap functionality

that requires internal pull down to be sampled at rising PWROK.
When uses as SATA2GP/SATA3GP for mechanical presence detect
-use a external pull up 150K-200K ohm to Vcc3_3
When used as GP input
-ensure GPI is not driven high during strap sampling window
When Unused as GPIO or SATA*GP
-use 8.2K-10K pull-down
check list page 47
R233
10K_0402_5%
@
R235
10K_0402_5%
@
Issued Date
2011/11/22
Compal Secret Data
PCH_GPIO22
GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.
CRB1.0 PU 10K to +3VALW
SLOAD / GPIO38
R226
R212
PCH_GPIO68
R228
2 10K_0402_5%
EC_KBRST#
R227
130c shut down
<5>
T14
HM77@
R224
<29>
<5,29>
EC_KBRST#
AY11
GPIO27
NCTF
A44
9/15 Layout
request remove
Test point
They will route
by itself
PCH_GPIO68
B41
GPIO8
VSS_NCTF_18
A4
C40
<29>
No use PU +3VALW
Deep S4,S5 wake event signal

RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal
R209
No use PU 10K +3VS
TACH4 / GPIO68
TACH1 / GPIO1
Debug Port DG 1.2 PU 4.7K +3VALW_PCH
BMBUSY# / GPIO0
PCH_GPIO1
No use PU 10K +3VS
T7
PCH_GPIO0
CPU/MISC
R205
1K_0402_5%
No use PU 10K +3VS
GPIO
PCH_GPIO28
LVDS
eDP
PCH_GPIO70
R203
10K_0402_5%
R202
4.7K_0402_5%
PCH_GPIO69
R201
10K_0402_5%
EDP@
PCH_GPIO71
GPIO71
1
0
Fan Tachometer Inputs

TACH1~7 only on server
can insted to GPIO
R200
10K_0402_5%@
11/21 EDP@->POP
+VCCSUS3_3
LVDS/eDP
R199
10K_0402_5%
@
2
R198
10K_0402_5%
LVDS@
H On-Die PLL voltage regulator enable

L On-Die PLL Voltage Regulator disable
+3VS
This signal has a weak internal pull up
+3VS
1
+3VS
GPIO28
On-Die PLL Voltage Regulator
2012/11/22
Deciphered Date
Title
PCH (6/9) GPIO, CPU, MISC
Rev
1.0
Date:
A
Sheet

E
18
of
45
Thermal Senser share with VCCADAC power rail

so can't remove this power
POWER
1/10 Add
C183
0.01U_0402_16V7K 0.1U_0402_16V7K
2
2
VSSALVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
60mA VCCTX_LVDS[3]
VCCTX_LVDS[4]
AK37
R237
0_0402_5%
EDP@
AM37
AM38
AN17
AN21
AN26
AN27
+1.05VS_VTT
AP21
AP23
AP24
AP26
AT24
AN33
Place Near AN16,AN21,AN33
AN34
+3VS
BH29
1
Place Near
BH29
C196
0.1U_0402_16V7K
AP16
@
T23
+1.05VS_VCCAPLL_FDI
BG6
AP37
3799mA
VCC3_3[6]
1
3
0921 LVDS@->POP
LVDS@
C186
LVDS@
C187
0.01U_0402_16V7K
+VCCTX_LVDS
LVDS@
C188
22U_0805_6.3V6M
Near
AU20
C484
22U_0805_6.3V6M
@
L2
0.1UH_MLF1608DR10KT_10%_1608
2
1
LVDS@
R238
0_0402_5%
EDP@
0.01U_0402_16V7K
V34
0.1uH inductor, 200mA

1121 EDP@->POP
I/O Buffer Voltage
C189
0.1U_0402_16V7K
VCCIO[17]
VCCVRM[3]
AT16
VCCIO[21]
VCCIO[23]
VCCIO[24]
Internal PLL and VRM(+1.5VS)
+1.05VS_VTT
VCCIO[20]
VCCIO[22]
PCH Power Rail Table
+1.5VS
VCCIO[18]
VCCIO[19]
VCCDMI[1]
47mA
VCCIO[1]
AT20
1
AB36
DMI buffer logic
C195
1U_0402_6.3V6K
place
near AT20
VCCIO[26]
VCCPNAND[1]
VCC3_3[3]
VCCVRM[2]
VCCFDIPLL
VCCPNAND[2]
VCCPNAND[3]
AG16
1
AJ16
2
VCCPNAND[4]
VccDFTERM should PH +1.8VS or +3VS
AG17
AJ17
VCCIO[27]
VCCDMI[2]
10mA
HM77@
VCCSPI
S0 Iccmax
Current(A)
V_PROC_IO
1.05
0.002
Processor I/F
0.001
PCH Core Well Reference Voltage
0.001
Suspend Well Reference Voltag
Vcc3_3
3.3
0.178
I/O Buffer Voltage
VccADAC
3.3
0.063
Display DAC Analog Power. This power is

supplied by the core well.
VccADPLLA
1.05
0.075
Display PLL A power
C197
0.1U_0402_16V7K
VccADPLLB
1.05
0.075
Display PLL B power
place
near AG16
VccCore
1.05
1.73
Internal Logic Voltage
VccDMI
1.05
0.047
DMI Buffer Voltage
VccIO
1.05
3.799
Core Well I/O buffers
VccASW
1.05
0.803
1.05 V Supply for Intel R Management

Engine and Integrated LAN
VccSPI
3.3
0.01
3.3 V Supply for SPI Controller Logic
VccDSW
3.3
0.003
3.3v supply for Deep S4/S5 well
VccpNAND
1.8
0.19
1.8V power supply for DF_TVS
VccRTC
3.3
6 uA
Battery Voltage
3.3
0.065
Suspend Well I/O Buffer Voltage
V1
For SPI control logi

1
Voltage
V5REF_Sus
Core Well I/O Buffer
+1.8VS
Voltage Rail
V5REF
190mA
VCCIO[25]
+1.8VS
Place Near V33
+3VS
AU20
C198
1U_0402_6.3V6K
V33
1
VCC3_3[7]
1121 LVDS@ ->@
+3VS
+1.05VS_VTT
AP17
VCCIO[16]
+1.5VS
PAD
VCCIO[15]
FDI
C194
1U_0402_6.3V6K
C193
1U_0402_6.3V6K
C192
1U_0402_6.3V6K
C191
1U_0402_6.3V6K
C190
10U_0603_6.3V6M
HVCMOS
H On-Die PLL voltage regulator

enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
+3VS
1121 EDP@->POP
Place Near AM37
AP36
178mA
VCCAPLLEXP
DMI
AN16
NAND / SPI
C483
0.01U_0402_16V7K
@
1 LVDS@ 2
R236
0_0805_5%
VCCIO[28]
VCCIO
+VCCAPLLEXP BJ22
T22 @
C185
10U_0603_6.3V6M
AK36 +VCCA_LVDS
2
PAD
C184
U47
VCCALVDS
1mA
+1.05VS_VTT
AN19
VSSADAC
+3VS
L1
MBK1608221YZF_2P
2
1
Place Near U48
+VCCADAC
Place Near AA23
63mA
VCCADAC
U48
1121 LVDS@ ->@
LVDS
VCC CORE
C182
1U_0402_6.3V6K
C181
1U_0402_6.3V6K
C180
1U_0402_6.3V6K
C179
10U_0603_6.3V6M
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
CRT
1730mA
U16G
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
+1.05VS_VTT
+1.05VS_VTT
C199
1U_0402_6.3V6K
Trace 20mil

enable
,VCCAPLLSATA
VccSus3_3
0.16
VccCLKDMI
1.05
0.02
DMI Clock Buffer Voltage
VccSSC
1.05
0.095
Spread Modulators Power Supply
VccDIFFCLKN
1.05
0.055
Differential Clock Buffers Power Supply
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.06
3.3 / 1.5
VccVRM
0.01
Analog power supply for LVDS (Mobile

Only)
Analog power supply for LVDS (Mobile
Only)
2011/11/22
Compal Secret Data
Issued Date
1.8 / 1.5
High Definition Audio Controller Suspend

Voltage
1.8 V Internal PLL and VRMs (1.8 V for
Desktop)
VccSusHDA
2012/11/22
Deciphered Date
Title
PCH (7/9) PWR
Rev
1.0
Date:
A
Sheet

E
19
of
45
+VCCDSW3_3
PAD
+VCCSUS1 AL24
T25 @
AA24
AA27
AA29
AA31
Near BF47
C213
1U_0402_6.3V6K
AA26
AC26
1
+1.05VS_VCCA_B_DPL
C216
330U_D2_2V_Y
@
C209
22U_0805_6.3V6M
Near BD47
C212
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
1
2
L5
10UH_LB2012T100MR_20%
C217
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C208
22U_0805_6.3V6M
1
+1.05VS_VCCA_A_DPL
VCCIO[14]
DCPSUS[3]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
AC27
AC29
AC31
AD29
AD31
Near AA19
W21
W23
W24
W26
SGA20331E10
330U 2V H1.9
9mohm POLY
W29
W31
W33
Near M6
VCCASW[1]
VCCASW[2]
803mA
VCCIO[34]
1mA
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
V5REF_SUS
DCPSUS[4]
VCCSUS3_3[1]
1mA
VCCASW[15]
V5REF
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]
VCCASW[16]
VCC3_3[4]
1
0.1U_0402_16V7K
N16
+VCCRTCEXT
VCCASW[19]
VCC3_3[2]
VCCASW[20]
DCPRTC
VCCVRM[4]
VCCIO[13]
+1.05VS_VTT
BF47
+1.05VS_VCCA_B_DPL
AF17
AF33
AF34
AG34
+1.05VS_VTT
1 C224
1U_0402_6.3V6K
2
Place
near AG33
VCCVRM[1]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[11]
55mA
VCCIO[2]
VCCIO[3]
AG33
Place
near AF33,
AF34,AG34
2
C226
Near V16
PAD
suppied by internal
1.05V VR Must NC
1
+VCCSST
0.1U_0402_16V7K
V16
+1.05VM_VCCSUS T17
V19
T30 @
VCCIO[10]
VCCIO[4]
95mA
VCCASW[22]
C233
0.1U_0402_16V7K
C232
0.1U_0402_16V7K
1
2
2
1
2
For Deep S3 turn off +V5REF_SUS,+VCCSUS3_3
Near T23
V24
C206
0.1U_0402_16V7K
C203
0.1U_0402_16V7K
Near T24
+VCCSUS3_3
P24
+1.05VS_VTT
+5VREF_SUS
D3
RB751V-40_SOD323-2
T26
R243
100_0402_5%
Near M26
M26
+PCH_V5REF_SUS
AN23 +VCCA_USBSUS
AN24
1
2
C207
0.1U_0402_16V7K
T28
PAD
suppied by internal
1.05V VR Must NC
+VCCSUS3_3
+3VS
+5VS
D4
P34
+PCH_V5REF_RUN
R244
100_0402_5%
+VCCSUS3_3
N22
P20
C214
1U_0603_10V6K
C215
1U_0402_6.3V6K
Near P34
Near N20
P22
N20
+3VS
AA16
1
W16
T34
C218
0.1U_0402_16V7K
2 Place
near
AJ2
C219
0.1U_0402_16V7K
2 Place
near
AA16,W16
C220
0.1U_0402_16V7K
2 Place
near
T34
+1.05VS_VTT
AJ2
AF13
1
AH13
2
AH14
VCCASW[23]
VCCASW[21]
Near AH13,AH14,AF13
C222
1U_0402_6.3V6K
GPIO28
AF14
AK1
+VCCSATAPLL
@ T29
PAD
+1.5VS

enable
,VCCAPLLSATA
AF11
AC16
+1.05VS_VTT
AC17
AD17
Near AC16
1
C227
1U_0402_6.3V6K
T21
V21
T19
VCCRTC
HM77@
10mAVCCSUSHDA
P32
Need +3VALW and 0.1U close PCH

1
C234
0.1U_0402_16V4Z
Near P32
Near A22
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
PCH (8/9) PWR
Rev
1.0
Date:
A
PCH_PWR_EN#
+VCCSUS3_3
A22
2
1
V23
+RTCVCC
C231
1U_0402_6.3V6K
Place
near BJ8
2mA
V_PROC_IO
RTC
C230
0.1U_0402_16V7K
C229
0.1U_0402_16V7K
C228
4.7U_0603_6.3V6K
T24
+1.05VS_VTT
DCPSUS[1]
DCPSUS[2]
CPU
BJ8
+VCCSUS3_3
T23
DCPSST
+1.05VS_VTT
isolation between SSC (AG33)

and DIFFCLKN(AF33,AF34,AG34)
18mil width(DIFFCLKN)
10mil (SSC)
VCCAPLLSATA
+1.05VS_VTT
1 C225
1U_0402_6.3V6K
2
VCCIO[6]
MISC
Place
2 near AF17
VCCADPLLB
75mA
75mA
HDA
1 C223
1U_0402_6.3V6K
VCCADPLLA
SATA
BD47
+1.05VS_VCCA_A_DPL
Near N26
T29
<25,33>
C500
R553
1K_0402_5%
VCCASW[18]
VCCIO[12]
Y49
+1.5VS
PCH_PWR_EN#
VCCASW[17]
VCCIO[5]
2
C221
C204
1U_0402_6.3V6K
T27
0.1U_0402_16V7K
1
2
RB751V-40_SOD323-2
PCI/GPIO/LPC
AA21
+1.05VS_VTT
VCCSUS3_3[7]
65mA
VCCAPLLDMI2
Clock and Miscellaneous
AA19
C499
R552
1K_0402_5%
VCC3_3[5]
VCCSUS3_3[6]
+1.05VS_VTT
L4
10UH_LB2012T100MR_20%
1
2
VCCIO[33]
P28
2
0_0402_5%
VCCIO[32]
P26
AL29
+1.05VS_VTT
DCPSUSBYP
VCCIO[31]
3mA
0.1U_0402_16V7K
1
2
1
R242
BH23
+VCCAPLL_CPY_PCH
T27 @
+3VALW_PCH
VCCIO[30]
VCCDSW3_3
N26
PAD
T38
+3VS_VCC_CLKF33

enable
,VCCAPLLSATA
V12
+PCH_VCCDSW
suppied by internal
1.05V VR must NC
GPIO28
T16
Near T16
T26 @
VCCIO[29]
PAD
+1.05VS_VTT
VCCACLK
Near T38
Not support Deep S4,S5

connect to +3VALW
POWER
U16J
AD49
C202
0.1U_0402_16V7K
1
DS3@
Q8
AP2301GN-HF_SOT23-3
+VCCDSW3_3
1
DS3@
Q68
AP2301GN-HF_SOT23-3
1 0_0603_5%
R241
20K_0402_5%
+VCCACLK
T24 @
S3@
R240 2
C205
0.1U_0402_16V7K
PAD
R288
20K_0402_5%
C200
10U_0603_6.3V6M
C201
1U_0402_6.3V6K
+3VS_VCC_CLKF33
1
1
+5VREF_SUS
+5VALW
20mil
C279
0.1U_0402_16V7K
L3
10UH_LB2012T100MR_20%
1
2
+VCCSUS3_3
JUMP_43X39
J13 @
1
2
1
2
1
VCCDMI = 47mA detal waiting for newest spec
+1.05V analog
internal clock PLL
Can NC
USB
+3VS
+3VALW
VCC3_3 = 178mA detal waiting for newest spec
Sheet

E
20
of
45
U16I
U16H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
HM77@
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
HM77@
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
PCH (9/9) VSS
Rev
1.0
Date:
A
Sheet

E
21
of
45
LCD POWER CIRCUIT

+LCDVDD
1
6 2
R246
10K_0402_5%
C236
680P_0402_50V7K
2
1K_0402_5%
2
1
R247
3
4
+CAM_VCC
W=60mils
1
<16>
<16>
C240
0.1U_0402_16V4Z
R248
100K_0402_5%
2
R525
INVTPWM
2
10K_0402_5%
1
R249
<16>
+3VS
U22 @
2
1
100K_0402_5% OE#
DPST_PWM
2
3
VCC
12/13 Add
<16>
<16>
PCH_TXOUT1+
PCH_TXOUT1-
<16>
<16>
PCH_TXOUT0+
PCH_TXOUT0-
PCH_LCD_DATA
PCH_LCD_CLK
<29>
IN
C471
BKOFF#
+LCDVDD
R489 1
EDP_HPD
R454 1 LVDS@ 2 0_0402_5%

R455 1 LVDS@ 2 0_0402_5%
PCH_TXCLK+_R
PCH_TXCLK-_R
R456 1 LVDS@ 2 0_0402_5%

R457 1 LVDS@ 2 0_0402_5%
PCH_TXOUT2+_R
PCH_TXOUT2-_R
R458 1 LVDS@ 2 0_0402_5%

R459 1 LVDS@ 2 0_0402_5%
PCH_TXOUT1+_R
PCH_TXOUT1-_R
R460 1 LVDS@ 2 0_0402_5%

R461 1 LVDS@ 2 0_0402_5%
PCH_TXOUT0+_R
PCH_TXOUT0-_R
R462 1 LVDS@ 2 0_0402_5%

R463 1 LVDS@ 2 0_0402_5%
PCH_LCD_DATA_R
PCH_LCD_CLK_R
BKOFF#
INVTPWM
2 220P_0402_50V7K
+3VS
+LCDVDD
2 10K_0402_5%
INVTPWM
+LED_VOUT
GND
74AHC1G125GW_SOT353-5
1
R250
PCH_TXOUT2+
PCH_TXOUT2-
PCH_TXCLK+
PCH_TXCLK-
<16>
<16>
<16>
<16>
+3VS
OUT
USB20_P10_R
USB20_N10_R
Camera
+LCDVDD
C239
Q9B
4.7U_0603_6.3V6K
JLVDS1
PCH_ENVDD
LCD/LED PANEL Conn.
Q10
AO3419L_SOT23-3
C238
0.047U_0402_16V7K
DCR 0.04
2
1
<16>
C235
4.7U_0603_6.3V6K
Q9A
+LED_VOUT
B+
L6
FBMA-L11-201209-221LMA30T_0805
2
1
L7
FBMA-L11-201209-221LMA30T_0805
2
1
@
1
1
C237
SM010014520 3000ma
68P_0402_50V8J 220ohm@100mhz
W=60mils
R245
300_0603_5%
W=60mils
+3VS
+3VALW
C247
2
0_0402_5%
0.1U_0402_16V4Z
C248
10U_0603_6.3V6M
W=60mils
C249
0.1U_0402_16V4Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SP010011S00
EDP_AUXN
EDP_AUXP
<4>
<4>
EDP_HPD
<4>
<4>
EDP_TXP0
EDP_TXN0
<4>
<4>
EDP_TXP1
EDP_TXN1
2
G
S
Q11
SSM3K7002FU_SC70-3
EDP@
GND1
GND2
GND3
GND4
GND5
GND6
11/29 Modify.
eDP
EDP_HPD#
31
32
33
34
35
36
STARC_107K30-000001-G2_30P
CONN@
Place closed to JLVDS1
W=60mils
<4>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
R251
100K_0402_5%
EDP@
EDP@ C241 1
EDP@ C242 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCH_LCD_DATA_R
PCH_LCD_CLK_R
EDP@ C243 1
EDP@ C244 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCH_TXOUT1+_R
PCH_TXOUT1-_R
EDP@ C245 1
EDP@ C246 1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PCH_TXOUT2+_R
PCH_TXOUT2-_R
3
D5
Camera
USB20_P10_R
1
2
USB20_N10_R
11/29 Modify D5(ESD request)
L30ESDL5V0C3-2
R252 1
L8
<17>
USB20_P10
<17>
USB20_N10
2
3
2 0_0402_5%
@
USB20_P10_R
USB20_N10_R
WCM2012F2SF-670T04_0805
R253 1
+3VS
2
0_0603_5%
+CAM_VCC
2011/11/22
Deciphered Date
Compal Secret Data
Issued Date
1
R453
2 0_0402_5%
2012/11/22
Title
LVDS&eDP
Document Number
Custom
Date:
A
Sheet
E
22
of
45
Rev
1.0
R255
0_0603_5%
1
2
@
4
L9
WCM-2012-900T_0805
1
F1
+HDMI_5V
3
D6
RB491D-YS_SOT23-3
R254 1
HDMI_CLK+
W=40mils
+HDMI_5V_OUT
+5VS
SM070001310 400ma 90ohm@100mhz DCR 0.3
1.1A_6V_SMD1812P110TF
PCH_DPB_N0
PCH_DPB_P0
C251
C252
2
2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_TX2HDMI_TX2+
<16>
<16>
PCH_DPB_N1
PCH_DPB_P1
C253
C254
2
2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_TX1HDMI_TX1+
<16>
<16>
PCH_DPB_N2
PCH_DPB_P2
C255
C256
2
2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_TX0HDMI_TX0+
PCH_DPB_N3
PCH_DPB_P3
C257
C258
2
2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
HDMI_CLKHDMI_CLK+
<16>
<16>
HDMI_R_CK+
0_0402_5%
2
2
0_0402_5%
HDMI_R_CK-
0_0402_5%
HDMI_R_D0+
@
C250
0.1U_0402_16V4Z
R257 1
HDMI_TX0+
4
L10
WCM-2012-900T_0805
1
<16>
<16>
R256 1
HDMI_CLK-
R258 1
HDMI_TX0-
0_0402_5%
HDMI_R_D0-
0_0402_5%
HDMI_R_D1+
@
R259 1
HDMI_TX1+
4
L11
WCM-2012-900T_0805
1
HDMI_TX1-
R260
0_0402_5%
HDMI_R_D1-
0_0402_5%
HDMI_R_D2+
@
HDMI_TX2+
+3VS
L12
WCM-2012-900T_0805
1
1
2
R263 1
HDMI_TX2-
0_0402_5%
HDMI_R_D2-
R262
1M_0402_5%
PCH_DPB_HPD
HDMI_HPD
C259
220P_0402_50V7K
HDMI_TX2HDMI_TX2+
R264 1
R265 1
2 680_0402_5% HDMI_GND
2 680_0402_5%
HDMI_TX1HDMI_TX1+
R266 1
R267 1
2 680_0402_5%
2 680_0402_5%
HDMI_TX0HDMI_TX0+
R268 1
R270 1
2 680_0402_5%
2 680_0402_5%
HDMI_CLK- R271 1
HDMI_CLK+ R272 1
2 680_0402_5%
2 680_0402_5%
3
Q12A
R269
100K_0402_5%
<16>
R261
+3VS
3/1 Add (ESD request)

+HDMI_5V_OUT
Q12B
+3VS
C492
+3VS
SDVO_SCLK
2 2.2K_0402_5%
SDVO_SDATA
C493
@
0.1U_0402_16V4Z
+3VS
HDMI connector
HDMI_SDATA
HDMI_SCLK
R276
2.2K_0402_5%
HDMI_R_CK-
<16>
SDVO_SDATA
SDVO_SDATA
2
1
SDVO_SCLK
SDVO_SCLK
<16>
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_HPD
+HDMI_5V_OUT
R275
2.2K_0402_5%
HDMI_R_CK+
HDMI_R_D0-
RF request
HDMI_SCLK
HDMI_R_D0+
HDMI_R_D1-
Q13A
3
HDMI_SDATA
Q13B
@
Place closed to JHDMI1
JHDMI1
2 2.2K_0402_5%
R274 1
0.1U_0402_16V4Z
R273 1
D7
RB751V-40_SOD323-2
C260
47P_0402_50V8J
HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+
C261
47P_0402_50V8J
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
HONGL_13-13201904CP_19P
CONN@
DC232001000
11/29 Modify.
Issued Date
Compal Secret Data
2011/11/22
Deciphered Date
2012/11/22
Title
HDMI Conn
Document Number
Custom
Rev
1.0
Date:
A
Sheet
E
23
of
45
W=40mils
+5VS
+R_CRT_VCC
D11
2
@
D10
L30ESDL5V0C3-2
CH491DPT_SOT23-3
C262
0.1U_0402_16V4Z
@
D9
L30ESDL5V0C3-2
+CRT_VCC
F2
1.1A_6V_SMD1812P110TFW=40mils
1
2
CRT Connector
CRB1.0 use 47ohm@100Mhz Bead
PCH_CRT_B
0_0603_5%1
2 L15
CRT_G_1
PCH_CRT_B
0_0603_5%1
2 L17
CRT_B_1
JCRT1
PAD
CRT_G_2
2
1
2 L19
0_0603_5%
+CRT_VCC
1
PCH_CRT_HSYNC R281 2
33_0402_5%
CRT_HSYNC
DC060004W00
D-SUB
DSUB_12
C274
10P_0402_50V8J
@
CRT_VSYNC_2
1
C275
10P_0402_50V8J
2@
16
17
G
G
CONTECK_80435-5K1-152
CONN@
100P_0402_50V8J
CRT_HSYNC_2
1
2 L20
0_0603_5%
CRT_HSYNC_1
JCRT1.5
@ T32
PAD
C272
C276 2
68P_0402_50V8J
74AHCT1G125GW_SOT353-5
DSUB_15
1
PCH_CRT_HSYNC
1 10K_0402_5%
U23
<16>
R280 2
1
2 0.1U_0402_16V4Z
OE#
C273 1
2
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
JCRT1.11
@ T31
CRT_B_2
C271
2.2P_0402_50V8C
CRT_R_2
C270
2.2P_0402_50V8C
C269
2.2P_0402_50V8C
C268
2.2P_0402_50V8C
C267
2.2P_0402_50V8C
C266
2.2P_0402_50V8C
C265
10P_0402_50V8J
C264
10P_0402_50V8J
R279
150_0402_1% @
C263
10P_0402_50V8J
R277
R278
150_0402_1% 150_0402_1%
L14
FBMA-L10-160808-600LMT 0603
1
2
L16
FBMA-L10-160808-600LMT 0603
1
2
L18
FBMA-L10-160808-600LMT 0603
1
2
CRT_R_1
PCH_CRT_G
<16>
PCH_CRT_G
2 L13
0_0603_5%1
<16>
PCH_CRT_R
PCH_CRT_R
<16>
12/30 Modify.
C277
68P_0402_50V8J
+CRT_VCC
+3VS
CRT_VSYNC_1
R283
2.2K_0402_5%
2
74AHCT1G125GW_SOT353-5
<16>
PCH_CRT_DATA
PCH_CRT_DATA
5
HDD Board Conn
<16>
PCH_CRT_CLK
PCH_CRT_CLK
R284
2.2K_0402_5%
2
CRT_VSYNC
+CRT_VCC
U24
5
P
1
PCH_CRT_VSYNC R282 2
33_0402_5%
PCH_CRT_VSYNC
<16>
2 0.1U_0402_16V4Z
OE#
C278 1
DSUB_12
Q15A
3
DSUB_15
Q15B
JHDD1
3
<13>
<13>
C281 1
C282 1
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
<13>
<13>
+5VS
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
+5VS_HDD
+3VS
@ J2
1
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
JUMP_43X79
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
13
14
ACES_85201-1205N
CONN@
SP01000E400
+5VS_HDD
100mils
C488
1000P_0402_50V7K
C487
0.1U_0402_16V4Z
10U_0805_10V4Z
C486
1U_0603_10V6K
C485
+3VS
C502
@
0.1U_0402_16V4Z
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
CRT&HDD Connector
Custom
Rev
1.0
Date:
A
Sheet
E
24
of
45
+3VALW
R285
@
LAN_PWR_EN#
2
R548 1
@
0_0402_5%
2
R549 1
1K_0402_5%
XTALVDDH
AVDDH
AVDDH
2
+3V_LAN
7
56
62
C301
0.1U_0402_16V4Z
C289
0.1U_0402_16V4Z
VDDO
VDDO
VDDO
TRD2_N
TRD2_P
39
45
51
+LAN_AVDDL
36
+LAN_GPHYPLLVDDL
32
+LAN_PCIEPLLVDD
29
AVDDL
AVDDL
AVDDL
TRD1_N
TRD1_P
TRD0_N
TRD0_P
GPHY_PLLVDDL
+LAN_BIASVDDH
+LAN_XTALVDDH
48
42
+LAN_AVDDH
+3V_LAN
49
50
LAN_MIDI3LAN_MIDI3+
47
46
LAN_MIDI2LAN_MIDI2+
43
44
LAN_MIDI1LAN_MIDI1+
41
40
LAN_MIDI0LAN_MIDI0+
60mil
LAN_MIDI3LAN_MIDI3+
<26>
<26>
LAN_MIDI2LAN_MIDI2+
<26>
<26>
LAN_MIDI1LAN_MIDI1+
<26>
<26>
LAN_MIDI0LAN_MIDI0+
<26>
<26>
C302
20mil
C304
C498
0.1U_0402_16V4Z
SCLK_SPD1000LED#
SPD100LED#_SERIALDO
65
LAN_LINK#
2
<27,29>
EC_PME#
+3V_LAN
<15,27>
C303 1
2 0.1U_0402_16V4Z
PLT_RST_BUF#
PCIE_PRX_C_DTX_P3
PCIE_PRX_C_DTX_N3
2 4.7K_0402_5%
@
28
27
33
34
PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
TRAFFICLED#_SERIALDI
GPIO1_LR_OUT
GPIO_0
2 0_0402_5%
R290 1
R292 1
PLT_RST_BUF#
CLK_PCIE_LAN
CLK_PCIE_LAN#
2 C305
2 C308
R289 1
R291 1
PCH_PCIE_WAKE#
<17,27,29,30>
<14>
<14>
1
1
66
2 0_0402_5%
LAN_PME#
2 0_0402_5%
11
31
30
SI_EEDATA
CS#_EECLK
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
R295
R296
R298
R299
1
1
1
1
2
2
2
2
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
CR_DATA0_R
CR_DATA1_R
CR_DATA2_R
CR_DATA3_R
25
24
23
22
52
53
54
55
PREST#
PCIE_REFCLK_P
PCIE_REFCLK_N
SR_DISABLE/XD_DETECT#
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
MS_INS#/XD_CE#
GPIO2_MEDIA_SENSE/XD_RE#
CR_WP#/XD_WP#
CR_LED_CR_BUS_PWR/XD_ALE
CR_CLK/XD_RY_BY#
+3VS
R310 1
2 1K_0402_5%
R311 1
2 4.7K_0402_5%
58
L22
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z
L23
1
2
BLM18AG601SN1D_2P
+LAN_AVDDH
67
+VDDO_CR_R
R286 2
1 0_0402_5%
R287 1
2 0_0603_5%
LAN_ACTIVITY#
<26>
+3V_LAN
0.1U_0402_16V4Z
C307
0.1U_0402_16V4Z
+VDDO_CR
64
63
SPROM_DOUT
SPROM_CLK
CR_DETECT_R
R293
1 0_0402_5%
CR_DETECT
57
CR_WP#_R
R303
1 0_0402_5%
CR_WP#
60
CR_PWR_EN_R
R306
1 0_0402_5%
CR_PWR_EN
21
CR_CLK_R
R307
<EMI> 2 33_0402_5%
26
CR_CMD_R
R308
2 33_0402_5%
WAKE#
SD_DETECT/XD_WE#
<26>
<26>
<26>
<26>
L21
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z
20mil
<26>
C306
.1U_0402_16V7K
.1U_0402_16V7K
+LAN_BIASVDDH
PCIE_PLLVDDL
20mil
+LAN_XTALVDDH
PCIE_PLLVDDL
SO_LINKLED#
37
17
C298
0.1U_0402_16V4Z
VDDC
VDDC
TRD3_N
TRD3_P
C300
0.1U_0402_16V4Z
C299
4.7U_0603_6.3V6K
D
G
R554
1
2
@
10K_0402_5%
PCH_PWR_EN#
BIASVDDH
2 0_0805_5%
3
AO3419L_SOT23-3
Q37
<29>
35
61
+3V_LAN
1
<20,33>
+1.2V_LAN
VDDO_CR
C297
4.7U_0603_6.3V6K
C478
0.1U_0402_16V4Z
20
R02 Modify
C477
0.1U_0402_16V4Z
U25
1/3 Add(Broadcom request)
4.7U_0603_6.3V6K
C296
C295
0.1U_0402_16V4Z
C294
0.1U_0402_16V4Z
C293
0.1U_0402_16V4Z
C292
0.1U_0402_16V4Z
C288
0.1U_0402_16V4Z
+VDDO_CR
1
C291
0.1U_0402_16V4Z
C290
4.7U_0603_6.3V6K
+1.2V_LAN
CR_CMD_XD_CLE
CR_DETECT
<26>
68
59
9
CR_WP#
<26>
CR_PWR_EN
For EMI request
<26>
CR_CLK
CR_CLK
CR_CMD
CR_CMD
C309
<26>
<EMI> 1
<26>
10P_0402_50V8J
VMAIN_PRSNT
+3V_LAN
R312
6
10
4.7K_0402_5%
1
C316
15P_0402_50V8J
GND
GND
<14>
2 LAN_RDAC
1.24K_0402_1%
12
LAN_CLKREQ#
R550
15mil38
1
R315
3LAN_XTALO
C317
15P_0402_50V8J
+3V_LAN
40mil
L24
2
+1.2V_LAN_OUT 1
4.7UH_PG031B-4R7MS_1.1A_20%
13
40mil
+1.2V_LAN
1
C310
0.1U_0402_16V4Z
XTALO
XTALI
EMI Request...2010/07/27
C311
10U_0603_6.3V6M
SM010005500 500ma 600ohm@100mhz DCR 0.38
R02 Modify
GND PLANE
SR_VFB
16
RDAC
CLK_REQ#
BCM57785XA0KMLG_QFN68_8X8
2
SR_VDDP
SR_VDD
15
14
20mil
40mil
L25
1
2
BLM18AG601SN1D_2P
+LAN_PCIEPLLVDD
+3V_LAN
1 0.1U_0402_16V4Z
C312
69
25MHZ_10PF_7V25000014
LOW_PWR
R314
200_0402_1%
2
Y3
1
19
18
LAN_XTALO_R
LAN_XTALI
TEST2
SR_LX
4
LAN_XTALI
LAN_XTALO_R
TEST1
4.7U_0603_6.3V6K
C313
C314
0.1U_0402_16V4Z
+1.2V_LAN
C315
4.7U_0603_6.3V6K
PLACE NEXT P14
10K_0402_5%
20mil
L26
1
2
BLM18AG601SN1D_2P
+LAN_GPHYPLLVDDL
C318
0.1U_0402_16V4Z
+1.2V_LAN
C319
4.7U_0603_6.3V6K
+3V_LAN
On chip
AT24C02
@
C320 1
1
2
R317
4.7K_0402_5%
SPROM_DOUT
(EEDATA)
1
2
R316
4.7K_0402_5%
SPROM_CLK
(EECLK)
1
2
R319
4.7K_0402_5%
R318
4.7K_0402_5%
SPROM_CLK
SPROM_DOUT
2 0.1U_0402_16V4Z
20mil
L27
1
2
BLM18AG601SN1D_2P
+LAN_AVDDL
C321
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
AT24C04BN-SH-T_SO8
SA00004QG00
4
Issued Date
Compal Secret Data
2011/11/22
Deciphered Date
2012/11/22
Title
LAN Boardcom 57785

Size
Document Number
Custom
Rev
1.0
Date:
A
+1.2V_LAN
C322
U26 @
Sheet
E
25
of
45
BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00

TIMAG:S X'FORM_ IH-160 LAN , SP050006F00
LAN Connector
C474,C475 and D14

ME interefer,do not pop!!
TL1
350UH_IH-160
SP050006F00
1
C329
220P_0402_50V7K
RJ45_MIDI0RJ45_MIDI0+
1
1K_0402_5% 1
LAN_ACTIVITY#
LAN_LINK#
C324 68P_0402_50V8J
@
2
1
RJ45_GND
Place close to TCT pin
+3V_LAN
11/30 Modify(EMI Request)
2
R320
1
1K_0402_5%
C496
0.1U_0402_16V4Z
RJ45_MIDI1-
RJ45_MIDI2-
RJ45_MIDI2+
RJ45_MIDI1+
RJ45_MIDI0-
RJ45_MIDI0+
PR4PR4+
PR2PR3PR3+
PR2+
PR1SHLD2
PR1+
14
13
LED-(G)
11
40mil
LED+(G)
SANTA_130452-A
CONN@
DC234005S00
12/21 Modify
EMI Request
2
C331 1
RJ45_GND
2 10P_0402_50V8J
40mil
LANGND
1
JP4
2
1
2
1
RJ45_MIDI3+
LED+(Y)
12
R04 modify for EMI
C495
@
JP3
SHLD1
J3
JUMP_43X39
@
JP2
LSE-200NX3216TRLF_1206-2
1
2
0.1U_0402_16V4Z
LSE-200NX3216TRLF_1206-2
C494
JP1
LSE-200NX3216TRLF_1206-2
0.1U_0402_16V4Z
LSE-200NX3216TRLF_1206-2
+3VS
RJ45_MIDI3-
LAN_LINK#
LAN_LINK#
MCT3
MCT2
MCT1
MCT0
D12
L30ESDL5V0C3-2
@
<25>
LED-(Y)
LANGND
RJ45_GND
R03 Modify
MCT0
2
R325
+3V_LAN
RJ45_MIDI1+
RJ45_MIDI1-
JRJ1
10
LAN_ACTIVITY#
LAN_ACTIVITY#
15
14
13
<25>
MCT4
MX4+
MX4-
MCT1
RJ45_MIDI2RJ45_MIDI2+
TCT4
TD4+
TD4-
18
17
16
68P_0402_50V8J
2
1
@
C330
RJ45_MIDI3+
RJ45_MIDI3-
1
2
L28
100UH_SSC0301101MCF_0.18A_20%
MCT3
MX3+
MX3-
MCT2
@ C332
100P_0402_50V8J
TCT3
TD3+
TD3-
21
20
19
C323
220P_0402_50V7K
MCT2
MX2+
MX2-
MCT3
LAN_MIDI0LAN_MIDI0+
10
11
12
TCT2
TD2+
TD2-
24
23
22
7
8
9
MCT1
MX1+
MX1-
2
R323
75_0603_1%
2
1
R324
75_0603_1%
LAN_MIDI0LAN_MIDI0+
LAN_MIDI1+
LAN_MIDI1-
C325
0.1U_0402_16V4Z
<25>
<25>
LAN_MIDI1+
LAN_MIDI1-
LAN_MIDI2LAN_MIDI2+
4
5
6
TCT1
TD1+
TD1-
2
1
R321
75_0603_1%
2
1
R322
75_0603_1%
1
<25>
<25>
1
2
3
C328
0.1U_0402_16V4Z
LAN_MIDI2LAN_MIDI2+
LAN_MIDI3+
LAN_MIDI3-
C327
0.1U_0402_16V4Z
<25>
<25>
LAN_MIDI3+
LAN_MIDI3-
C326
0.1U_0402_16V4Z
<25>
<25>
D13
L30ESDL5V0C3-2
R04 modify
Card Reader Connector

JREAD1
CR_WP#
CR_DETECT
10
11
12
13
DAT0
DAT1
DAT2
CD/DAT3
WP SW
CD SW
GND SW
GND SW
GND
GND
14
15
<25>
CR_PWR_EN
10P_0402_50V8J
R547
33_0402_5%
2
1
<EMI> @
GND
VIN
VIN
EN
VOUT
VOUT
VOUT
FLG
8
7
6
5
AP2301MPG-13_MSOP8

@
+5VS
+5VS
+5VALW
1
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
Custom
Card Reader
Date:
A
R04 modify
CR_CLK_CONN
C335
0.1U_0402_16V4Z
@
CR_CLK_C
C334
0.1U_0402_16V4Z
C333
0.1U_0402_16V4Z
C489
2
G
Q16
2N7002K_SOT23-3
2/25 Change symbol of Q16 from SB000009080 to

SB00000EN00
SP07000TF00
12/23 Modify(2in1 CARD READER)
(
2.85mm)
<EMI> 1
40mil
U27
1
2
3
4
R327
300_0603_5%
T-SOL_156-1000302601_11P
CONN@
+SDPWR_MMCPWR
C338
0.1U_0402_16V4Z
CR_WP#
CR_DETECT
8
9
1
2
2
@
R326
0_0805_5%
C337
0.1U_0402_16V4Z
<25>
<25>
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
C336
4.7U_0603_6.3V6K
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
+3VALW
EPAD
<25>
<25>
<25>
<25>
CR_CLK_CONN
1 0_0402_5%
C339
0.1U_0402_16V4Z
R559
+VDDO_CR
CMD
VSS
VDD
CLK
VSS
+SDPWR_MMCPWR
<25> CR_CLK
3
4
5
6
7
CR_CMD
CR_CMD
<25>
Sheet

E
26
of
45
Rev
1.0
MINI CARD(Wireless LAN)
60mil
+3VS
+3VS_WLAN
+3VS_WLAN
+1.5VS
@ J4
+3VS_WLAN
2
1
JUMP_43X79
1
R333
1
R545
+3VALW
2
PCH_PCIE_WAKE#_R
4.7K_0402_5%
AC@ 2
DISASSOCIATE#
4.7K_0402_5%
@ J5
C342
4.7U_0603_6.3V6K
2
0.1U_0402_16V4Z
<29>
<15,25>
WLAN_PME#
<25,29>
R331
PCH_PCIE_WAKE#
R332
0_0402_5%
MINI1_CLKREQ#
<14>
<14>
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
<14>
<14>
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
1
RB751V-40_SOD323-2
WLAN&BT Combo module circuits

BT on
module
Enable
BT_ON#
<14>
<14>
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2
+3VS_WLAN
L
<29>
<29>
R340 1
R341 1
E51TXD_P80DATA
E51RXD_P80CLK
2 0_0402_5% E51TXD_P80DATA_R
2 0_0402_5% E51RXD_P80CLK_R
R541
1K_0402_5%
BT@
<29>
2
G
BT_ON#
C346
0.1U_0402_16V4Z
+1.5VS +3VS_WLAN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
WL_OFF#
PLT_RST_BUF#
WL_OFF# <29>
PLT_RST_BUF# <17,25,29,30>
MINI1_SMBCLK R337 1
MINI1_SMBDATA R338 1
USB20_N8
USB20_P8
@
@
2 0_0402_5%
2 0_0402_5%
PCH_SMBCLK <14>
PCH_SMBDATA <14>
<17>
<17>
2
DISASSOCIATE#
DISASSOCIATE#
<29>
54
SP07000QC00
BT_CTRL
BT_CTRL
PLAST_SSM010-52-B-K
CONN@
R342
100K_0402_5%
C345
0.1U_0402_16V4Z
JMINI1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
BT_CTRL
BT on
module
Disable
4.7U_0603_6.3V6K
0_0402_5%
D31
<14>
C344
Mini Card Power Rating
PCH_PCIE_WAKE#_R
0_0402_5%
R330
EC_PME#
C343
0.1U_0402_16V4Z
JUMP_43X79
C341
11/29 Modify
+3VS_WLAN
1
R349
Q38
2N7002K_SOT23-3
BT@
2
E51RXD_P80CLK_R
4.7K_0402_5%
+3VALW
+3VS_WLAN
Q17
AO3419L_SOT23-3
D
3
AC@
AC@
2 3VSWLAN_GATE_R
1
100K_0402_5%
R335
AC@
3VSWLAN_GATE
1K_0402_5%
C347
0.1U_0402_16V7K 3VSWLAN_R
AC@
Q18
2N7002K_SOT23-3
AC@
2
G
WLAN_ON
<29>
R339
1K_0402_5%
1
2
AC@
C348
0.1U_0402_16V7K
AC@
R336
470_0603_5%
@
1
R334
+3VALW
40mil(1A)
2
G
Q19
2N7002K_SOT23-3
3VSWLAN_GATE
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
Document Number
Custom
MINI CARD (WLAN)
Date:
A
Sheet
E
27
of
45
Rev
1.0
IO Board

1
<17>
<17>
USB20_N3
USB20_P3
R555
0_0402_5%
2
@
L32
USB20_N3_2
USB20_P3_2
JIO1
USB2.0
SM070000K00
USB2.0
R556
0_0402_5%
<17>
<17>
<17>
USB20_P2
USB20_N2
R557
0_0402_5%
2
@
L33
USB_OC1#
+5VALW
USB20_P2_2
USB20_N2_2
<29>
USB_ON#
<31>
<31>
<31>
<31>
<31>
HP_RIGHT
HP_LEFT
COM_MIC
HP_PLUG#
INT_MIC_R
+5VS
W CM-2012-900T_4P
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
USB20_P3_2
USB20_N3_2
USB20_P2_2
USB20_N2_2
W CM-2012-900T_4P
HP_RIGHT
HP_LEFT
COM_MIC
HP_PLUG#
INT_MIC_R
SM070000K00
R558
0_0402_5%
+3VALW
G2
G1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CONN@
ACES_85201-2005N
SP010011U00
C497
0.1U_0402_16V4Z
+5VALW
USB3.0
3/29 Add (ESD request) +5VALW

1
C351
0.01U_0402_16V7K
1
2
C501
USB_ON#
+USB3_VCCA
W=60mils
U28
1
2
3
4
0.1U_0402_16V4Z
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
D15
10 9
U3RXDN2
U3RXDP2
2 2
9 8
U3RXDP2
U3TXDN2
4 4
7 7
U3TXDN2
5 5
U3TXDP2
6 6
USB_OC0#
<17>
+USB3_VCCA
C352
W=100mils
0.1U_0402_16V4Z
+
<17>
U3TXDP2
USB20_N1
USB20_N1
R348
L31
3
3
3 3
U2DN1_L
0_0402_5%
C353
150U 6.3V_M
1
2
@
L05ESDL5V0NA-4 SLP2510P8
<17>
SM070000S80 WCM2012F2SF-670T04 67ohm

<17>
PCH_USB3_TX2_P
<17>
PCH_USB3_TX2_N
USB3@
2
1
PCH_USB3_TX2_P_C
C349
0.1U_0402_16V7K
USB3@
2
1
PCH_USB3_TX2_N_C
C350
0.1U_0402_16V7K
R343 1
L29
3
2
3
2
<17>
PCH_USB3_RX2_P
USB3@
4
4
U3TXDP2
U3TXDN2
2 0_0402_5%
R346 1
2 0_0402_5%
<17>
PCH_USB3_RX2_N
L30
PCH_USB3_RX2_N
U3RXDN2
U3RXDP2
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
GND
GND
GND
GND
10
11
12
13
For USB2.0 ESD request

D16
USB3@
U2DP1_L
JUSB1
1
2
3
4
5
6
7
8
9
DC23300AI00
2
3
U2DN1_L
U2DP1_L
LOTES_AUSB0015-P001A
CONN@
R345 1
PCH_USB3_RX2_P
USB3.0 Conn.
U3TXDN2
U3TXDP2
W CM-2012-900T_0805
1
2
@
R351
0_0402_5%
USB20_P1
W CM2012F2SF-670T04_0805
SM070000S80 WCM2012F2SF-670T04 67ohm
SM070001310 WCM2012F2SF-900T04 90ohm
2 0_0402_5%
USB20_P1
C354
470P_0402_50V7K
1 1
G547I2P81U_MSOP8
For ESD request

U3RXDN2
R344
0_0402_5%
U3RXDP2
U3RXDN2
U2DP1_L
I/O1
I/O4
REF1 REF2
I/O2
I/O3
6
5
4
+USB3_VCCA
4
U2DN1_L
AZC099-04S_SOT23
W CM2012F2SF-670T04_0805
R347 1
2 0_0402_5%
Compal Secret Data
2011/11/22
Issued Date
Deciphered Date
2012/11/22
Title
IO Board & USB3.0

Document Number
Size
Custom
Rev
1.0
Date:
Sheet
E
28
of
45
+3VALW_EC
R372
2 2.2K_0402_5%
EC_SMB_DA1
R368
2 2.2K_0402_5%
EC_SMB_CK1
<17>
<17,25,27,30>
+3VALW
CLK_PCI_LPC
PLT_RST_BUF#
<18>
<27>
R369
1
2
3
4
5
7
8
10
CLK_PCI_LPC
PLT_RST_BUF#
EC_RST#
EC_SCI#
WLAN_ON
12
13
37
20
38
+3VS
@
2
2 2.2K_0402_5%
C475
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
SUSWARN#
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
EC_KBRST#
EC_SMB_CK2
180P_0402_50V8J
R375
2 2.2K_0402_5%
EC_SMB_DA2
12/22 Add(ESD request)

1
R376
2 10K_0402_5%
1
C368
2
EC_SCI#
2 0.01U_0402_16V7K
PLT_RST_BUF#
<30>
ESD request
X1
32.768KHZ_12.5PF_9H03200019
1 EC_XCLK0
EC_XCLK1 2
@
1
@
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
C370
15P_0402_50V8J
C371
15P_0402_50V8J
<30>
1/11 Add "ACPRESENT" signal. (follow Q5LJ1)

EC_SPOK
KSO[0..15]
KSO[0..15]
<35,36>
<35,36>
<14>
<14>
<35>
KSI[0..7]
KSI[0..7]
EC_SPOK
<15> PM_SLP_S3#
<15> PM_SLP_S5#
<18> EC_SMI#
<15> SUSWARN#
<15> SUS_PWR_DN_ACK
<15> ACPRESENT
R542 1
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_DPWROK
EC_SPOK_R
FAN_SPEED1
EC_PME#
E51TXD_P80DATA
E51RXD_P80CLK
9012_PCH_PWROK
PWR_SUSP_LED#
WL_OFF#
2 0_0402_5%
<32>
<25,27>
<27>
<27>
FAN_SPEED1
EC_PME#
E51TXD_P80DATA
E51RXD_P80CLK
<30>
<27>
PWR_SUSP_LED#
WL_OFF#
AD Input
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
AD_BID0
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
R392
8.2K_0402_5%
21
23
26
27
DISASSOCIATE#
BEEP#
63
64
65
66
75
76
BATT_TEMP
DISASSOCIATE#
BEEP# <31>
BT_ON#
BT_ON#
GPIO
Bus
GPIO
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PW R_LED#/GPIO54
BATT_LOW _LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APW ROK/GPXIOA10
SA_PGOOD/GPXIOA11
GPI
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW #/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
AGND/AGND
XCLKI/GPIO5D
XCLKO/GPIO5E
C374
0.1U_0402_16V4Z
ADP_I
AD_BID0
AD_PID0
ENBKL
ADP_I
ENBKL
EC_DPWROK
68
70
71
72
SUSACK#
EN_DFAN1
WLAN_PME#
LAN_PWR_EN#
83
84
85
86
87
88
EC_MUTE#
USB_ON#
SLP_SUS#
EAPD
TP_CLK
TP_DATA
1
@
EC_MUTE#
R366
97
98
99
109
EC_RST_GATE
HDA_SDO
VCIN0_PH_R
2 10K_0402_5%
R371
0_0402_5%
2
1
VR_HOT
H_PROCHOT#
<5,35>
Q20B
Latest design guide suggest change to

74LVC1G06.
SUSACK# <15>
EN_DFAN1 <32>
WLAN_PME# <27>
LAN_PWR_EN# <25>
EC_RST_GATE
HDA_SDO <13>
H_PROCHOT#_EC
H_PROCHOT#_EC
+3VLP
2
R374
D19
2
<6>
EC_ACIN
1
200K_0402_5%
ACIN
<15,33,36>
RB751V-40_SOD323-2
2
1 100P_0402_50V8J
C369
119
120
126
128
KB930&9012 Co-Layout Item

1
+EC_VCC
V18R
73
74
89
90
91
92
93
95
121
127
FSTCHG
BATT_AMB_LED#
PWR_LED#
BATT_BLUE_LED#
SYSON
VR_ON
PM_SLP_S4#
100
101
102
103
104
105
106
107
108
PCH_RSMRST#
EC_LID_OUT#
VCIN1_PROCHOT_R
H_PROCHOT#_EC
GPXIOA07
BKOFF#
PBTN_OUT#
PCH_PWR_EN
SA_PGOOD
110
112
114
115
116
117
118
EC_ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
124
+V18R
FSTCHG <36>
BATT_AMB_LED#
<30>
PWR_LED# <30>
BATT_BLUE_LED# <30>
SYSON <33,38>
VR_ON <41>
PM_SLP_S4# <15>
R381
ENBKL 1
2 100K_0402_5%
H_PECI
43_0402_1%
<5,18>
Pin74(KB930),Pin118(KB9012) are with different PECI pin location,

so HW must co-layout for it.
Please make sure which EC pin will be connected to PECI circuit.
PCH_RSMRST# <15>
EC_LID_OUT# <18>
11/15 Power modify

BKOFF# <22>
PBTN_OUT# <15>
PCH_PWR_EN <33>
SA_PGOOD <39>
EC_ON <37>
ON/OFF <30>
LID_SW# <30>
SUSP# <33,36,38,39,40>
+3VALW_EC
9012_PCH_PWROK 2
R382
GPXIOA07
R384
R385
10K_0402_5%
@
R386
10K_0402_5%
@
PCH_PWROK
0_0402_5%
<15>
MAINPWON
0_0402_5%
<35,37> 3
Pin104 This co-layouted circuit is for power fail function of

KB930 and KB9012.At KB930, PCH_PWROK will be connected to pin 104.
At KB9012,PCH_PWROK will be connected to pin 32,
and VCOUT0_PH will be connected to pin 104.
9012_PECI
R524
9012_PECI
KB9012QF-A3_LQFP128_14X14
+3VLP
0_0402_5%
Pin 111 is a power source for HW operation of KB9012.

So, power plan will be different between KB930 and KB9012.
VCIN0_PH_R
R387 1
2 0_0402_5%
VCIN1_PROCHOT_R
R391 1
2 0_0402_5%
VCIN0_PH
<35>
VCIN1_PROCHOT
C372
4.7U_0603_6.3V6K
<35>
Near EC pin for power noise.
20mil
L35
1
ECAGND 2
FBMA-L11-160808-800LMT_0603
SA_PGOOD
ADP_I
2
C385
100P_0402_50V8J
ON/OFF
2
C409
100P_0402_50V8J
C376
0.1U_0402_16V4Z
@
C410
100P_0402_50V8J
@
EC_SMB_DA1
EC_SMB_CK1
+EC_VCC
1
4
Y
A
AD_PID0
4.7K_0402_5%
EC_MUTE# <31>
USB_ON# <28>
SLP_SUS# <15>
EAPD <31>
TP_CLK <30>
TP_DATA <30>
U32
2
<16>
SPOK
<35,36>
PCH_DPWROK
<15>
C421
100P_0402_50V8J
C423
100P_0402_50V8J
<35,37>
R364
C375
0.1U_0402_16V4Z
@
Analog Board ID definition,

Please see page 3.
TP_DATA
<41>
1
R393
100K_0402_5%
I57@
Ra
Project ID
4.7K_0402_5%
<27>
+3VALW
R395
100K_0402_5%
@
1 100P_0402_50V8J ECAGND
1
+3VALW
<27>
2
+3VALW
R363
BATT_TEMP <35>
Rb
TP_CLK
R379
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PW M/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PW ROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
2
20P_0402_50V8
<30>
Q20A
<35>
C367 2
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
SPI Flash ROM
C373
SMB_ALERT#_R
SPI Device Interface
69
Ra
122
123
EC_XCLK1
2
EC_XCLK0
0_0402_5%
1
100K_0402_5%
1
R388
2
R390
SUSCLK
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
CPU1.5V_S3_GATE/GPXIOA00
W OL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00
GND/GND
GND/GND
GND/GND
GND/GND
GND0
R389
100K_0402_5%
<15>
+3VS
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
PS2 Interface
11
24
35
94
113
Board ID
ECAGND
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
DA Output
2 100K_0402_5%
+3VS
SMB_ALERT#
<35>
+3VALW
Analog Board ID definition,

Please see page 3.
<14>
PWM Output
2 100K_0402_5% EC_PME#
PU at LAN side
R373
EC_SCI#
WLAN_ON
GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
C365
0.1U_0402_16V4Z
<18> GATEA20
<18> EC_KBRST#
<13,30> SERIRQ
<13,30> LPC_FRAME#
<13,30> LPC_AD3
<13,30> LPC_AD2
<13,30> LPC_AD1
<13,30> LPC_AD0
R360
0.1U_0402_16V4Z
LID_SW#
+EC_VCC
U30
ECAGND
+3VALW
+3VS
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
C366 2
EC_RST#
1/10 Add
1 47K_0402_5%
2
0_0603_5%
EC_VDD/AVCC
R365 2
C364
1000P_0402_50V7K
2
1
R362
+3VALW_EC
+3VLP
C363
1000P_0402_50V7K
1
CLK_PCI_LPC
33_0402_5%
C362
0.1U_0402_16V4Z
+3VALW_EC
1
1
C361
0.1U_0402_16V4Z
2
R361
C360
0.1U_0402_16V4Z
C358
22P_0402_50V8J
2
1
@
2
0_0603_5%
C359
0.1U_0402_16V4Z
1
R359
+EC_VCCA
L34
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA
2
1
67
+3VALW
9
22
33
96
111
125
R394
0_0402_5%
CP3@
Rb
1
R544
C377
0.1U_0402_16V4Z
@
0_0402_5%
Issued Date
Compal Secret Data
2
DS3@
2011/11/22
2012/11/22
Deciphered Date
Title
EC ENE-KB9012
Document Number
Custom
Date:
A
Sheet
E
29
of
45
Rev
1.0
JKB1
<29>
<29>
JTPM2
CLKRUN#
PLT_RST_BUF#
<15> CLKRUN#
<17,25,27,29> PLT_RST_BUF#
C381 1
100P_0402_50V8J
KSO14
C382 1
100P_0402_50V8J
KSO13
C383 1
100P_0402_50V8J
KSO12
C384 1
100P_0402_50V8J
+3VALW
+3VS
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
LPC_AD3
LPC_AD2
CLK_PCI_TPM_R_2
LPC_FRAME#
LPC_AD1
LPC_AD0
LPC_PD#
SERIRQ
C386 1
100P_0402_50V8J
KSO11
C387 1
100P_0402_50V8J
KSO10
C388 1
100P_0402_50V8J
KSI1
C389 1
100P_0402_50V8J
CLK_PCI_TPM
0_0402_5%
CLK_PCI_TPM
<17>
+3VS
<13,29>
R540
BTB@
10K_0402_5%
LPC_PD#
@ R546
33_0402_5%
2
1
CLK_PCI_TPM_R_2
+3VS
TP Conn.
LED Board
R543
100P_0402_50V8J
C393 1
100P_0402_50V8J
KSI3
C394 1
100P_0402_50V8J
KSO5
C395 1
100P_0402_50V8J
KSO8
C396 1
100P_0402_50V8J
KSO4
C397 1
100P_0402_50V8J
KSO0
C400 1
100P_0402_50V8J
KSO3
C401 1
100P_0402_50V8J
KSI5
C398 1
100P_0402_50V8J
KSI4
C399 1
100P_0402_50V8J
10K_0402_5%
TP_CLK
TP_DATA
<29>
<29>
TP_DATA
TP_CLK
+3VS
D21
C402 1
100P_0402_50V8J
KSO2
C403 1
100P_0402_50V8J
KSI7
C404 1
100P_0402_50V8J
KSO1
C405 1
100P_0402_50V8J
+3VLP
+3VS
C408
100P_0402_50V8J
KSI6
JTP1
<29> SMB_ALERT#_R
<11,12,14> D_CK_SCLK
<11,12,14> D_CK_SDATA
1
C407
100P_0402_50V8J
1
2
3
4
5
6
7
8
9
10
Lid
Switch(Hall
Effect Switch)
51_0402_5%
R551
BAV70W _SOT323-3
+3VALW
R526
47K_0402_5%
1
3
SW 4
EVQPLMA15_4P
SP010014M10
01/12 Change to ACES_51524-0060N-001 .
+3VS
ON/OFFBTN#
<29>
ON/OFF
D29
51_0402_5%
R528
@
<29>
LID_SW # 2
LID_SW #
RB751V-40_SOD323-2
C472
0.1U_0402_16V4Z
AH180W G-7_SC59-3
LED1
HT-191NB5-A168_BLUE
For power button ESD request

D30
C473
10P_0402_50V8J
U39
OUTPUT
ON/OFFBTN#
7
8
ACES_51524-0060N-001
CONN@
(BLUE)
+3VALW
D22
1
2
3
4
5 G1
6 G2
AZ5125-02S.R7G_SOT23-3
6
5
1
2
3
4
5
6
PWR_LED#
PWR_SUSP_LED#
BATT_BLUE_LED#
BATT_AMB_LED#
PW R_LED#
PW R_SUSP_LED#
BATT_BLUE_LED#
BATT_AMB_LED#
C406
0.1U_0402_16V4Z
2
R409
100K_0402_5%
JLED1
<29,30>
<29>
<29>
<29>
ACES_87151-0807G
CONN@
Power LED
ON/OFF BTN
+3VALW
1
2
3
4
5
6
7
8
GND
GND
C391 1
KSO6
VDD
KSO7
100P_0402_50V8J
100P_0402_50V8J
C392 1
C390 1
KSO9
G
G
SERIRQ
2
BTB@
GND1
GND2
KSI2
R145
LPC_FRAME# <13,29>
LPC_AD1 <13,29>
LPC_AD0 <13,29>
@ C481
22P_0402_50V8J
2
1
12/30 Modify.
<13,29>
<13,29>
KSI0
SP01000RY00
LPC_AD3
LPC_AD2
FOX_NQT510166-LOAO-7F
ACES_85208-24071
CONN@
CONN@
1
3
5
7
9
11
13
15
KSO[0..15]
GND
25
26
KSI[0..7]
KSO[0..15]
KSO15
TPM
KB KSI[0..7]
Conn.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
KSI0
KSI1
KSI2
KSO0
KSO1
KSO2
KSI3
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSI4
KSO9
KSI5
KSI6
KSO10
KSO11
KSI7
KSO12
KSO13
KSO14
KSO15
2
1
PW R_LED#
12/22 Modify.
PW R_LED#
<29,30>
10mil
L30ESD24VC3-2_SOT23-3
Compal Secret Data
2011/11/22
Issued Date
Deciphered Date
2012/11/22
Title
TP/IO Port/ KB CONN/TPM

Size
Document Number
Custom
Date:
Rev
1.0

Sheet

E
30
of
45
R411 1
R412 1
40mil
2 0_0603_5%
2 0_0603_5%
4.75V
JUMP_43X39
@
SPK_R+
SPK_R-
SPKR+
SPKR-
Int. Speaker Conn.
40mil
D24
AZ5125-02S.R7G_SOT23-3
2
2
BEEP#
BEEP#_R
<13>
PCH_SPKR
1
C413
100P_0402_50V8J
R415
4.7K_0402_5%
SPKL+
SPKL-
R416 1
R417 1
2 0_0603_5%
2 0_0603_5%
1
2
3
4
G1
G2
5
6
ACES_88266-04001
CONN@
40mil
SPK_L+
SPK_L-
R414
47K_0402_5%
1
2
3
4
SPK_L+
SPK_LSPK_R+
SPK_R-
C412 need to close U34.12

2
(output = 300 mA)
JSPK1
MONO_IN
1U_0402_6.3V6K
C412
R413
47K_0402_5%
<29>
C411
0.1U_0402_16V4Z
+VDDA
J6
60mil
1/4 Modify SPK Pin define
+5VS
D25
AZ5125-02S.R7G_SOT23-3
SM010014520 3000ma 220ohm@100mhz DCR 0.04
+PVDD_HDA
40mil
HD Audio Codec
Place near Pin46
20mil
1
C422
Combo MIC
<28>
COM_MIC
COM_MIC
1 COM_MIC_R
1K_0402_5%
R420
MIC2_C_L
4.7U_0603_6.3V6K
2
MIC2_C_R
4.7U_0603_6.3V6K
C425 1
16
17
23
24
C463
1000P_0402_50V7K
21
External MIC
22
35
Combo MIC
2
36
29
10mil
30
Internal MIC
External MIC
68mA 600mA
10mil31
+INTMIC_VREFO
10mil
35mA
SPK_OUT_L+
40
SPKL+
MIC2_R
SPK_OUT_L-
LINE1_L
SPK_OUT_R+
LINE1_R
SPK_OUT_RMIC1_L
HPOUT_L
MIC1_R
HPOUT_R
CBN
CBP
SDATA_OUT
MIC2_VREFO
SYNC
RESET#
MIC1_VREFO_R
BCLK
41
SPKL-
45
SPKR+
44
SPKR-
32
HP_LEFT
33
HP_RIGHT
HP_PLUG#
28
R428 2
LDD_CAP
GPIO1/DMIC_CLK
JDREF
PD#
Place near
codec
2
2
R429
R430
HP_PLUG#
MIC2JD
1
1
C432
2 2.2U_0603_6.3V6K
39.2K_0402_1%
20K_0402_1%
<29>
CPVEE
SENSE_A
SENSE_B
EAPD
R431
34
10mil13
18
47
2
0_0402_5%
48
7
49
J7
JUMP_43X39
@ 1
J8
JUMP_43X39
@ 1
J9
JUMP_43X39
@ 1
GND
<28>
HDA_SDIN0
33_0402_5%
HDA_SDOUT_AUDIO
10
11
HDA_SYNC_AUDIO
HDA_RST_AUDIO#
<13>
<13>
<13>
HDA_BITCLK_AUDIO
CPVEE
PCBEEP
SENSE A
SENSE B
EAPD
MONO_OUT
AVSS2
VREF
R421
<13>
12
AVSS1
PVSS2
PVSS1
GND
EC_MUTE#
+MIC2_VREFO
3
reseve for EMI
2 C430
+3VS
22P_0402_50V8J
MIC2JD
HDA_RST_AUDIO#
<29>
C429
@
0.1U_0402_16V7K
MONO_IN
R425
22K_0402_5%
R424
4.7K_0402_5%
@
For EMI
2
0_0402_5%
<13>
Q23
BSS138_NL_SOT23-3 S
2
G
MIC2JD_R
C428
10U_0603_6.3V6M
R423
2.2K_0402_5%
COM_MIC
R426
22K_0402_5%
20
37
27
CODEC_VREF
10mil
SPDIFO
DVSS
2
1
@
0_0402_5%
1 281@
EAPD
HDA_RST_AUDIO#
26
43
42
C433 1
2 0.1U_0402_16V4Z
C434 1
2 2.2U_0603_6.3V6K
C435 1
@
2 10U_0603_6.3V6M
Place next pin27
ALC271X-VB6-CG_QFN48_6X6
DGND
J10
JUMP_43X39
2
@ 1
J11
JUMP_43X39
1 R422
GPIO0/DMIC_DATA
1 20K_0402_1% JDREF 19
<28>
<28>
HP_RIGHT
MIC1_VREFO_L
Place near pin28
<28>
C464
220P_0402_50V7K
HP_LEFT
HDA_SDIN0_AUDIO
10U_0603_6.3V6M
INT_MIC_R
MIC2_L
R427
C431 1
INT_MIC_R
DVDD
DVDD_IO
46
39
38
25
LINE2_R
SDATA_IN
C427
2.2U_0603_6.3V6K
+MIC2_VREFO
LINE2_L
PVDD2
15
PVDD1
C426 1
14
AVDD2
C462 1
AVDD1
1
INT_MIC
1K_0402_5%
Place near Pin1, 9

U34
1U_0603_10V6K
2
LINE2_C_L
1U_0603_10V6K
2
LINE2_C_R
C461 1
2
R464
15mil
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
INT_MIC_R
Place near Pin25, 38
Internal MIC
C420
0.1U_0402_16V4Z
C424
C418
C419
10U_0805_10V4Z
C417
R465
10K_0402_5%
+3VS
20mil
0.1U_0402_16V4Z
2
L38 1
BLM18AG121SN1D_2P
+VDDA
L37 1
2
BLM18AG121SN1D_2P
10U_0603_6.3V6M
+3VS_DVDD
+AVDD_HDA
Place near Pin39

SM010030010 200ma 120ohm@100mhz DCR 0.2
+INTMIC_VREFO
SM010030010 200ma 120ohm@100mhz DCR 0.2
C416
C415
C414
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L36 2
1
FBMA-L11-201209-221LMA30T_0805
+VDDA
2
@ 1
J12
JUMP_43X39
@ 1
GNDA
GND
GNDA
Issued Date
Compal Secret Data
2011/06/24
2012/07/12
Deciphered Date
Title
HD Audio Codec ALC271X
Document Number
Size
Custom
Rev
1.0
Date:
A
Sheet
E
31
of
45
FAN1 Conn
+5VS
H3
H_2P5
H4
H_2P5
H5
H_2P5
H6
H_2P5
D27
1SS355_SOD323-2
H2
H_2P5
H7
H_2P5
H8
H_2P5
H9
H_2P5
H10
H_2P5
H11
H_2P5
+3VS
H12
H_3P8
H13
H_3P8
H14
H_3P8
H15
H_3P8
4
5
CPU support plate
GND
GND
ACES_85204-0300N
CONN@
H16
H_3P6
H17
H_3P0N
C439
1000P_0402_50V7K
1
2
3
1
2
JFAN1
1
2
3
+VCC_FAN1
FAN_SPEED1
FAN_SPEED1
1
C438
1000P_0402_50V7K
1
2
R433
10K_0402_5%
H18
H_3P2X3P5N
H19
H_3P2X3P7N
2/3 Modify.
SP02000JR00
12/1 Add
+5VS
<29>
EN_DFAN1
2
R432
1
2
3
4
1
EN
VIN
VOUT
VSET
GND
GND
GND
GND
8
7
6
5
APL5607KI-TRG_SO8
C470
0.1U_0402_16V4Z
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FD3
FD4
@
FIDUCIAL_C40M80
FIDUCIAL_C40M80
Compal Secret Data
Issued Date
FD2
U33
+VCC_FAN1
1
300_0402_5%
FD1
C436
2 10U_0805_10V4Z
<29>
C437
10U_0805_10V4Z
1
2
D28
BAS16_SOT23-3
2
40mil
2011/06/24
Deciphered Date
2012/07/12
Title
Custom
FAN & Screw Hole

Rev
1.0
Date:
Sheet
32
of
45
+5VALW TO +5VS
+3VALW to +3VALW_PCH(PCH AUX Power)
+5VS
U35
AO4478L_SO8
C447
0.1U_0603_25V7K
R435
100K_0402_5%
<38,39,40>
SUSP
SUSP
<29,36,38,39,40>
SUSP#
SUSP
Q24A
2
G
Q35
2N7002K_SOT23-3
R439
10K_0402_5%
3
Q24B
+5VS_R
2
1
R630
0_0603_5%
5VS_GATE
SUSP
+3VALW_PCH
R434
470_0603_5%
10mil
R436
20K_0402_1%
1 C443
+VSB
+3VALW
C445
4.7U_0603_6.3V6K
1U_0603_10V6K
+5VALW
20mil
1
2
3
C442
4.7U_0603_10V6K
20mil
C441
4.7U_0603_10V6K
C440
4.7U_0603_10V6K
8
7
6
5
+5VALW
+5VALW
+3VALW TO +3VS
+3VALW
R440
100K_0402_5%
@
+3VS
10mil
1
3
C453
0.1U_0603_25V7K
R444
100K_0402_5%
+1.5VS
10mil
1
3
R448
510K_0402_5%
2
D
2
G
1
1
2
S
R452
470_0603_5%
+1.5V_R
+1.8VS_R
2
SUSP
G
Q32
2N7002K_SOT23-3
2 SUSP
G
Q33
2N7002K_SOT23-3
@S
+1.5V
1
1
1
3
SUSP
R451
470_0603_5%
+1.05VS_VTT_R
2
SUSP
G
Q31
2N7002K_SOT23-3
+1.8VS
R450
470_0603_5%
+0.75VS_R
Q28
2N7002K_SOT23-3
1
2
R449
22_0603_5%
C460
0.1U_0603_25V7K
+1.05VS_VTT
Q30
2N7002K_SOT23-3
@
+0.75VS
ACIN
ACIN
2
G
<15,29,36>
PCH_PWR_EN
R446
100K_0402_5%
+1.5VS_R
Q29A
1.5VS_GATE
Q29B
<29>
R445
470_0603_5%
PCH_PWR_EN#
PCH_PWR_EN#
R447
200K_0402_5%
SUSP
1
2
3
C458
1U_0402_6.3V6K
+VSB
<20,25>
8
7
6
5
C457
4.7U_0603_6.3V6K
20mil
3
C456
0.1U_0402_16V4Z
C455
0.1U_0402_16V4Z
C454
4.7U_0603_6.3V6K
C459
4.7U_0603_6.3V6K
1
1
Q27A
U38
AO4478L_SO8
+5VALW
+1.5V
Q36
2N7002K_SOT23-3
@
SUSP
+1.5V to +1.5VS
2
G
Q27B
SYSON
SYSON
R443
100K_0402_5%
2
1
<29,38>
+3VS_R
3VS_GATE
SUSP
SYSON#
R441
470_0603_5%
+VSB
R442
47K_0402_5%
20mil
6 1
1
2
3
C452
1U_0402_6.3V6K
8
7
6
5
C451
4.7U_0603_6.3V6K
C450
4.7U_0603_6.3V6K
C449
4.7U_0603_6.3V6K
U37
AO4478L_SO8
2
SYSON#
G
Q34
2N7002K_SOT23-3
Issued Date
Compal Secret Data
2011/11/22
2012/11/22
Deciphered Date
Title
Document Number
Size
Custom
DC Interface
Date:
A
Sheet
E
33
of
45
Rev
1.0
PL1
1
PC6
1000P_0402_50V7K
JUMP_43X118
PJ2
+3VALW
@ PC2
1000P_0402_50V7K
+0.75VS
JUMP_43X79
2
@
PJ3
2
+5VALWP
+5VALW
+VCCSAP
JUMP_43X118
@ PC8
1000P_0402_50V7K
+VCCSA
D
JUMP_43X118
PC7
1000P_0402_50V7K
PJ4
PC5
100P_0402_50V8J
@ PC1
1000P_0402_50V7K
PC4
100P_0402_50V8J
1
2
1
2
PC3
1000P_0402_50V7K
+0.75VSP
PJ1 @
2
+3VALWP
470P_0402_50V7K PC14
1
2
ACES 88266-04001
CONN@
VIN
HCB2012KF-121T50_0805
1
2
DCJK_IN
330P_0402_50V7K PC10
GND 4
GND 3
2
1
4
3
2
1
PJP1
6
5
PJ6
2
+1.8VS
JUMP_43X118
@ PC9
1000P_0402_50V7K
+1.8VSP
PJ10
@ JUMP_43X39
1
2
1
2
+1.5VP
JUMP_43X118
@ PC12
1000P_0402_50V7K
+VSB
+VSBP
@ PC11
1000P_0402_50V7K
+1.5V
1
PJ9
2
PJ11
JUMP_43X118
PJ12
2
1
2
1
@ PC13
1000P_0402_50V7K
PR1
560_0603_5%
1
2
PR2
560_0603_5%
1
2
+1.05VS_VTT
JUMP_43X118
PBJ1 @
+1.05VSP
+RTCBATT
ML1220T13RE
+CHGRTC
PR3
0_0402_5%
1
2
+3VLP
Compal Secret Data
Issued Date
2011/11/22
2012/11/22
Deciphered Date
Title
PWR DCIN / Pre-charge

Custom
Rev
1.0
Date:
5
Sheet
1
34
of
45
footprint :SUYIN_200275MR008G15QZR_8P-T
PN:DC040007N10 SOCKET BATT C200275MR008G15QZR 8P W/FORK
@
PJP2
D
10
9
8
7
6
5
4
3
2
1
EC_SMDA
EC_SMCA
TH
BI+
PR58
100_0402_1%
GND
GND
8
7
6
5
4
3
2
1
EC_SMB_DA1
<29,36>
EC_SMB_CK1
<29,36>
VL
+EC_VCCA
<40,41>
VMB
SUYIN_200275GR008G16MZR
PR59
100_0402_1%
MAINPWON
4
PR67 @
100K_0402_1%
G
3
1
2
VCIN0_PH <29>
6
C
VCIN1_PROCHOT <29>
@ PR68
28.7K_0402_1%
PR79
10K_0402_1%
SD034100280 10K OHM
PR81
0_0402_5%
1
2
ECAGND
PH1 under CPU bottom side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
<29> H_PROCHOT#_EC
2
PC68
0.22U_0603_25V7K
1
PR70
100K_0402_1%
2
VL
+VSBP
PR71
22K_0402_1%
1
2
B+
EC_SPOK
<29>
<29>
BSS84LT1G_SOT23-3
~OT2 RHYST2
@ PR66
2
1
9.53K_0402_1%
PH1
100K_0402_1%_NCP15WF104F03RC
@
PR80
0_0402_5%
1
2
~OT1TMSNS2
G718TM1U_SOT23-8
@ PQ32
2N7002KW_SOT323-3
GND RHYST1
BATT_TEMP <29>
VCC TMSNS1
<5,29> H_PROCHOT#
PQ19
PR63 CS@
5.62K_0402_1%
+3VLP
PU3 @
@ PR64
100K_0402_1%
PR78
+3VALW
PR65
1K_0402_1%
C
12.4K_0402_1%
1
PC65
0.1U_0603_25V7K
@ PR61
21K_0402_1%
1
PR62
6.49K_0402_1%
2
1
PC67
0.01U_0402_25V7K
VL
ADP_I <29,36>
PR60
1K_0402_5%
JUMP_43X118
PC66
1000P_0402_50V7K
1
2
<40,41>
BATT+
PJ5 @
2
PC69
0.1U_0603_25V7K
+3VALW
PR72
100K_0402_1%
@ PC70
0.1U_0603_25V7K
PQ20
2N7002KW 1N SOT323-3
@ PR74
10K_0402_1%
@ PR75
10K_0402_1%
@ PU4
1
VCC
2
GND
3
OT1
4
OT2
@ PR76
100K_0402_1%
<29,37> MAINPWON
VL
TMSNS1
RHYST1
TMSNS2
RHYST2
PH2_R
@ PR77
47K_0402_1%
6
5
2
G
SPOK
PC71
1U_0402_6.3V6K
<29,37>
PR73
1K_0402_5%
1
2
G718TM1U_SOT23-8
@ PH2
100K_0402_1%_NCP15WF104F03RC
For 65W adapter==>action 70W , Recovery 54W

For 90W adapter==>action 97W , Recovery 75W
A
Compal Secret Data
Issued Date
2011/11/22
2012/11/22
Deciphered Date
Title

Custom
Rev
1.0
Date:
5

PWR-BATTERY CONN/OTP
Sheet
1
35
of
45
for reverse input protection

PC117
0.1U_0402_25V6
PC115
0.1U_0402_25V6
2
1
3M_0402_5%
PC114
0.1U_0402_25V6
1M_0402_5%
PC113
0.1U_0402_25V6
2
1
PC121
0.1U_0402_25V6
2N7002KW 1N SOT323-3
PR13
1
1
PR12
B+
PQ4
2
G
B+
SRN
11
BQ24725_BATDRV
PR29
10
1
2
PR16
0_0402_5%
PC25
0.01U_0402_50V7K
1
2
PC37
0.01U_0402_50V7K
PC36
2200P_0402_50V7K
PC34
10U_0805_25V6K
2
1
PC33
10U_0805_25V6K
2
1
1
2
CSON1
PC38
0.1U_0402_25V6
1
2
CSOP1
PR26
4.7_1206_5%
<29,35>
<29,35>
Issued Date
Compal Secret Data

2011/11/22
Deciphered Date
2012/11/22
Title

PWR DCIN / Pre-charge

Custom
Date:
A
1
2
PC41
0.01U_0402_25V7K
ADP_I
<29,35>
@ PC44
0.1U_0402_25V6
1
2
PC148
100P_0402_50V8J
EC_SMB_CK1
PQ11
2N7002KW 1N SOT323-3
PR33
100K_0402_1%
PC149
100P_0402_50V8J
PC147
100P_0402_50V8J
ILIM
SCL
SDA
1
2
PR37
66.5K_0402_1%
PR39
0_0402_5%
1
2
100P_0402_50V8J
29,33,38,39,40> SUSP#
BATT+
316K_0402_1%
EC_SMB_DA1
PC43
2
G
PR31
<29> FSTCHG
ACDET
1 2
4
PR35
154K_0402_1%
PC42
1000P_0402_50V7K
PR34
2M_0402_1%
ACDET=
2.4 ~3.15 V
Vin=20.55~18.6V
280K_0402_1%
PR36
2M_0402_1%
1
2
1
VIN
PQ10
PDTC115EU_SOT323-3
+3VALW
BQ24725_ILIMT
PR32
PR38
100K_0402_1%
1K_0402_1%
ACDET
PR30
<15,29,33> ACIN
BATDRV
ACOK
IOUT
10K_0402_1%
ACDET
+3VLP
PC48
470P_0402_50V7K
SRP
ACDRV
330P_0402_50V7K
2
1
CMSRC
PC63
1
SRP1
PR27
10_0603_5%
2 CSOP1
PR28
6.8_0603_5%
12 SRN 1
2 CSON1
13
BQ24725_ACDRV
14
GND
3
2
1
ACP
DL_CHG
15
LODRV
PC39
680P_0402_50V7K
3
2
1
2
16
REGN
17
BTST
HIDRV
18
19
20
ACN
PL3
PR25
10UH_FDSD0630-H-100M-P3_3.8A_20%
0.01_1206_1%
1
2 CHG
1
4
BQ24725_LX
BATT+
PC31
1
2
PQ9
SIS412DN-T1-GE3_POWERPAK8-5
BQ24725_CMSRC
470P_0402_50V7K PC17
PQ8
SIS412DN-T1-GE3_POW ERPAK8-5
PD6
RB751V-40_SOD323-2
BQ24725ARGRR _VQFN20_3P5X3P5
1.Change PR33 to 280K 0.1%

2.Chagee PR35 and PR36 to 0.1%.
3.Change PC30 to 1000P.
4.Add PR52,PR70,PR72,PQ17,PQ21.
5.Add GPIO pin,need check HW/EC.
6.Chanrge PR31 to 1K.
PC23
2200P_0402_50V7K
PC22
330P_0402_50V7K
2
1
1
2
PC19
10U_0805_25V6K
PC18
10U_0805_25V6K
PR21
1
2.2_0603_5%
1
BQ24725_BST 2
DH_CHG
PR20
10_1206_1%
BQ24725_LX
PR23
1_0603_5%
1
2
DH_CHG
PAD
BATT_GATE
PC35
0.1U_0402_25V6
1
1
2
PC40
0.1U_0402_25V6
BQ24725_VCC2
0.1U_0402_25V6
2
1
21
PC32
@ 2.2U_0805_25V6K
BQ24725_BATDRV 1
PR17
4.12K_0603_1%
1U_0603_25V6K
PU1
1U_0603_25V6K
PC27
VCC
@
PR24
3.3_1206_5%
PQ7
0.047U_0402_25V7K
PC30
1
2
BQ24725_ACN
1 2
PR22
3.3_1206_5%
BQ24725_ACP
PC29
0.1U_0402_25V6
PR19
4.12K_0603_1%
PC26
0.1U_0402_25V6
PR18
4.12K_0603_1%
PC28
BAS40CW H_SOT323-3
1
2
3
<BOM STRUCTURE>
PD5
BTB_GATE
VIN
2
2
VIN
1
PC20
470P_0402_50V7K
330P_0402_50V7K
2
1
PC16
1
PHASE
1
2
3
CHG_B+
PL2
1UH_NRS4018T1R0NDGJ_3.2A_30%
PR14
0.02_1206_1%
1
4
1
4
PC24
2200P_0402_50V7K
1
2
3
P2
PQ6
PC15
0.1U_0402_25V6
P1
PQ5
PR15
0_0402_5%
VIN
Sheet

D
36
of
45
Rev
1.0
+3VLP
PC52
2
1U_0603_10V6K
@ PC99
100P_0402_50V8J
1
2
PR40
13.7K_0402_1%
1
2
PR41
30.9K_0402_1%
1
2
VFB=2V
VFB=2V
118K_0402_1%
VCLK
DRVL1
PC54
0.1U_0603_25V7K
2
1
PC53
2200P_0402_50V7K
2
1
3
2
1
UG_5V
PC62
1U_0603_10V6K
PR51
+5VALWP
1
3
2
1
Rds=13.5m(min)
= 16.5m(max)
VL
PC61
1U_0603_25V6K
2
1
RT8243_B+
PQ15
SI7716ADN-T1-GE3_POW ERPAK8-5
+5VALWP
PR52
Rds=13.5m(min)
= 16.5m(max)
EN_5V
PC51
4.7U_0805_25V6-K
2
1
1
16
LG_3V
2.2_0603_1%
B
PL6
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
LG_5V
1
2
3
ESR=17m ohm 2
PC56
0.1U_0603_25V7K
1
2
VO1
VREG5
LX_5V
PR47
2.2_0603_5%
1
2
BST_5V
15
DRVH1
14
PQ14
12
DRVL2
DRVH2
13
10
17
VBST2
VBST1
UG_3V
19
18
+
PC58
680P_0402_50V7K
2
1
PC57
220U_6.3V_M
PC55
0.1U_0603_25V7K
11
SW1
PR46
2 1
2BST_3V
2.2_0603_5%
ESR=17m ohm 2
PC59 220U_6.3V_M
PR48
4.7_1206_5%
2
1
2
5
EN_5V
TPS51225CRUKR_QFN20_3X3
SW2
VIN
1
2
3
PL5
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
+3VALWP
LX_3V
20
PQ13
@ PR49
4.7_1206_5%
PGOOD
21
@ PC60
680P_0402_50V7K
EN1
7
PC50
4.7U_0805_25V6-K
2
1
2
PR45
2
VFB1
PAD
<29,35> SPOK
RT8243_B+
EN2
VREG3
EN_3V
CS2
PU2
VFB2
5
PQ12
PR43
20K_0402_1%
1
2
CS1
CS2
PC49
2200P_0402_50V7K
2
1
PC47
10U_0805_25V6K
2
1
PC46
0.1U_0603_25V7K
2
1
B+
RT8243_B+
PL4
HCB2012KF-121T50_0805
1
2
FB_5V
1
PR44
95.3K_0402_1%
FB_3V
PR42
20K_0402_1%
1
2
CS1
@ PC85
100P_0402_50V8J
1
2
(1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=355KHZ (+3VALWP)
PR51 0_0402_5%
1
2
PR50 0_0402_5%
1
2
EN_3V
<29> EC_ON
<29,35> MAINPWON
EN_5V3V
EN
Rising=1.6~0.3V
PR69 2.2K_0402_5%
2
1
PC64
4.7U_0603_6.3V6M
2
1
PR56
402K_0402_1%
PR54 0_0402_5%
+3.3VALWP
Ipeak=5.6A ; 1.2Ipeak=6.72A; Imax=3.92A
f=375KHz, L=4.7UH
Rdson=13~16m ohm
1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=1.48/2=0.74A
Vlimit=10*10^-6*150Kohm/10=0.15V
Ilimit=0.15/(16m*1.2)~0.15/(13m)=7.82A~11.53A
Iocp=7.7A (8.536A>8.4A -> ok)
+5VALWP
Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=300KHz, L=4.7UH,Rentrip=154k ohm
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.63/2=0.815A
Vlimit=10*10^-6*154Kohm/10=0.15V
Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
Iocp=14.2A
A
Compal Secret Data
2011/11/22
Issued Date
Deciphered Date
2012/11/22
Title
3VALWP/5VALWP
Size
Document Number
Custom
Date:
5
Sheet
1
37
of
45
Rev
1.0
PJ18
1
1.5V_B+
1
2
+1.5VP
JUMP_43X79
PC72
10U_0805_25V6K
B+
PQ30
1
1
S3
S5
S0
Hi
Hi
On
On
S3
Lo
Hi
On
On
Lo
Lo
S4/S5
1.5VP
VTT_REFP
2
3
2
1
1
2
2
1
PR97
10K_0402_5%
PC77
1U_0603_10V6K
2
1
PGOOD
need change OCP setting
PC78
1U_0603_10V6K
PGOOD_1.5V
PR95
10.5K_0402_1%
2
1
PR169
10K_0402_1%
2
G
FB=0.75V
To GND = 1.5V
To VDD = 1.35V
2N7002KW _SOT323-3
STATE
+5VALW
PQ31
2
1
PR174
5.1_0603_5%
VDD_1.5V
PC100
100P_0402_50V8J
1
2
<33,39,40> SUSP
Rds=13.5m(Typ)
16.5m(Max)
+3VALW
10
8
S5_1.5V
S3
FB
7
FB_1.5V
@ PC96
0.1U_0402_16V7K
PC325
0.1U_0402_16V7K
<29,33> SYSON
11
PC75
680P_0402_50V7K
PQ29
12
VDD
1.5V_TON
PR172
887K_0402_1%
2
1 1.5V_B+
PR171
0_0402_5%
1
2
1
<29,33,36,39,40> SUSP#
PR173
680K_0402_1%
1
2
PR170
21.5K_0402_1%
2
1
1.5V_CS
13
CS
VDDP
VDDQ
PC98
0.033U_0402_16V7K
VTTREF
S3_1.5V
1
2
+1.5VP
RT8207MZQW _W QFN20_3X3
TON
+VTT_REFP
GND
220U 2V Y D2 ESR15M
PC232
LG_1.5V
14
PGND
S5
VTTSNS
+1.5VP
2
15
LGATE
1.5UH +-20% PCMC063T- 9A
LX_1.5V
16
PL16
1
UG_1.5V
17
PC76
0.1U_0603_25V7K
1
2
BST_1.5V-1
PR175
4.7_1206_5%
PHASE
BST_1.5V
18
PR96
0_0603_5%
1
2
VTTGND
UGATE
PAD
BOOT
VLDOIN
19
PU8
21
20
Output Cap PAD

VTT
PC73
10U_0805_25V6K
PC97
10U_0805_25V6K
+0.75VSP
2
LDO_IN
3
2
1
PJ15
JUMP_43X79
<Vo=1.5V> VFB=0.75V
V=0.75*(1+10K/10.5K)=1.52V
Fsw=286K to 200KHz
0.75VSP
On
Off
(Hi-Z)
Cout ESR=17m ohm Rdson(max)=16.5 mohm

Ipeak=12 A, Imax=8.4A, Iocp=14.4A
Rdson(typ)=13.5 mohm.
Delta I=((Vin-Vo)*(Vo/Vin))/(L*Fsw)=2.195A
=>1/2Delta I=1.099A
Off
Off
Off
(Discharge) (Discharge) (Discharge)
Iocpmax=((21.5K*11uA)/0.0135)+0.5 delta I= A
Iocpmin=((21.5K*9uA)/(0.0165))+0.5 delta I=15.6A
Note: S3 - sleep ; S5 - power off
Compal Secret Data
Issued Date
2011/11/22
Deciphered Date
2012/11/22
Title

PWR-+1.5VP
Document Number
Custom
Rev
1.0
Date:
A
Sheet
D
38
of
45
+1.8VSP
1
PQ34B
@
PC80
68P_0402_50V8J
2
1
<33,38,40> SUSP
D
PR84
20K_0402_1%
PU6
PC83
0.1U_0402_10V7K
EN
FB
GND
PG
LX
FB_1.8V
FB=0.6Volt
5
4
IN
PR87
10K_0402_1%
SY8032ABC_SOT23-6
<BOM Structure>
PL9
1UH +-20% VMPI0703AR-1R0M-Z01 11A
2
1LX_1.8V
PJ16
1
8032_IN
+3VALW
@
2
PC79
22U_0805_6.3V6M
4.7_0603_5%
PR83
2
1
JUMP_43X79
680P_0402_50V7K
PC84
2
1
22U_0805_6.3V6M
PC82
2
1
+1.8VSP
22U_0805_6.3V6M
PC81
2
1
2
1
PR86
1M_0402_5%
EN_1.8V
PR85 200K_0402_5%
<29,33,36,38,40> SUSP#
1.8VSP
Ipeak=1.24A
Vout=0.6*(1+(20K/10K))=1.8V
PG
VOUT
VID1
EN
VID0
SA_PGOOD
PR89
100K_0402_5%
1
2
4
5
+VCCSA_EN
PR90
0_0402_5%
<29>
+3VS
100P_0402_50V8J
PC146
PR88
4.7_0603_5%
VCCPPWRGOOD
<40>
PC145
100P_0402_50V8J
@
@ PC94
680P_0402_50V7K
13
@
FB_VCCSA
+VCCSAP
PC93
2200P_0402_50V7K
2
1
LX
FB
SVIN
PC92
22U_0805_6.3V6M
1
2
LX
PL10
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2
+VCCSA_PHASE
PC91
22U_0805_6.3V6M
1
2
10
PC88
68P_0402_50V8J
2
1 FB_VCCSA_IC9
PVIN
PC90
.1U_0402_16V7K
2
1
11
LX
PVIN
JUMP_43X79
12
+VCCSA_PWR_SRC
GND
PC89
22U_0805_6.3V6M
1
2
PC87
0.1U_0402_25V6
1
2
PC86
2200P_0402_50V7K
SY8037DDCC DFN 12P
PU7
PJ17
+3VALW
@ PC95
.1U_0402_16V7K
H_VCCSA_VID0
PR91
1K_0402_5%
2
1
<9>
The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
PR92
1K_0402_5%
2
1
H_VCCSA_VID1
PR93
100_0402_1%
2
1
<9>
PR94
0_0402_5%
2
1
+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A
A
VID [0]
0
0
1
1
VCCSA_SENSE
<9>
VID[1]
0
1
0
1
VCCSA Vout(ULV only)

0.9V
0.85V
0.775V
0.75V
output voltage adjustable network
Compal Secret Data
Issued Date
2011/11/22
Deciphered Date
2012/11/22
Title
PWR +VCCSAP
Size
C
Date:

Document Number
Rev
1.0

Sheet
1
39
of
45
PL11
HCB2012KF-121T50_0805
3
2
1
DRVL
TP
LG_1.05V
11
TPS51212DSCR_SON10_3X3
SUSP
<33,38,39>
PQ24
AO4456_SO8
PC111
4.7U_0805_10V6K
DMN66D0LDW -7_SOT363-6
PQ34A
@
Rds=4.5m(min)- 5.6m(Max)
PC104
0.1U_0402_25V6
2
1
1
+
PR176
1
2
4.99K_0402_1%
PR188
1
VCCIO_SENSE
<8>
100_0402_1%
1000P_0402_50V7K 1.2K_0402_1%
PC122
PR186
PR106
10K_0402_1%
<Vo=1.05V> VFB=0.75V
V=0.704*(1+4.02K/10K)=1.052V
Fsw=290KHz
PC103
2200P_0402_50V7K
2
1
1
2
PC112
680P_0603_50V7K
FB_1.05V
PR104
470K_0402_1%
PR102
4.7_1206_5%
+5VALW
PC102
4.7U_0805_25V6-K
5
6
7
8
LX_1.05V
330U_D2_2V_Y_R9
PC257
TST
8
7
V5IN
PC105
0.1U_0402_25V6
+1.05VSP
2200P_0402_50V7K
SW
VFB
UG_1.05V
PC110
VFB=0.7V
EN
PC109
0.1U_0402_25V6
2
1
PC107
0.1U_0402_16V7K
DRVH
PC124
0.1U_0402_16V7K
2
1
VBST
TRIP
B+
PL12
1UH +-20% VMPI0703AR-11A
1
2
PGOOD
BST_1.05V
10
1.05V_EN
@ PR103
30K_0402_5%
84.5K_0402_1%
2
1
SUSP#
<29,33,36,38,39>
PR100
PR101
330K_0402_1%
1
2
PR99
PC106
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_1.05V-1 1
2
PU9
VCCPPW RGOOD
<39>
3
2
1
PR98
10K_0402_1%
+1.05VSP
PQ23
SIS412DN-T1-GE3_POWERPAK8-5
PC101
4.7U_0805_25V6-K
1.05V_B+
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.

Ipeak=15.6A, Imax=10.92A, Iocp=18.72A
A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=2.06A
Iocpmax=((15K*11uA)/0.0045)+1.665A=23.54A
Iocpmin=((15K*9uA)/(0.0056*1.3))+1.665A=19A
Iocp=A
Compal Secret Data
2011/11/22
Issued Date
Deciphered Date
2012/11/22
Title
Size
Document Number
Custom
Date:
5

PWR +1.05VS_VCCPP/+0.75VSP
Sheet
1
40
of
45
Rev
1.0
+GFX_B+
@ PC125
1000P_0402_50V7K
2 2
+
PC132
PQ27
2
1
PR140
2.55K_0402_1%
MDV1525URH
PL15
0.22UH 20% FDUE0640J-H-R22M=P3 25A
2
1
1
PC135
680P_0402_50V7K
1 2
PR138
1_0402_5%
PC194
470P_0402_50V7K
PHASEA_GFX
PR130
3.65K_0402_1%
VSUMG-
UGA_GFX
2
1
BOOTA_GFX
PR154
4.7_0603_5%
VSUMG+
5
4
LGA_GFX
LGA_GFX
1
PR159
0_0603_5%
@ PR185
2
LG1_CPU
1.91K_0402_1%
1
18
PHASE1_CPU
17
UG1_CPU
PC261
1U_0603_10V6K
2
1
20
19
PR179
2
UG1_CPU
0_0603_5%
1
UG1_CPU-1
PC21
470P_0402_50V7K
PC45
1
330P_0402_50V7K
2
1
2
1
1
2
PC116
33U_25V_M
B+
+CPU_CORE
PR137
1_0402_5%
1
3
2
1
PC123
PR128
680P_0402_50V7K 4.7_0603_5%
2.61K_0402_1%
1
PR180
1
11K_0402_1%
12
2
PR184
VSUM-
10K_0402_1%_ERTJ0EG103FA
2
PC259
0.1U_0603_25V7K
1
2
PC169
0.047U_0402_25V7K
PR187
348_0402_1%
PR129
3.65K_0402_1%
VSUM+
Close Phase 1 choke
VSUM-
+CPU_CORE
Load line= -2.9 mohm
0.22uH DCR= 0.85+-5% m ohm
.1U_0402_16V7K
local sense revese HW
PH3
PC266
2
1
PC264
150P_0402_50V8J
2
1
2
1
PR190
137K_0402_1%
PC143
PR146
2200P_0402_50V7K 649 +-1% 0402
2
1
2
1
PC170
68P_0402_50V8J
2
1
4
LG1_CPU
VSUM+
PL14
0.22UH +-20% PCMB104T-R22MS 35A
2
1
PQ33
MDU1511RH_POWERDFN56-8-5
3
2
1
2.2_0603_5%
PC171 0.1U_0603_25V7K
1 2
1
PR181
BOOT_CPU 2
PQ26
PR189
1.91K_0402_1%
2
1
MDU1516URH_POWERDFN56-8-5
PHASE1_CPU
CM@
1
PR183
499_0402_1%
PQ25
+3VS
PR177
42.2K_0402_1%
2
1
PC260
470P_0402_50V7K
2
1
2
PC119
10U_0805_25V6K
<15>
PC120
0.1U_0402_25V6
1.91K_0402_1%
1
LG1_CPU
PR203
2K_0402_1%
2
1
PC118
10U_0805_25V6K
2
VGATE
PR202
2
HCB2012KF-121T50_0805
2
1
@ PR197
0_0402_5%
PC162
470P_0402_50V7K
2
1
PL18
+CPU_B+
BOOT_CPU
+5VS
21
PC258
1U_0603_10V6K
1
2
UGATEG
25
26
BOOTG
27
28
COMPG
PGOODG
30
31
29
FBG
RTNG
PHASE1
UGATE1
22
5 3
2
1
PR201
61.9K_0402_1%
ISUMNG
33
ISEN2
23
PR162
1_0603_5%
PR204
3.83K_0402_1%
@ PC126
0.1U_0402_16V7K
1
2
+1.05VS_VTT
NTC
+5VS
PR196
0_0402_5%
PH5
470K_0402_5%_ TSM0B474J4702RE
2
1
2
1
1
2
PR156
130_0402_1%
1
2
PR200
75_0402_5%
1
2
PR160
54.9_0402_1%
2
PR168
0_0402_5%
@ PC263
47P_0402_50V8J
LGATE1
BOOT1
7
1
VR_HOT#
24
GT2
Iccmax=29A
Max Istep=13A
PS1 current=20A
TDP=18.3A
+GFX_CORE
Load line = -3.9m ohm
0.22uH DCR= 0.97+-5% m ohm
16
VR_HOT
PWM2
PGOOD
<29>
VDD
SDA
15
COMP
SVID_DATA
ISL95833HRTZ-T_TQFN32_4X4
FB
SVID_DATA
ALERT#
14
<8>
SVID_ALERT# 4
VCCP
RTN
SVID_ALERT#
LGATEG
SCLK
13
<8>
VR_ON
ISUMN
ISUMP
12
2
0_0402_5%
PHASEG
11
SVID_CLK
NTCG
10
ISEN1
1
NTCG
470K_0402_5%_ TSM0B474J4702RE
SVID_CLK
<8>
1
PR165
VR_ON
PH4
2
PC163
100P_0402_50V8J
2
1 SVID_CLK
PC161
100P_0402_50V8J
2
1 SVID_ALERT#
PC144
100P_0402_50V8J
2
1
SVID_DATA
<29>
PAD
PR158
3.83K_0402_1%
1
2
ISUMPG
32
+5VS
PU13
PR152
61.9K_0402_1%
2
1
+VGFX_CORE
SH00000O200
PQ28
0.1U_0603_25V7K
PC183
2
1 2
1
BOOTA_GFX
PR182 2.2_0603_5%
PR205
2K_0402_1%
PR147
PC160
33U_25V_M
2
1
1
2
1
2
PC131
10U_0805_25V6K
PC130
10U_0805_25V6K
5
4
UGA_GFX
PHASEA_GFX
2
1
1.91K_0402_1%
VSUMG+
+3VS
PC134
470P_0402_50V7K
2
1
2
1
PR134
499_0402_1%
2
1
PR143
33.2K_0402_1%
PC141
0.022U_0402_25V7K
2
1
PC140
0.1U_0603_25V7K
1
2
PC136
150P_0402_50V8J
2
1
2
1
PR136
137K_0402_1%
3
2
1
PC133
68P_0402_50V8J
2
1
PR135
430_0402_1%
2
1
PR142
11K_0402_1%
1
2
PR141
2.61K_0402_1%
1
2 1
B+
1
3
2
1
PC127
0.01UF_0402_25V7K
PL17
HCB2012KF-121T50_0805
2
1
PR139
649 +-1% 0402
1
2
PC142
<9> VSS_GFXSENSE
2200P_0402_50V7K
PH6
10K_0402_1%_ERTJ0EG103FA
VSUMG-
.1U_0402_16V7K
PC137
2
1
VCC_GFXSENSE
<9>
0.1U_0402_25V6
ICCMAX=33A
I tdc=15.8~ 20 (Tdc-up)A
PS1=20A
Max Istep=28A
@ PC265
330P_0402_50V7K
2
1
<8>
<8>
VCCSENSE
VSSSENSE
PC262
0.01UF_0402_25V7K
Compal Secret Data
Issued Date
2011/11/22
Deciphered Date
2012/11/22
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number
CPU/GFX_CORE
Date:
A
Sheet
E
41
of
45
Rev
1.0
1U_0402_6.3V6K
PC244
330U_D2_2V_Y
PC203
PC210
10U_0603_6.3V6M
2
1
PC211
10U_0603_6.3V6M
2
1
PC212
10U_0603_6.3V6M
2
1
PC213
10U_0603_6.3V6M
2
1
PC214
10U_0603_6.3V6M
2
1
PC215
10U_0603_6.3V6M
2
1
PC216
10U_0603_6.3V6M
2
1
PC217
10U_0603_6.3V6M
2
1
PC218
10U_0603_6.3V6M
2
1
PC224
10U_0603_6.3V6M
2
1
1U_0402_6.3V6K
PC223
1U_0402_6.3V6K
PC222
1U_0402_6.3V6K
PC221
1U_0402_6.3V6K
PC220
1U_0402_6.3V6K
PC219
PC108
470P_0402_50V7K
PC74
1
330P_0402_50V7K
2
1
1U_0402_6.3V6K
PC209
1U_0402_6.3V6K
PC208
1U_0402_6.3V6K
PC207
1U_0402_6.3V6K
PC206
1U_0402_6.3V6K
PC205
330U_D2_2V_Y
PC182
PC181
330U_D2_2V_Y
330U_D2_2V_Y
PC180
330U_D2_2V_Y
PC179
PC185
330U_D2_2V_Y
PC184
330U_D2_2V_Y
PC178
10U_0603_6.3V6M
2
1
PC177
10U_0603_6.3V6M
2
1
PC176
10U_0603_6.3V6M
2
1
PC175
10U_0603_6.3V6M
2
1
PC174
10U_0603_6.3V6M
2
1
PC173
10U_0603_6.3V6M
2
1
PC172
22U_0805_6.3V6M
PC168
22U_0805_6.3V6M
PC167
22U_0805_6.3V6M
PC166
22U_0805_6.3V6M
PC165
22U_0805_6.3V6M
1U_0402_6.3V6K
PC227
1U_0402_6.3V6K
PC225
1U_0402_6.3V6K
PC226
1U_0402_6.3V6K
PC228
1U_0402_6.3V6K
PC229
1U_0402_6.3V6K
PC235
1U_0402_6.3V6K
PC230
1U_0402_6.3V6K
PC231
1U_0402_6.3V6K
PC236
1U_0402_6.3V6K
PC237
1U_0402_6.3V6K
PC238
1U_0402_6.3V6K
PC240
PWR - PROCESSOR DECOUPLING
1U_0402_6.3V6K
PC242
1U_0402_6.3V6K
PC241
1U_0402_6.3V6K
PC243
1U_0402_6.3V6K
PC245
1U_0402_6.3V6K
PC247
1U_0402_6.3V6K
PC246
1U_0402_6.3V6K
PC248
1U_0402_6.3V6K
PC250
1U_0402_6.3V6K
PC249
1U_0402_6.3V6K
PC251
1U_0402_6.3V6K
PC252
1U_0402_6.3V6K
PC253
45
of
42
Sheet
Date:
Rev
1.0
Document Number
Size
Title

Compal Secret Data
1
2
2
2
2
2
2012/11/22
Deciphered Date
2011/11/22
Issued Date
1U_0402_6.3V6K
PC204
PC202
2.2U_0402_6.3V6M
PC201
2.2U_0402_6.3V6M
PC200
2.2U_0402_6.3V6M
PC199
2.2U_0402_6.3V6M
PC198
2.2U_0402_6.3V6M
PC197
2.2U_0402_6.3V6M
PC196
2.2U_0402_6.3V6M
1U_0402_6.3V6K
PC239
PC159
22U_0805_6.3V6M
PC158
22U_0805_6.3V6M
PC233
22U_0805_6.3V6M
PC234
22U_0805_6.3V6M
PC193
2.2U_0402_6.3V6M
PC192
2.2U_0402_6.3V6M
PC191
2.2U_0402_6.3V6M
PC190
2.2U_0402_6.3V6M
PC189
2.2U_0402_6.3V6M
PC188
2.2U_0402_6.3V6M
PC187
2.2U_0402_6.3V6M
PC195
2.2U_0402_6.3V6M
3
4
PC157
22U_0805_6.3V6M
PC156
22U_0805_6.3V6M
PC155
22U_0805_6.3V6M
PC154
22U_0805_6.3V6M
PC153
22U_0805_6.3V6M
PC152
22U_0805_6.3V6M
PC151
22U_0805_6.3V6M
PC186
2.2U_0402_6.3V6M
1U_0402_6.3V6K
PC254
Mid-Frequency Decoupling
10x10F
+1.05VS_VTT
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
Low-Frequency
Decoupling 1x330 F 9m
A
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
High-Frequency Decoupling
27x1F
+1.05VS_VTT
16x2.2F
B
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
PC150
22U_0805_6.3V6M
+CPU_CORE
1
1
Low-Frequency
+
+
Low-Frequency
11x1F
+
1
1
2
2
2
2
PC164
22U_0805_6.3V6M
12x22F
1
1
2
2
2
2
1
1
1
1
1
1
@
+
+
2
2
2
2
2
2
2
2
1
1
C
1
1
1
1
2
2
2
2
2
2
D
6x10F 0603
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+VGFX_CORE
+VGFX_CORE
6x22F
+CPU_CORE
1
2
3
4
5
CR PDDG Rev 0.95
Version change list (P.I.R. List)

Item
Fixed Issue
Page 1 of 1
for PWR
Reason for change
Rev.
PG#
Modify List
Date
0.1
0.1
Phase
2010/12/29
2010/12/29
---
2011/02/08
2011/02/08
2011/02/08
5
C
---
---
2011/02/16
---
2011/05/13
PVT2
---
2011/05/13
PVT2
10
---
2011/05/13
PVT2
11
---
2011/05/13
PVT2
2011/05/13
PVT2
2011/02/08
12
13
14
A
15
2011/11/22
Issued Date
Compal Secret Data
Deciphered Date
2012/11/22
Title
Document Number
Custom
PIR (PWR)
Rev
1.0
Date:
5
Sheet
1
43
of
45
(PU13)
RT8167BGQW
VR_ON
WQFN40
ADAPTER
D
SYSON
SON10
+1.5VS
+1.5V_CPU_VDDQ
+1.05VS_VTT
Page 40
PJ4
+VCCSAP
DFN12
CHARGER
PJ11 & PJ12
+1.05VSP
(PU7)
SY8037DCC
VCCPPWRGOOD
J1
Page 33
+0.75VS
Page 38
(U38)
AO4478L_SO8
SUSP
+1.5V
(PU9)
TPS51212DSCR
SUSP#
BATTERY
+VGFX_CORE
Page 41
WQFN20
+CPU_CORE
(PU8)
RT8207MZQW
SUSP#
B+
+VCCSA
Page 39
(PU2)
RT8243BZQW
EC_ON
MAINPWON
WQFN20
Page 37
+LED_VOUT
+5VALW
SUSP
SYSON#
(U35)
AO4478L
SOP8
PCH_PWR_EN#
(U28)
G547I2P81U
Page 33
+5VS
R630
+3VALW
PCH_PWR_EN#
(Q8)
AP2301GN-HF
MSOP8
SOT23-3
+USB3_VCCA
Page 20
+5VREF_SUS
SUSP
PCH_PWR_EN#
(Q68)
AP2301GN-HF
SOT23-3
+3VALW_PCH
R285
R359
Q37
SOP8
Page 20
+VCCSUS3_3
+3V_LAN
WLAN_ON
(U37)
AO4478L
+3VALW_EC
+3VS_WLAN
Page 33
MSOP8
Page 26
+SDPWR_MMCPWR
+3VS
PCH_ENVDD
(U25)
BCM57785
+CRT_VCC
CR_PWR_EN
(U27)
AP2301MPG
+DVDD_AUDIO
(Q10)
AO3419L
SO23-3
+HDMI_5V_OUT
J4
+1.2V_LAN
+3VS_WLAN
Page 22
+LCDVDD
+5VS_HDD
R453
+VDDA
(U34)
ALC271X-VB6
+CAM_VCC
TPM
(U33)
APL5607KI-TRG
TP
Compal Secret Data
Issued Date
2011/06/13
2012/06/13
Deciphered Date
Title

Power Rail
Rev
1.0
Date:
5
Sheet
1
44
of
45
B6
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_A#
PM_SLP_SUS#
EC_ON
U19
PM_DRAM_PWRGD
PBTN_OUT#
14
15
U2
CPU
H_CPUPWRGD
PLT_RST#
UCPU1
C
SYSON
SYSON#
SUSP#,SUSP
ON/OFF
13
PCH
U16
A4
PCH_RSMRST#
B7
SYS_PWROK
U30
V V
51ON#
9012_PCH_PWROK
EC
A5
10
PU8
+1.5VP
PQ17
B3
+5VALW
B4
B+
B2
PCH_PWROK
V V
B1
B7
V V
+3VALW
V V
PU2
A5
B+
BATT
+VCCDSW3_3
+5VREF_SUS
B5
PU1
A3
VV
A2
V V
VIN
BATT
MODE
Q68,+VCCDSW3_3
Q8,+5VREF_SUS
A1
AC
MODE
PCH_PWR_EN#
U35
+5VS
11
U37
+3VS
U38
+1.5VS
PU6
+1.8VS
VGATE
PU8
+0.75VSP
PU9
+1.05VSP
VCCPPWRGOOD
PU7
+VCCSAP
SUSP#,SUSP
PU10
+CPU_CORE
+VGFX_CORE
VR_ON
A
Compal Secret Data
Issued Date
2011/06/13
2012/06/13
Deciphered Date
Title

Power sequence
Rev
1.0
Date:
5
Sheet
1
45
of
45

C26a2 COmpal LA-8941P

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A

Model Name : Q1VZC

Q1VZC M/B Schematics Document

Compal Electronics, Inc.

Compal Secret Data

Q1VZC M/B LA-8941P Schematic

Friday, April 20, 2012

1.5V DDRIII 1066/1333

Power On/Off CKT.

DC/DC Interface CKT.

Compal Electronics, Inc.

Compal Secret Data

Power Circuit DC/DC

Q1VZC M/B LA-8941P Schematic

Friday, April 20, 2012

Adapter power supply (19V)

Battery power supply (12.6V)

AC or battery power rail for power circuit.

Core voltage for CPU

Core voltage for UMA graphic

Board ID / SKU ID Table for AD channel

+0.75VP to +0.75VS switched power rail for DDR terminator

+1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU

+1.5VP to +1.5V power rail for DDRIII

+1.5V to +1.5VS switched power rail

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU

+3VALW always on power rail

+3VALW to +VCCSUS3_3 power rail for PCH (Short Jump)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5VREF_SUS power rail for PCH (Short resister)

+5VALW to +5VS switched power rail

+VSBP to +VSB always on power rail for sequence control

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

PCH SM Bus address

BTO Option Table

USB Port Table

USB 3.0 Port

USB Port(Right 3.0)

Compal Electronics, Inc.

Compal Secret Data

Q1VZC M/B LA-8941P Schematic

Friday, April 20, 2012

PEG_ICOMPI and RCOMPO signals should be

W=12mil L=500mil S=15mil

PCI EXPRESS -- GRAPHICS

eDP_COMPIO and ICOMPO signals

W=12mil L=500mil S=15mil

SA00005BH40(S IC AV8062701148901 SR0FK J1 1.3G ABO!)

SA00005BJ50(S IC AV8062701147701 SR0FB J1 1.4G ABO!)

SA00004X010(S IC AV8062701047504 SR0D6 J1 1.6G ABO!)

SA000051H60( S IC AV8062701047904 SR0CV J1 1.4G ABO! )

SA00005QI00( S IC AV8062701148001 QB35 J1 1.4G BGA)

SA00005QH00(S IC AV8062701147601 QB31 J1 1.5G BGA)

SA000051J40(S IC AV8062701147801 SR0FC J1 1.3G ABO!)

SA00005MX10(S IC AV8062701048004 QAXQ J1 1.5G BGA)

SA00005K650(S IC AV8063801058002 QC9E L1 1.7G BGA)

SA00005LA50(S IC AV8063801057405 QC9B L1 2G BGA 1023)

SA00005L530(S IC AV8063801058400 QC56 L0 1.8G ABO!)

SA00005L9A0(S IC AV8063801057801 SR0N7 L1 1.8G BGA)

SA00005K540(S IC AV8063801057605 QC9C L1 1.9G BGA)

Compal Electronics, Inc.