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Thuc Hanh Thiet Ke Mach So Voi HDL
Thuc Hanh Thiet Ke Mach So Voi HDL
Thuc Hanh Thiet Ke Mach So Voi HDL
THC HNH
THIT K MCH S VI HDL
TP.HCM, 9-2009
Gii thiu
B ti liu thc hnh thit kt mch s vi HDL c son tho nhm mc ch h
tr cc bn sinh vin trong vic tip xc vi ngn ng c t phn cng. M c th l h
tr cho mn hc thit kt mch s vi HDL.
Ti liu ny bao gm 9 bi, tng ng vi 9 bui. Ni dung chu yu hng n
vic hc t duy thit kt phn cng. Gip sinh vin luyn tp cc k nng lp trnh vi
Verilog, m phng trn Model Sim hay trc tip trn board DE2.
Mc d rt c gng nhng cng khng th trnh khi nhng sai st. V vy rt
mong nhn c kin ng gp t pha bn c hoc cc bn sinh vin.
Chn thnh cm n!
TP.HCM, ngy 27thng 9 nm 2009
Mc lc
Bui 1.
Tng quan v cc phn mm thit k trn FPGA ....................................... 7
I. Gii thiu Board DE2 ca Altera ............................................................................. 7
1.
Gii thiu .......................................................................................................... 7
2.
Thnh phn ....................................................................................................... 7
3.
Mt vi ng dng ca board DE2 .................................................................... 8
II. Cch ci t Quartus II 8.0 v Nios II ..................................................................... 9
1.
Gii thiu .......................................................................................................... 9
2.
Ci t ............................................................................................................. 10
III. Cch np chng trnh cho Quartus II 8.0: ............................................................ 13
1.
To 1 project: .................................................................................................. 13
2.
Vit chng trnh v bin dch: ...................................................................... 17
3.
To file m phng (simulate) v bt u simulate ......................................... 22
4.
Cu hnh chn v np ln board...................................................................... 30
Bui 2.
Mch t hp v mch tun t...................................................................... 40
I. Gii thiu ............................................................................................................... 40
1.
Gii thiu ........................................................................................................ 40
2.
Hng dn thit k FPGA thng qua s khi/Schematic .......................... 40
II. Bi tp .................................................................................................................... 46
Bui 3.
Lp trnh Verilog vi m hnh cu trc ..................................................... 48
I. Gii thiu ModelSim ............................................................................................. 48
1.
Gii thiu ........................................................................................................ 48
2.
Ci t ............................................................................................................. 48
3.
Hng dn ...................................................................................................... 58
II. Bi tp .................................................................................................................... 65
Bui 4.
M hnh hnh vi ............................................................................................ 67
I. Bi tp .................................................................................................................... 67
Bui 5.
M hnh hnh vi (tt)...................................................................................... 71
I. Bi tp .................................................................................................................... 71
Bui 6.
My trng thi .............................................................................................. 75
I. Gii thiu ............................................................................................................... 75
1.
Gii thiu ........................................................................................................ 75
2.
Hng dn ...................................................................................................... 75
II. Bi tp .................................................................................................................... 83
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Bui 1.
Khoa KH&KTMT
Mc tiu
Nm c cng ngh FPGA
Lm quen board thc hnh DE2
Ci t, v lm quen vi cc phn mm: Quartus II, Nios II
2. Thnh phn
Board DE2 cung cp kh nhiu tnh nng h tr cho vic nghin cu v pht
trin, di y l thng tin chi tit ca mt board DE2:
FPGA:
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B nh:
-
SRAM 512-Kbyte.
SDRAM 8-Mbyte.
B nh cc nhanh 4-Mbyte (1 s mch l 1-Mbyte).
Khe SD card.
4 nt nhn, 18 nt gt.
18 LED , 9 LED xanh, 8 Led 7 on
LCD 16x2
B dao ng 50-MHz v 27-MHz cho ng h ngun.
Hnh 2. TV Box
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2. Ci t
Ci t Quartus II v Nios II
Qu trnh ci t Quartus II v Nios n gin ch cn a a vo my v thc
hin theo hng dn ca chng trnh ci t
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Kt tip bn chn Search for the best driver in these location v sau nhn
Browse.
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Hp
thoi
mi
s
xut
hin
bn
tm
n
v
altera\quartus60\drivers\usbblaster, sau nhn OK v tip tc nhn Next
tr
Ca s thng bo vic kim tra logo window khng thnh cng, tuy nhin
vic ny s khng b nh hng n vic kt ni ca chng trnh sau ny. Bn
tip tc nhn Continue Anyway
Hnh 9. Thng bo li
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Bc 2.
Ta chn th mc cha project v t tn cho project, xem hnh
bn di
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Bc 3.
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Bc 4.
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Bc 2.
Sau chn loi file m chng ta mun vit chng trnh. y ta
chn loai file Verilog HDL
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Bc 3.
x2
Bc 4.
Sau khi vit xong th ta phi lu tn file trng vi tn module ca
chng trnh
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Bc 6.
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Vo Menu > file chn New, sau chn Vector Waveform File
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Bc 2.
Sau nhp chut phi chn Insert, chn Insert Node or bus
Bc 3.
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Bc 4.
Ca s la chn tn hiu s xut hin (xem hnh 26).
hin th ra tt c cc chn :
Chn Pins: all.
Sau chn nt List hin tt c cc chn.
Nt
Nt
: Chn tt c cc tn hiu
Nt
: B tng tn hiu
Nt
: B tt c cc tn hiu
V d mun chn 3 tn hiu f, x1, x2 ta c 2 cch:
Nhn nt
chn tt c c tn hiu
Nhn OK hon tt vic chn tn hiu
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Bc 6.
Thit lp gi tr cc tn hiu:
Ta r chut t khi chng li
Sau s dng cc nt 0, 1 thit lp gi tr cho chng (xem hnh 28)
Bc 7.
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Bc 8.
Nhp vo nt
Bc 9.
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Bc 10.
Vo Processing > Generate Functional Simulation Netlist tin
hnh qu trnh phn tch v tng hp
Hnh 32. Thc hin chc nng tng hp v phn tch chng trnh
Bc 11.
Hp thoi thng bo qu trnh phn tch v tng hp thnh cng,
chn OK n nh
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Bc 12.
Bc 13.
Nhn vo nt
Bc 14.
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Bc 15.
Chn Processing > Start Simulation hoc nhp vo nt
tin
hnh qu trnh simulation. Nu thnh cng th s c thng bo nh hnh 38, v
kt qu qu trnh m phng s c hin th nh hnh 39.
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Bc 2.
Nhp p vo <<new>> ct To nh trn hnh. Mt menu cha
danh sch cc chn cn gn s c hin ra. Bn chn chn cn gn (v d
y chn tn hiu cn gn x1).
Bc 3.
Tip theo nhn vo <<new>> ct Location. Mt menu cha
danh sch cc chn trong FPGA s c hin ra bn chn chn ca FPGA s
ni vi tn hiu (v d y chn chn PIN_N25).
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Bc 4.
Bc 5.
lu li file cu hnh chn bn chn File -> Export, sau nhp
tn file cn lu.
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Bc 6.
nhng ln cu hnh sau ta c th load file cu hnh bng cch
(nu ln cu hnh chn ny l hon ton ging vi ln cu hnh trc). Bn
chn. Assignment -> Import Assignments, tip theo bn chn file cu hnh
chn ri nhn OK.
Np ln board
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Bc 2.
Trn ca s lp trnh, ch la chn JTAG trong khung ch lp
trnh (Mode). Tip o nu USB-Blaster khng c chn nh trn hnh, th
bn nhn Hardware Setup, ca s Hardware Setup s xut hin khi bn
chn USB-Blaster la chn cng kt ni vi board DE2.
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Bc 3.
Tr li ca s lp trnh bn chn vo file lp trnh (light.sof). Nu
file ny cha c th bn c th nhn nt Add File thm file ny vo. Tip
bn nhp vo la chn Program/configure
Bc 4.
Nhn nt Start bt u vic lp trnh. Trong khi lp trnh th cc
n led trn board DE2 s sng m i. Trn ca s lp trnh, thanh Progess s
cho thy tin trnh np ln board DE2.
Lp trnh theo ch AS
Bc 1.
Gt nt RUN/PROG trn board DE2 sang PROG.
Bc 2.
Vo Assignment -> Device, chn Device v sau chn thit b l
EP2C35F672C6. Tip nhp vo Device & Pin Options, ca s Device &
Pin Opions s xut hin, bn chn tab Configuration, trong khung
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Bc 3.
Tools->Programmer, ca s lp trnh s xut hin (nh hnh ca
s lp trnh). Tip trong khung Mode bn chn Active Serial
Programming. Mt thng bo s hin ln bn chn Yes.
Bc 4.
Ca s lp trnh ch AS s hin ra nh hnh bn di. Bn
chn nt Add File thm file cn np vo chng trnh (light.pof, file
cu hnh cho ch AS s c dng *.pof v file cu hnh cho ch JTAG s
c dng *.sof).
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Bc 5.
Nhp vo la chn Program/Configure. Tip bn nhn nt
Start np chng trnh cu hnh ln board DE2
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Bui 2.
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I. Gii thiu
1. Gii thiu
Ngoi vic vit chng trnh cu hnh FPGA thng qua code verilog nh
trnh by chng trc th Quartus II cn h tr nhiu cch thit k FPGA khc:
s dng AHDL, EDIF file, SystemVerilog HDL file, Tcl Script file trong th
cch thit k s dng s khi, s dng trc tip cc khi lun l l mt trong
nhng cch kh thng dng. Di y s trnh by mt v d thit k FPGA thng
qua m hnh s khi.
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Bc 3.
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Ca s lm vic
Thanh cng c
Ca s project
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Bc 7. Tip tc chn
(Symbol tool), trong ca s la chn linh kin
bn chn ng dn primitives -> pin -> input, sau bn c 2 tn hiu
ng nhp. Lp li qu trnh ny c thm mt tn hiu output nh hnh
bn di
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II. Bi tp
Bi 1. Hy hin thc hm F (khng rt gn) ln FPGA bng phng php thit
k s khi, tn hiu nhp c a vo t cc SW, v tn hiu xut l cc
LEDR. Rt gn hm F, v m hnh transitor v kim tra li kt qu hm rt
gn vi kt qu chng trnh chy trn FPGA. Vi hm F nh sau:
a. F a(b c d )(a bc)
b. F a(c b) ad bcd
Bi 2. Ch s dng tnh cht ca hm Boole bin i biu thc F thnh dng
tng cc tch (SOP) v tch cc tng (POS), vi F
a. F a(b c)(a c)
b. F a(b c) d bc
Bi 3. S dng phng php Ba Karnaugh
a. Rt gn hm F (a, b, c, d ) m(0,1, 4, 7, 8,11,15) d (2,13) v dng tng
cc tch (SOP)
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Bui 3.
Khoa KH&KTMT
2. Ci t
tin hnh ci t bn ln lt thc hin cc bc sau:
Bc 1. Nu bn cha c file ci t th c th down load file ci t ti
https://www.altera.com/support/software/download/eda_software/modelsim/msmindex.jsp. Bn chn phin bn web 6.1g
Bc 2. Sau khi c file ci t bn nhp p chut vo file ny. Ca s ci t
s xut hin.
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Bc 3.
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Bc 4.
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Bc 6.
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a ch card mng
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3. Hng dn
Di y s l quy trnh son tho mt project vi ModelSim.
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Bc 8. Hnh v trn cha code verilog hin thc mt cng AND 2 ng nhp. Sau
khi g xong code verilog bn nhp vo nt
trn thanh cng c bin dch
chng trnh. Ca s lnh s cho bit chng trnh bin dch c thnh cng hay
khng (xem hnh).
Bc 9. Tip theo kim th ta phi hin thc thm file testbench. File
TestBench ny s s dng chng trnh chnh (cng AND) nh l mt linh kin
th vin, v nhim v chnh ca file testbench l lm sao to ra y cc kh
nng c th kim tra tnh ng n ca linh kin test. Cc bc tip theo y
s l quy trnh to ra file testbench.
Bc 10.To mi mt file bn vo File->New->Source->Verilog to mi file
verilog (xem hnh).
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Bc 15.Bin dch file testbench sau nhp vo tab Library. Ton b file trong
project s c bin dch vo th vin word. Bn m th vin ny s thy cc
file va mi to (xem hnh).
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II. Bi tp
Bi 1. Hin thc b cng Half-adder bng Verilog
Bi 2. Hin thc b cng Full-adder t cc b cng Half-adder s dng Verilog.
Bi 3. Hin thc cc testbench kim th b cng Half-adder
Bi 4. Hin thc testbench kim th cho b cng Full-adder
Bi 5. S dng cc cng primitive thit k mch sau
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Bui 4.
Khoa KH&KTMT
M hnh hnh vi
Mc ch:
Cng c kin thc v HDL v Verilog
Thc hin vic np v kim th trc tip trn FPGA
Nm vng quy trnh thit k FPGA
Lm quen vi DE2
S dng Quartus II
I. Bi tp
Bi 1. Board DE2 cung cp 18 nt gt (SW0-SW17) v 18 n led (LEDR0LEDR17). Hin thc mt module, v np ln board DE2 cho php s dng
cc nt gt iu khin m hoc tt cc n led ny.
Hng dn: thc hin lnh gn:
assign LEDR[17] = SW[17]
assign LEDR[16] = SW[16]
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Hng dn:
-
Hin thc b chn 2-to-1 tng t nh bi 2 (xy dng chng trnh con).
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Hng dn:
-
Ni c2c1c0 vo cc SW[2:0]
Bi 5. Hin thc chng trnh verilog thc hin cc chc nng sau:
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Hnh 94. S kt ni
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Bui 5.
I. Bi tp
Bi 1. Hin thc mt chng trnh verilog thc hin cc chc nng sau:
-
Bi 2. Hin thc b gii m 4 bit thp lc phn thnh 2 s thp phn hin th trn
led 7:
-
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Hng dn:
-
Thit k mch A, nhn tn hiu nhp v2v1v0 v tn hiu xut l bng tn hiu
nhp tr i 2.
Hng dn:
Thc hnh thit kt mch s vi HDL
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Bi 8. Hin thc mch trn board DE2, hin th thng tin ngy thng nm
-
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Bui 6.
My trng thi
Mc ch:
Thit k s dng m hnh my trng thi
Cng c kin thc l thuyt v cc my trng thi Moore v Mealy
Bit cch xy dng mch t cc my trng thi
Nm vng k thut rt gn mt my trng thi
I. Gii thiu
1. Gii thiu
Quy trnh thit k FPGA thng thng kh phc tp i hi ngi thit k
phi thng qua kh nhiu bc phc tp. My trng thi l mt trong nhng bc
trung gian gip cho qu trnh thit k v hin thc code verilog tr nn d dng
hn i vi ngi lp trnh. Thng thng c 2 dng my trng thi: Moore v
Mealy. Tuy nhin trong Quartus ch h tr my trng thi Moore. Bi thc hnh
ny s gip cc bn sinh vin tip cn vi cch thit k HDL theo cch thc ny.
2. Hng dn
to mt my trng thi cc bn thc hin cc bc sau:
Bc 1. M Quartus v to mi mt project (cch to nh trnh by trong bui
u tin)
Bc 2. K tip bn vo File -> New hoc nhp vo biu tng trn thanh cng
c, to mi mt file
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Thanh cng c
Ca s project
Ca s lm vic
e.
f.
g.
h.
i.
(Generate HDL file): Cng c chuyn my trng thi thnh code verilog,
HDL,
j.
(Transition Equation): Cng c n/hin biu thc trn cc cnh chuyn trng
thi
Cc bc tip theo s l quy trnh to ra mt my trng thi c kh nng nhn
din chui 2 bit 1 lin tip. Sau chuyn file ny thnh code verilog.
Bc 5. Bn nhp vo cng c
(State tool) sau v 3 trng thi nh hnh v
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Bc 12. Trong ct Output Port bn chn tn hiu xut, ct Output Value bn thit
lp gi tr xut ra cho trng thi . Sau nhn OK
Bc 13. Lp li thao tc ny cho 2 trng thi cn li.
a. State1: Output Port l output1, v Output Value l 0
b. State2: Output Port l ouput1, v Output Value l 0
c. State3: Output Port l output1, v Output Value l 1
Bc 14. Cui cng bn s c my trng thi nh hnh v:
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Hnh 107. Chuyn my trng thi sang nh dng ca ngn ng thit kt phn cn
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II. Bi tp
Bi 1. Cho s my trng thi sau:
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