Power Network Analysis

Guide: Dr MS Hashmi Author: Abhishek Jain

Mentor: Nitin Bansal MT-13151
Motivation:
Important question that needs to be answered is the performance degradation in using the
common power supply or we have to use the dedicated power supply for all the devices






The whole project work is divided into 3 parts:
1) Characterizing the supply noise:
2) How to define output error
3) How to do analysis
a) For a given supply noiseerror we are getting
b) For a given errorwhat supply noise can be tolerated


Output error

Supply noise

Sensors are being taken under test as it involves mixed IP
Sensors
PLL ADC/DAC PHY
Sensors
Work done so far:
Literature survey on characterizing a supply noise:
Since supply noise is not a periodic signal Fourier transform tool needs to be expertise. Fourier
series along with Fourier transform is studied for understanding noise. The major concern is the
method of defining supply noise or to give a supply noise. Need to justify certain set of
parameters that are required to define supply noise
Noise in Deep submicron technology:
Noise can be defined as anything that causes the voltage of an evaluation node to deviate from
the nominal supply or ground rails when it should otherwise have a stable high or low value (i.e.,
the node is not switching) as determined by the logic and delay of the circuit. Noise can be
characterized by its peak magnitude relative to the nominal supply and ground rails and its
behavior in the time-domain. Noise sources that reduce an evaluation node voltage below the
supply level (VDD) are denoted VH, while noise sources that increase an evaluation node
voltage above the ground level (GND) are denoted VL. Noise may also be bootstrapping if it
increases a node voltage above the supply level (Vdd) or below the ground level.
Noise sources in digital systems
The noise sources most relevant to digital design are leakage noise, power supply noise, charge-
sharing noise, and crosstalk noise.
Leakage noise.
Leakage noise is due to the off current of FETs, which allows charge to drain from or
accumulate on the dynamic node. This is largely due to subthreshold current and is directly
determined by the threshold voltage and the temperature. Another leakage noise source is
minority carrier back-injection into the substrate due to bootstrapping. This is sometimes referred
to as substrate noise. Leakage noise is a DC noise source because it changes the steady-state
logic high or low voltage value on a time scale which is slowly varying with respect to the
system clock

Charge sharing and cross talk noise
Charge-sharing noise is produced by charge redistribution between a dynamic evaluation node
and internal nodes of the circuit. Crosstalk noise is the voltage induced on a node due to
capacitive coupling to a switching node of another net. Both crosstalk and charge-sharing noise
are pulse noise sources, in which the leading edge is determined by a switching signal on the
chip and the trailing edge is determined by the node impedance charging or discharging the
capacitance of the evaluation node.

Power Supply noise
Power supply noise explicitly refers to noise appearing on the supply and ground nets of the chip
and coupled onto evaluation nodes through a FET conduction path. Power supply noise contains
both a DC and sinusoidal content. The DC component of power supply noise is produced by the
IR drop through the power and ground nets. The sinusoidal component of power supply noise
comes from the RLC response of the chip and package to current demands that peak at the
beginning of the clock cycle. Since power supply variations vary slowly relative to circuit
Frequency response, they are generally treated as DC for analysis purposes.

Noise in digital dynamic cmos circuits
Dynamic logic has advantages of higher speed, lower area, low power consumption but has a
drawback of noise.

There are three main differences between static and dynamic logic considering noise:
1) Static logic may recover from noise induced logic errors if there is no loop in a circuit. Notice
however that a static D flip-flop has a feedback loop that cannot recover from noise induced
errors. Precharged dynamic logic cannot recover if the precharged node has been discharged by a
noise pulse.
2) Static logic contains both N and P structures that can be balanced to obtain highest possible
noise margin. This is not the case for dynamic logic, which might have a noise margin as low as
Vt.
3) Highly synchronous logic will generate large current pulses by precharging and evaluating
many nodes simultaneously causing dI/dt noise. If many nodes are precharged in dynamic logic,
the noise levels might be higher than for static logic.


Scaling of Mosfets leads to higher speed and lower area, but leads to higher demands on
material, packaging, and interconnections.
A discrete capacitor inside a package and on-chip decoupling capacitance have been proven
efficient to reduce noise. Adding decoupling capacitance on a chip may give resonance
oscillations in the power distribution network. This may cause noise accumulation with
unexpectedly large noise amplitude.